JPS6262395B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic cash register equipped with a timekeeping means.

[Prior Art] Conventionally, technology related to switching functions of data processing devices such as electronic cash registers has been disclosed in Japanese Patent Application Laid-Open No. 1986-
There is a technique disclosed in Publication No. 69950. This conventional technology is equipped with a mode switch that can be operated by a key held by an operator, and by switching this mode switch, various functions such as setting, registration, return, inspection, and payment are selected. There is. That is, in conventional electronic cash registers, the mode switch is set to, for example, the registration position to register each department, and the mode switch is also set to, for example, the return position to correct the previously registered data. etc. Therefore, by simply switching the mode switch, the operator can select and change each function at any time according to his will.

[Problems to be Solved by the Invention] However, it is important for a cash register machine to prevent errors in cash payment processing due to erroneous key operations, etc., and high accuracy is required. However, with the above-mentioned conventional devices in which each function can be selected at any time simply by operating a mode switch, errors in the stored data in the cash register may occur due to key operation errors, etc. There is a risk that discrepancies may occur between the parties, making it impossible to obtain a high degree of accuracy in the payment and disbursement processing of money.
Furthermore, since the selection of each function can be switched at any time, the contents stored in the cash register can be changed freely, making it easy for unauthorized use, which is also a problem in terms of security.

An object of the present invention is to store a time slot in which a specific process is possible, and to enable the specific process to be performed only when an instruction to perform the specific process is given during this time slot.

[Means for solving problems] The means of the present invention are as follows.

1 (see the functional block diagram in FIG. 8, the same applies hereinafter) is a timekeeping means for measuring the current time, 2 is an instruction means such as a key for instructing to perform a specific process such as payment, and 3 is this instruction means 2. 4 is a time zone storage means for storing a time zone such as 7:00 p.m. to 7:30 p.m. in which a specific processing operation can be performed according to an instruction from the timer means 1; A determining means 5 reads out the current time from the time zone storage means 3 and reads out a time zone such as, for example, 19:00 to 19:30 from the time zone storage means 3, and determines whether or not the current time is included in this time zone. This determination means 4
Processing means for invalidating the instruction by the instruction means 2 when it is determined that it is not included, and carrying out a specific process instructed by the instruction means 2 when it is determined that it is included by the determination means 4. It is.

[Effect] The operation of the means of the invention is as follows.

The current time is measured by the clock means 1.
In this state, when the instruction means 2 issues an instruction to perform a specific process, the current time is read out from the timekeeping means 1, the time zone stored in the time zone storage means 3 is read out, and the determination means 4, it is determined whether or not the current time is included in this time zone, and when the determination means 4 determines that the current time is not included, the processing means 5 invalidates the instruction by the instruction means 2; When the determination means 4 determines that the information is included, the processing means 5 performs the specific processing instructed by the instruction means 2.

Therefore, specific processing can be performed only during the memorized time period, and inadvertent errors and unauthorized use can be prevented.

[Example] An example will be described below with reference to FIGS. 1 to 7.

First, the configuration of the front operation section 10 of the electronic cash register will be explained with reference to FIG. In FIG. 1, 11 is an amount key for entering the amount of the product, 12 is a department key for specifying the department for each product, and 13 is a department key for specifying the department for each product.
a is a correction key, 13b is a subtraction key, 13c is a key to temporarily save the data currently being registered or call up saved data, 13d is a key to specify non-addition or exchange, 13e is a key to register the responsible person number,
13f is a key for setting date and time data; 14 is a transaction key for instructing deposits, withdrawals, credit sales such as credit sales, and lending sales; 15 is a subtotal key for adding or calculating a total; 16 is a key for calculating a total or change. This is the key to issue a receipt. Further, a mode switch 17 switches and selects each function of "OFF", "Registration", "Return", "Inspection", "Payment", and "Setting". ``OFF'' in the mode switch 17 is when the cash register is not in use, and ``REGISTER'' is when performing normal money collection operations.
"Return" is used to cancel part of the money registered in the cash register, "Inspection" is used to read the stored data without destroying it, "Payment" is used to clear the stored data after reading it, and "Settings" is used to cancel part of the money registered in the cash register. Used when setting data for presets.

Next, the system configuration of the present invention will be explained with reference to FIG. In Fig. 2, 21 is a CPU (arithmetic processing unit), and this CPU 21 includes a memory circuit 2.
2 and a clock circuit 23 are connected via a data bus D8 for transferring data D, a row address bus RB for transferring row addresses RA, and a column address bus CB for transferring column addresses CA. The memory circuit 22 and clock circuit 23 are each formed of an integrated circuit, and chip designation is performed by chip enable signals CE ₁ and CE ₂ sent from the CPU 21, and read/write signals R/W. ₂ specifies reading or writing. In addition, the above CPU21 is a data bus
An I/O port 24 is connected via DB and column address bus CB. This I/O port 24 has
An operation signal J is given from the CPU 21. A key input section 25, a display section 26, and a printing section 27 are connected to the I/O port 24. When the key input section 25 performs a key operation,
A key input signal KI is input to an input buffer (not shown) in the I/O port 24 in accordance with a timing signal KP from the I/O port 24 . Further, the display section 26 performs a display operation in accordance with the digit signal DG from the I/O port 24 and the segment signal SG obtained by decoding data in a display buffer (not shown) of the I/O port 24. Printing section 27
For example, a line printer sends a print position signal T of a print drum to the I/O port 24, and by matching this print position signal T with data in a print buffer (not shown) of the I/O port 24, The hammer is driven by the generated hammer drive signal MD to perform printing on receipt paper and journal paper.

Next, according to Figures 3 to 6, the above CPU2
1. Details of the clock circuit 23, alarm circuit 28, and memory circuit 22 will be explained. Figure 3 shows the CPU
21 is a circuit block diagram showing the details of the circuit 21. In the figure, 31 is a control section in which various microinstructions are stored. Then, from the control unit 31, a signal SU designating a row address of a register storing an operand of a RAM 32, which is an arithmetic memory to be described later;
Signal SL that specifies the column address of the register that stores the operation number or the processing start column address; Signal FL that specifies the column address of the register that stores the operation number or the processing end column address; Numerical code signal CO; Operation An operation code OP such as a command or a transfer command, and a signal NA specifying the next address of the device are outputted in parallel via bus lines a to g, respectively. The signal NA output via the bus line g is temporarily stored in the buffer register 33 via the address conversion circuit 30. The output of the buffer register 33 is input to the address section 34. The address section 34 specifies the address of the control section 31 in accordance with a signal input from the buffer register 33. Further, the operation code OP is supplied to the operation decoder 35 via the bus line f. This operation decoder 35 is an operation code
OP is decoded and given to the timing control circuit 36. This timing control circuit 36 generates gate control signals to gate circuits 38 and 39 in accordance with a command from an operation decoder 35 and a timing signal given from a timing signal generation circuit 37.
To, up/down count command is counter 40
, a match detection command goes to the match circuit 41, an addition/subtraction command goes to the adder circuit 46, a judgment command goes to the address conversion circuit 30, a read/write command R/W ₁
is output to RAM32. Furthermore, the read/write command R/W ₂ is sent to the memory circuit 22 and the clock circuit 23, and the operation signal is sent to the I/O port 2.
4 and the alarm circuit 28.

The row designation addresses SU and FU output from the control section 31 are applied to the gate circuit 38 via bus lines a and b, respectively, and the outputs of these gate circuits 38 are sent to the RAM RAM via the bus line h.
32 to the row address input terminal UA. Further, the column address or processing start column designation address SL and column address or processing end designation address FL of the RAM 32 output from the control unit 31 are sent to the gate circuit 3 via bus lines c and d, respectively.
Added to 9. The output of the gate circuit 39 is outputted to the bus line i, inputted to the column address input terminal LA of the RAM 32, and outputted to the outside as the column address CA. Further, the output of the gate circuit 39 is supplied to a counter 40. This counter 40 performs a counting operation based on a predetermined timing signal, and normally counts up by one each time a timing signal is input, but when a down-count command is given from the timing control circuit 36, Counts down by 1 each time a signal is input. The output of the counter 40 is applied to the column address input terminal LA of the RAM 32 and the external memory, and is also applied to one input terminal of the matching circuit 41. The other input terminal of the matching circuit 41 is given the processing end column designation address FL output from the control section 31 to the bus line d. This matching circuit 4
The coincidence output of 1 is input to the timing control circuit 36.

On the other hand, the RAM 32, which is the arithmetic memory, is provided with registers A, B, and C, for example. These registers A, B, and C are the row specified address FU.
Alternatively, it is addressed by the row address output from SU. Furthermore, the digits of each of the above registers are designated by the column designation address FL or SL, and reading and writing are performed by the timing control circuit 3.
It is designated by the read/write command R/W ₁ output from 6. Therefore, the operands and operands addressed by the above row and column addresses,
Alternatively, data read for transfer etc. is output as parallel 4-bit data from the output terminal OD, and is passed through the gate circuit 42 to the latch circuit 43,
Sent to 44. The output of the latch circuit 43 is sent to an adder circuit 46 via a gate circuit 45.
The signal is supplied to input terminal b of , and is also sent to buffer 47 . This buffer 47 reads an input signal according to a predetermined timing signal, and its output is outputted to the outside as a row address RA. Further, the output of the latch circuit 44 is outputted to the data bus DB via the gate circuit 48, and is also output to the adder circuit 4.
6 and a predetermined timing signal to a buffer 49 that performs a read operation. The data stored in this buffer 49 is sent to the decoder 50.
decoded by chip enable signal
Output to the outside as CE ₁ and CE ₂ . Further, the carry signal output from the output terminal c of the adder circuit 46 is transmitted from the output terminal d of the adder circuit 46 to the OR circuit 5.
It is input to the address conversion circuit 30 together with the data taken out through the address conversion circuit 30. Furthermore, the adder circuit 46
The data output from the output terminal d of the data bus
It is applied to the gate circuit 52 together with data input from the outside via DB, and the output of this gate circuit 52 is applied to the data input terminal ID of the RAM 32. The gate circuit 52 and the gate circuit 3
8, 39, 42, 45, and 48 are controlled by a signal output from the timing control circuit 36.

FIG. 4 shows the details of the clock circuit 23. In the figure, 61 is an oscillator that generates a reference pulse signal of, for example, 32 kHz, and its oscillation output is sent to a frequency division counter 62 and frequency-divided. This frequency division counter 6
2 consists of 15 bits, for example, and the input 32k
The frequency of the Hz signal is divided sequentially, and finally the frequency is divided to a 1 Hz signal. The bit outputs of 8 kHz and 4 kHz divided by the frequency division counter 62 are sent to an AND circuit 63, the bit outputs of 2 kHz to 256 Hz are sent to an AND circuit 64, the bit outputs of 128 Hz to 32 Hz are sent to an AND circuit 65, and the bits of 16 Hz/1 Hz are sent to an AND circuit 65. Output is zero detection circuit 6
Added to 6. This zero detection circuit 66 detects the state in which all bit outputs of the frequency division counter 62 from 16Hz to 1Hz become zero and outputs a "1" signal, and the detection output is gate-controlled to the AND circuits 63 to 65. Added as a signal. The output of the AND circuit 63 is applied to a bit decoder 67, the output of the AND circuit 64 is applied to a digital decoder 68, and the output of the AND circuit 65 is applied to a word decoder 69. Thus, the output of the digital decoder 69 is input to the control circuit 70. and,
The output of the digital decoder 68 is input to the gate circuit 71b together with the column address CA sent from the CPU 21 as a column address. Further, the word decoder 69 is provided with output lines a and b that output the 128 Hz and 64 Hz bits of the frequency division counter 62 input through the AND circuit 66, and the signal output from the output line a is used for reading/writing. A signal applied to gate circuit 71c as a command and output from output line b is applied to gate circuit 71a as a row address. In addition, the gate circuit 7
The read/write command R/W2 from the CPU 21 and the chip enable signal _CE2 are inputted to 1c via the AND circuit 86, and the gate circuit 71a is inputted to the gate circuit 71a.
A row address RA is input from the CPU 21. The gate circuits 71a to 71c include a zero detection circuit 66
Gate switching is performed by the zero detection signal sent from the CPU 21, and when the zero detection signal is "0", the
2, CE ₂ is selected and output, and when the zero detection signal is "1", the signals from the digital decoder 68 and word decoder 69 are selected and output. The outputs of the gate circuits 71a to 71c are input to a RAM 72 that stores alarm setting data and current time. For example, this RAM 72 has a configuration of 2 rows and 16 columns as shown in FIG.
The current date and time data of year, month, day, hour, minute, and second are written in columns 11 to 0, and columns 15 to 12.
Timer setting data for 10 o'clock, hour, 10 minutes, and minutes is written in the column. In addition, the first row of RAM 72 has 15 columns,
10 ³ o'clock, 10 ² o'clock timer setting data in column 14, column 13 ~
Hour and minute time data for three types of alarms AL3 to AL1 are written in the second column, and an alarm flag ALF is written in the 0th line. This alarm flag ALF indicates whether or not the alarm setting data AL1 to AL3 match the current time.The 3 bits in the 0 column are used to indicate whether or not the alarm setting data AL1 to AL3 match the current time. Set a "1" signal to the corresponding bit. RAM7 configured as above
As shown in FIG. 4, write data sent via the data bus DB is input to 2 through the gate circuit 73a, and read data is input to the gate circuit 73a.
The signal is sent to the P-S (parallel-to-serial) conversion circuit 74 via the P-S (parallel-to-serial) conversion circuit 74 via the signal line b, and is also input to the all "1" write circuit 75. This all "1" write circuit 75 operates in synchronization with the zero detection circuit 66, and generates a busy signal when the zero detection signal becomes "1" and the clock circuit 23 is accessing the RAM 72. Its output is sent to the data bus DB. When the CPU 21 accesses the RAM 72 of the clock circuit 23, it uses the all “1” write circuit 75.
The operating state of the clock circuit 23 is controlled from the output signal of the clock circuit 23, and the clock circuit 23 accesses the RAM 72 when the RAM 72 is not in use.

Therefore, the output of the P-S conversion circuit 74 is
A gate circuit 77 is added to the match circuit 76 and is controlled by the output of the word decoder 69.
The signal is input to a 4-digit shift register 78a via the 4-digit shift register 78a. The output of this shift register 78a is sent to a matching circuit 76 and an 11-digit shift register 78
b. This shift register 78b is
Each bit output is sent to the control circuit 70, and the final bit output is input to the input terminal a of the half adder 79. Also, this half adder 79
A +1 signal is input from the control circuit 70 via the OR circuit 80 to the input terminal b of the control circuit 70 . The carry output of the half adder 79 is applied to its own input terminal b via a 1-bit delay circuit 81 and an OR circuit 80. The addition output of the half adder 79 is then sent to a 1-digit (4-bit) shift register 78c.
is input to. Each bit output of this shift register 78c is sent to the control circuit 70, and the final bit output is returned to the shift register 78a via the gate circuit 77. The shift registers 78a to 78c constitute a clock register 78, and the shift operation is controlled by the timing pulse output from the bit decoder 67. The output of the matching circuit 76 is input to flip-flops 82a to 82c for storing matching outputs. These flip-flops 82a-8
2c, the operation timing of which is controlled by a signal from the control circuit 70, so that they operate at different timings. That is, the coincidence or mismatch between the three types of alarm data stored in the RAM 72 and the current time is stored in the flip-flops 82a to 82c.
The outputs of the flip-flops 82a to 82c are:
S-
It is sent to a P (serial-parallel) conversion circuit 85. Further, the output of the shift register 78c is input to this S-P conversion circuit 85 via a gate circuit 84. The S-P conversion circuit 85 converts the input serial data into parallel data, sends it to the RAM 72 via the gate circuit 73a, and writes the current time and alarm flag ALF. Gate circuit 73
Gates a and 73b are switched by the zero detection circuit 66 sent from the zero detection circuit 66, and when the zero detection signal is "0", data is transferred to and from the data bus DB. When the zero detection signal is "1", the gate is switched so that data is transferred to and from the P-S conversion circuit 74 and the S-P conversion circuit 85.

In the clock circuit 23 configured as described above, current date and time data are initially written in accordance with key operations on the key input section 25. That is, by performing key operations for setting the date and time on the key input unit 25, the I/O port 2
Data is input into an input buffer (not shown) in 4. The CPU 21 writes the data in the input buffer to the RAM 32, and detects whether a busy signal is output from the all "1" write circuit 75 of the clock circuit 23. At this time, if there is no busy signal, a chip enable signal is sent from the CPU21.
CE ₂ , write command R/W2, row address RA, column address CA as well as date and time data are stored in RAM
72, and the current year, month, day, hour, minute, and second data are written in the 0th row, 11th column to 0th column.
Also, alarm data is stored in RAM72 in the same way.
Writing of AL1 to AL3, timer data TM, etc. is performed. Then, when the zero detection circuit 66 detects all "0" and the zero detection signal becomes "1", the gate circuits 71a to 71c, 73a, 73b
is switched to transmit and receive data within the clock circuit 23, and timekeeping operation is started. That is, the reference pulse signal outputted from the oscillator 61 is frequency-divided by the frequency division counter 62, and a predetermined frequency-divided output is inputted to the AND circuits 63 to 65 and the zero detection circuit 66. This zero detection circuit 66 is connected to the frequency division counter 62.
It detects the state in which all bit outputs from 16Hz to 1Hz become "0" and outputs a "1" signal. The 16Hz to 1Hz bit output of the frequency division counter 62 is output every second.
All bits become "0" for 1/32 second, and at that time a "1" signal is output from the zero detection circuit 66 and the gates of AND circuits 63 to 65 are opened. As a result, predetermined bit outputs of frequency division counter 62 are input to decoders 67-69 via AND circuits 63-65, and timing signals and address data are sent from each decoder 67-69 to the circuits. That is,
The output of the bit decoder 67 is sent to the clock register 78 as a shift signal, and the output is sent to the clock register 78 as a shift signal.
The output can be sent to the control circuit 70 as a timing signal and also via the gate circuit 71b.
It is sent to RAM 72 as a column address. Also,
The output of the word decoder 69 is sent to the control circuit 7
0 and the gate circuit 77 as a control signal. Furthermore, lines a and b of the word decoder 69
The signals outputted from are read/write commands and row addresses via gate circuits 71c and 71a.
Sent to RAM72. Therefore, while the zero detection circuit 66 is outputting a "1" signal, the bit output of the frequency division counter 61 from 128Hz to 32Hz is "000".
Changes in 8 steps from ~111. For example, the data of the first four stages of these eight stages, that is, 128Hz
and 64Hz bits are “00”, “10”, “01”, “11” and 4
Data is read from and written to the RAM 72 by utilizing the step change. The word decoder 69 outputs four types of signals "00" to "11" from output lines a and b in response to the 128 Hz and 64 Hz bit outputs of the frequency division counter 61. First, the output lines a of the word decoder 69,
Both outputs of b are “0”, and in read mode
The 0th row of the RAM is addressed and the output of the digital decoder 68 specifies the column address. Therefore, the date and time data on the 0th row of the RAM 72 is read out, converted to serial data via the gate circuit 73b and the P-S conversion circuit 74, and inputted to the time register 78 via the gate circuit 77. Then, under the control of the control circuit 70, the half adder circuit 79 adds 1 to the second data. Next, the signal becomes "1" which is output from the output line a of the word decoder 69.
Give a write command to RAM72. As a result, the date and time data read out to the clock register 78 and incremented by one second are written into the RAM 72. Note that if a carry occurs due to the operation for +1 second, the carry processing is performed under the control of the control circuit 70. Next, when the outputs of the output lines a and b of the word decoder 69 change to "01", the first row of the RAM 72 is designated in the read mode, and the alarm data AL1 to AL3 stored in the first row are read out. This alarm data AL1-AL3 is applied to the coincidence circuit 76 via the gate circuit 73b and the P-S conversion circuit. In addition, the time matching circuit 76 also includes a shift register 78 of the time register 78.
The current time in hours and minutes, which is cyclically held, is input to part a through the gate circuit 77. The coincidence circuit 76 reads the alarm data AL read from the RAM 72.
1 to AL3 are sequentially compared with the current time, and if they match, "1" is set in the corresponding flip-flops 82a to 82c. Then word decoder 69
When the output of output lines a and b changes to "11",
RAM 72 changes to write mode with the first row specified, and flip-flops 82a to 8
The output of 2c is the output gate 83, the gate circuit 84,
Via the S-P conversion circuit 85 and gate circuit 73a
It is sent to the RAM 72 and written to the arm flag ALF in the 1st row and 0th column. Therefore, the CPU 21 can determine whether the current time has reached the alarm time by checking the contents of this alarm flag. Thereafter, a clocking operation of +1 second is performed every second and a coincidence detection between the alarm data and the current time is performed in the same manner.

FIG. 6 is a diagram showing the stored contents of the memory circuit 22 in FIG. 2. For example, the memory circuit 22 has 16
In the row structure, sales data for departments 1 to 8 are stored in the 0th to 7th lines. For example, 15 to 12 in lines 0 to 7
The unit price of the sold product is stored in the column, the number of sold items is stored in the 11th to 18th columns, and the total sales by department is stored in the 7th to 0th columns.
Further, in other areas of the memory circuit 22, data on various types of sales, such as the number of deposits and withdrawals, the total number of deposits and withdrawals, etc., are stored.
In the 15th to 12th columns, times RST ₁ and RST ₂ are stored, which indicate the operational time period for a specified key such as payment. RST ₁ above is the start time of the operational time zone,
RST ₂ indicates the end time of the operable time zone. Thus, when a function is selected using a specific key, the CPU 21 determines whether or not the operation is possible by comparing the current time with the set times RST ₂ and RST ₂ of the operable time zone.

The operation will be explained below with reference to the flowchart shown in FIG.

FIG. 7 shows a flowchart when a time lock is applied to the payment function.
When the key 16 for printing payment data is operated with the master switch 17 switched to a specific function, that is, the payment position, the CPU 21
As shown in step A of the figure, the clock circuit 23
Current time (hours, minutes) stored in RAM72
Read CLK and set it in the register in RAM32. Then, proceeding to step B, the memory circuit 22
Start time of the operable time zone stored in RST ₁
is read and set in the B register in the RAM 32, and the stored digits are read as shown in step C.
Shift down by 10 digits to match the data storage digit positions of the A register and B register. After that, proceed to step D, subtract the memory contents of the B register from the memory contents of the A register, and determine which is greater between the current time CLK stored in the A register and the set time stored in the B register, and A<B If so, it is determined that there is no answer, that is, the key input data is invalid. For example, if the closing time is 19:00 and payment processing is to be performed within 30 minutes after closing, RST ₁ is 19:00.
time, RST ₂ is set at 19:30. If the payment key is operated by mistake at, for example, 18:00, it is determined in step D that A<B, that is, the current time 18:00 is smaller than the set time of RST _1, 19:00, and the no-functions button is pressed. becomes. Also, if it is determined that A≧B at slap D, that is,
If the settlement key is operated after 7:00 pm, the process proceeds to step E, where the set time RST ₂ is read from the memory circuit 22 and set in the B register in the RAM 32. Then, as shown in step F, the contents of the B register are incremented by 10 digits to match the contents of the A register with the stored digits. Thereafter, the process proceeds to step G, where "A-B" is subtracted to determine the magnitude of A and B. The judgment result is A>B, that is, the current time
If CLK is past the set time RST ₂ (7:30 p.m.), a no-function occurs. However, if it is determined in step G that A≦B, that is, the current time is past the set time RST ₂ (7:30 p.m. If it is determined that the time is before (minutes), proceed to step H and perform the payment process.The time when the payment key was operated in this way
CLK is within the set time range, that is, "RST ₂ ≦CLK≦
Settlement processing is performed only when the conditions of ``RST ₁ '' are satisfied. In the above embodiment, a case has been described in which payment processing is performed, but it is also possible to set the operating time for other keys, such as a key for inspection, for example.

[Effects of the Invention] According to the present invention, even if a key or the like is inadvertently operated, the probability of malfunction can be significantly reduced, and the accuracy of data processing can be greatly improved. It also helps prevent unauthorized use and is effective in terms of safety.

[Brief explanation of the drawing]

Figures 1 to 7 show one embodiment of the present invention, with Figure 1 being a diagram showing the arrangement of keys on the front operation section, Figure 2 being a system diagram showing the overall circuit configuration, and Figure 2 being a system diagram showing the overall circuit configuration. Figure 3 is a circuit diagram showing details of the arithmetic processing unit (CPU) in Figure 2, Figure 4 is a circuit diagram showing details of the clock circuit in Figure 2, and Figure 5 is a circuit diagram showing details of the clock circuit in Figure 4. FIG. 6 is a diagram showing an example of the memory contents of the memory circuit in FIG. 2, FIG. 7 is a flowchart for explaining the operation of the present invention, and FIG. 8 is a functional block diagram of the present invention. It is a diagram. 10...Operation unit, 21...CPU, 22...Memory circuit, 23...Clock circuit, 24...I/O port.

Claims (1)

[Claims] 1. A timekeeping means for measuring the current time, an instruction means for instructing to perform a specific process, a time zone storage means for storing a time zone, and an instruction for performing a specific process by the above-mentioned instruction means. determining means for reading the current time from the timekeeping means and reading a time zone from the time body storage means to determine whether or not the current time is included in the time zone; and processing means for invalidating the instruction by the instruction means when determined, and performing a specific process instructed by the instruction means when determined to be included by the determination means. Electronic cash register.