JPS6072236A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6072236A
JPS6072236A JP58179557A JP17955783A JPS6072236A JP S6072236 A JPS6072236 A JP S6072236A JP 58179557 A JP58179557 A JP 58179557A JP 17955783 A JP17955783 A JP 17955783A JP S6072236 A JPS6072236 A JP S6072236A
Authority
JP
Japan
Prior art keywords
area
mounting part
semiconductor element
fixed
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58179557A
Other languages
Japanese (ja)
Inventor
Masahiko Sakurai
桜井　正彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58179557A priority Critical patent/JPS6072236A/en
Publication of JPS6072236A publication Critical patent/JPS6072236A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To eliminate the stripping of elements or the generation of cracks by a method wherein the frame area of an element-mounting part is set at 20-60% of the element area, where the following element is then fixed with polyimide series paste or solder, when a large-scaled semiconductor element having a side over approx. 6mm. is fixed to the element-mounting part of a copper series lead frame. CONSTITUTION:On the semiconductor element mounting part of the lead frame 22 approx. 0.25-0.4mm. thick, the plane and square semiconductor element 21 is fixed by the use of an adhesive 23, while the centers thereof are adjusted. In this construction, if the element 21 is a large-scaled element having a side over approx. 6mm., its area at the mounting part of the frame 22 is reduced to 20-50% of the element area. Besides, the adhesive 23 composed of polyimide series paste of large adhesion strength or solder is used for fixing the element 21 to the frame 22. Such a manner makes it sufficient that contraction stress is small, even when it acts on the element 21 in the cooling process at the time of fixing, and cracks and the like do not generate in the element 21.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に係シ、特に１辺がほぼ６閣を越え
る大型の半導体素子が銅系リードフレームに載置固着さ
れてなる半導体装置の固着部に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a large semiconductor element with a side of approximately six sides is mounted and fixed on a copper lead frame. Regarding the fixed part.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

第１図（ａ）　、　（ｂ）は従来の半導体装置における
半導体素子１とリードフレームの素子載置部２との固着
状態を示しておシ、エポキシ系ペーストまたは半田３に
よシ半導体素子１の底面全面を固着している。FIGS. 1(a) and 1(b) show how a semiconductor element 1 and an element mounting part 2 of a lead frame are fixed to each other in a conventional semiconductor device. It is attached to the entire bottom surface.

ところで、銅系リードフレーム上に１辺がほぼ６ｍを越
える大型の半導体素子を上述のように固着する場合、固
着温度（高温）から常温までの冷却過程で半導体素子に
相尚大きな収縮応力が働く。したがって、この固着に際
して接着力の小さなエポキシ系ペーストを用いた場合に
は上記収縮応力によシ半導体素子がリードフレームの素
子載置部からはがれ易くなシ、また接着力の大きな半田
とかポリイミド系硬−ストを用いた場合には収縮応力に
よ）半導体素子にクラックが発生し易くなるという問題
があった。By the way, when a large semiconductor element with a side of approximately 6 m or more is fixed on a copper lead frame as described above, a large shrinkage stress is applied to the semiconductor element during the cooling process from the fixing temperature (high temperature) to room temperature. . Therefore, if an epoxy paste with a low adhesive strength is used for this fixing, the semiconductor element will not easily peel off from the element placement part of the lead frame due to the above shrinkage stress, and if an epoxy paste with a low adhesive strength is used, the semiconductor element will not easily peel off from the element mounting part of the lead frame. - When using a semiconductor device, there is a problem in that cracks are likely to occur in the semiconductor device (due to shrinkage stress).

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に鑑みてなされたもので、半導体素
子とリードフレームの素子載置部との固着に際して、半
導体素子が素子載置部からはがれたり、半導体素子にク
ラックが発生することを抑制し得る半導体装置を提供す
るものである。The present invention has been made in view of the above circumstances, and suppresses peeling of the semiconductor element from the element mounting part and generation of cracks in the semiconductor element when the semiconductor element and the element mounting part of the lead frame are fixed together. The present invention provides a semiconductor device that can perform the following steps.

〔発明の概要〕[Summary of the invention]

即ち、本発明は一辺がほぼ６ｍｍを越える半導体素子が
銅系リードフレームの素子載置部上に接着剤により固着
されてなる半導体装置において、素子載置部面積が素子
面積のほぼ２０％乃至６０％であり、接着剤としてポリ
イミド系ペーストまたは半田が用いられてなることを特
徴とするものである。That is, the present invention provides a semiconductor device in which a semiconductor element having a side of approximately 6 mm or more is fixed with an adhesive onto an element mounting part of a copper lead frame, in which the area of the element mounting part is approximately 20% to 60% of the element area. %, and is characterized by using polyimide paste or solder as the adhesive.

〔発明の実施例〕[Embodiments of the invention]

以下、図面を参照して本発明の一実施例を詳細に説明す
る。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

第２図（ａ）　、　（ｂ）において、２ノは１辺がほぼ
６ｍｍを越える平面方形の半導体素子、２２はその中心
部に上記素子２１の中心部をほぼ合わせて載置する銅系
リードフレームの方形平板状の素子載置部であって、そ
の面積は上記素子２ノの面積のほぼ２０％〜６０％であ
る。２３は上記素子載置部２２上に半導体素子２１の底
面中央部を固着する接着剤であり、接着強度の大きなポ
リイミド系ペーストまたは半田が用いられている。In FIGS. 2(a) and 2(b), 2 is a planar rectangular semiconductor element with a side of about 6 mm, and 22 is a copper lead placed with the center of the element 21 approximately aligned with the center of the semiconductor element. This is a rectangular flat element mounting part of the frame, and its area is approximately 20% to 60% of the area of the element 2. Reference numeral 23 denotes an adhesive for fixing the center portion of the bottom surface of the semiconductor element 21 onto the element mounting portion 22, and polyimide paste or solder having high adhesive strength is used.

なお、上記半導体素子２１は厚さがほぼ０．４５ｍｍの
シリコンペレットであシ、リードフレーム２２は厚さが
ｔ”ｉｌ了０．２５間〜０．４団である。The semiconductor element 21 is a silicon pellet having a thickness of approximately 0.45 mm, and the lead frame 22 has a thickness of 0.25 to 0.4 mm.

また、上記のように固着された素子２１は、通常の組立
工程を経てパッケーゾングされ、フラットタイツとかプ
ーアルインラインタイプなどのデバイスとなる。Further, the element 21 fixed as described above is packaged through a normal assembly process to become a device such as flat tights or a puer in-line type.

上記構成の半導体装置によれば、接着強度の大きなポリ
イミド系ペーストまたは半田２３を用いて固着している
ので、固着時の冷却過程で半導体素子２１に縮応力が働
いたとしても、接着強度の小さなエポキシ系ペーストを
用いる場合に比べて半導体素子２１が素子載置部２２が
らはが孔難い。しかも、半導体素子２１の底面面積のほ
ぼ２０条〜６０％の部分を固着するように素子載置部２
２の面積を小さく設定しているので、半導体素子２１に
加わる収縮応力は素子底面全面を固着する場合に比べて
低減し、半導体素子２１にクラッタが発生し難くなる。According to the semiconductor device having the above configuration, since the polyimide paste or solder 23 with high adhesive strength is used for fixation, even if shrinkage stress is applied to the semiconductor element 21 during the cooling process during fixation, even if the semiconductor element 21 is compressed, Compared to the case where an epoxy paste is used, it is difficult for the semiconductor element 21 to break through the element mounting portion 22. Moreover, the element mounting portion 2 is fixed so that approximately 20 to 60% of the bottom surface area of the semiconductor element 21 is fixed.
Since the area of 2 is set small, the shrinkage stress applied to the semiconductor element 21 is reduced compared to the case where the entire bottom surface of the element is fixed, and clutter is less likely to occur in the semiconductor element 21.

以上のことを実際に確認したデータ（素子厚さが０．４
５　ｔｔａｎ、フレーム厚さが０．２５恒のもの）を次
表に示している。即ち、半導体素子２１０面積に対する
素子載置部２２の面積の比をパラメータとし、６０個の
ザンプル素子について素子のはがれおよび素子のクラッ
タのそれぞれの発生個数を示してお、？、２０％〜６０
％の場合はそれぞれ良好であることが分る。Data that actually confirmed the above (element thickness is 0.4
5 ttan, frame thickness 0.25 mm) are shown in the following table. That is, using the ratio of the area of the element mounting portion 22 to the area of the semiconductor element 210 as a parameter, the number of occurrences of element peeling and element clutter for 60 sample elements is shown. ,20%~60
%, it can be seen that each case is good.

なお、本発明は上記実施例に限られるものではなく、第
３図（ａ）　、　（ｂ）に示すように銅系リードフレー
ムの素子載置部３０が方形の環状のものであってもよく
、この環状部の面積、したがって素子底面の固着部の面
積が素子底面積のほぼ９０　≦　〜　パ　０　べｆ訊ｈ
　ぼ前置−宙備層伺１シを斗シマロ櫓の効果が得られる
。なお、第３図（、）　、　（ｂ）において、２１は半
導体素子、２３は接着強度の大きいポリイミド系ペース
トまたは半田である。Note that the present invention is not limited to the above-mentioned embodiments, and the element mounting portion 30 of the copper lead frame may have a rectangular annular shape as shown in FIGS. 3(a) and 3(b). , the area of this annular portion, and therefore the area of the fixed portion on the bottom of the element, is approximately 90 ≦ the area of the bottom of the element.
You can obtain the effect of Dou Shimaro Yagura with Bo Maeji - Sorabi Layokki 1shi. In FIGS. 3(a) and 3(b), 21 is a semiconductor element, and 23 is a polyimide paste or solder with high adhesive strength.

〔発明の効果〕〔Effect of the invention〕

上述したように本発明の半導体装置により、ば、半導体
素子とリードフレームの素子載置部との固着に際して、
半導体素子が素子載置部からはがれたυ、半導体素子に
クラックが発生することを抑制することができる。As described above, with the semiconductor device of the present invention, for example, when fixing the semiconductor element and the element mounting part of the lead frame,
It is possible to suppress the occurrence of cracks in the semiconductor element when the semiconductor element is peeled off from the element mounting portion.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は従来の半導体装置の半導体素子とリード
フレーム素子載置部との固着状態を示す平面図、第１図
（ｂ）は同図（、）の横断面を示す図、第２図（ａ）は
本発明に係る半導体装置の一実施例の要部を示す一部透
視平面図、第２図（ｂ）は同図（、）の横断面を示す図
、第３図（、）は本発明の他の実施例の要部を示す一部
透視平面図、第３図（ｂ）は同図（ａ）の横断面を示す
図である。 ２１・・・半導体素子、２２．３０・・・素子載置部、
２３・・・ポリイミド系ペーストまだは半田。 （ａ） （ａ） （ａ） 第１１や′ｊ （ｂ） 第２図 （ｂ） 第３図 （ｂ）FIG. 1(a) is a plan view showing the fixed state of a semiconductor element and a lead frame element mounting portion of a conventional semiconductor device, FIG. 1(b) is a cross-sectional view of the same figure (,), FIG. 2(a) is a partially transparent plan view showing the main parts of an embodiment of the semiconductor device according to the present invention, FIG. 2(b) is a cross-sectional view of FIG. ,) is a partially transparent plan view showing the main part of another embodiment of the present invention, and FIG. 3(b) is a cross-sectional view of FIG. 3(a). 21... Semiconductor element, 22.30... Element mounting part,
23...Polyimide paste is still soldering. (a) (a) (a) 11th and 'j (b) Figure 2 (b) Figure 3 (b)

Claims (1)

【特許請求の範囲】[Claims] 一辺がほぼ６ｗｎを越える半導体素子を、この−素子の
面積のほぼ２０チ乃至６０％の面積を有する銅系リード
フレームの素子載置部上にテリイミド系ペーストまたは
半田によ）固着してなることを特徴とする半導体装置。A semiconductor element whose side exceeds approximately 6wn is fixed (by terimide paste or solder) onto the element mounting part of a copper lead frame having an area of approximately 20 to 60% of the area of the element. A semiconductor device characterized by:
JP58179557A 1983-09-28 1983-09-28 Semiconductor device Pending JPS6072236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58179557A JPS6072236A (en) 1983-09-28 1983-09-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58179557A JPS6072236A (en) 1983-09-28 1983-09-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6072236A true JPS6072236A (en) 1985-04-24

Family

ID=16067816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58179557A Pending JPS6072236A (en) 1983-09-28 1983-09-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6072236A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6476744A (en) * 1987-09-18 1989-03-22 Hitachi Ltd Resin sealed semiconductor device
EP0617464A3 (en) * 1993-03-22 1995-05-31 Motorola Inc Semiconductor device having a cross-shaped support and manufacturing method.
EP0628997A3 (en) * 1993-06-10 1995-09-06 Texas Instruments Inc Semiconductor device with a thin support and method of manufacturing it.
US5683944A (en) * 1995-09-01 1997-11-04 Motorola, Inc. Method of fabricating a thermally enhanced lead frame
US5903048A (en) * 1996-11-13 1999-05-11 Mitsubishi Denki Kabushiki Kaisha Lead frame for semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133655A (en) * 1981-02-10 1982-08-18 Pioneer Electronic Corp Lead frame
JPS5744551B2 (en) * 1978-09-29 1982-09-21
JPS57211762A (en) * 1981-06-24 1982-12-25 Hitachi Cable Ltd Lead frame for semiconductor
JPS58131740A (en) * 1982-01-30 1983-08-05 Nitto Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744551B2 (en) * 1978-09-29 1982-09-21
JPS57133655A (en) * 1981-02-10 1982-08-18 Pioneer Electronic Corp Lead frame
JPS57211762A (en) * 1981-06-24 1982-12-25 Hitachi Cable Ltd Lead frame for semiconductor
JPS58131740A (en) * 1982-01-30 1983-08-05 Nitto Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6476744A (en) * 1987-09-18 1989-03-22 Hitachi Ltd Resin sealed semiconductor device
EP0617464A3 (en) * 1993-03-22 1995-05-31 Motorola Inc Semiconductor device having a cross-shaped support and manufacturing method.
EP0628997A3 (en) * 1993-06-10 1995-09-06 Texas Instruments Inc Semiconductor device with a thin support and method of manufacturing it.
KR100331666B1 (en) * 1993-06-10 2002-08-14 텍사스 인스트루먼츠 인코포레이티드 Semiconductor device with small die pad and manufacturing method thereof
US5683944A (en) * 1995-09-01 1997-11-04 Motorola, Inc. Method of fabricating a thermally enhanced lead frame
US5903048A (en) * 1996-11-13 1999-05-11 Mitsubishi Denki Kabushiki Kaisha Lead frame for semiconductor device

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