JPS5889859A - Fabrication method of micro cantilever on silicon wafer - Google Patents

Fabrication method of micro cantilever on silicon wafer

Info

Publication number
JPS5889859A
JPS5889859A JP56186837A JP18683781A JPS5889859A JP S5889859 A JPS5889859 A JP S5889859A JP 56186837 A JP56186837 A JP 56186837A JP 18683781 A JP18683781 A JP 18683781A JP S5889859 A JPS5889859 A JP S5889859A
Authority
JP
Japan
Prior art keywords
layer
silicon
cantilever
silicon oxide
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56186837A
Other languages
Japanese (ja)
Other versions
JPH0113231B2 (en
Inventor
Keisuke Shinozaki
篠崎 啓助
Michiharu Hosoya
細矢 路晴
Keisuke Watanabe
敬介 渡辺
Yoshio Kawai
義雄 川井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP56186837A priority Critical patent/JPS5889859A/en
Publication of JPS5889859A publication Critical patent/JPS5889859A/en
Publication of JPH0113231B2 publication Critical patent/JPH0113231B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Mechanical Optical Scanning Systems (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明扛、シリコンウェー/S上に、光束を偏向見た
シ、スイッチ動作を行う金−Iili薗を持つ、駿化シ
リ;ンのマイクロ片持ち、梁を形成す石方法に胸するも
のである。
[Detailed Description of the Invention] This invention forms micro-cantilevers and beams of silicon wafer on silicon wafer/S, which have gold-containing wires that deflect and switch light beams. I am passionate about the stone method.

従来のマイク四片持ち梁の作製方法’を第1aclな−
いし絡4図に示す。各図において、(A)は平向−1(
B)は(A)における点線で示す部1分での断thl−
である。
The conventional method for making a four-cantilever microphone beam is explained in the 1st ACL.
The connection is shown in Figure 4. In each figure, (A) is horizontal direction -1 (
B) is the cut thl- at 1 minute in the part indicated by the dotted line in (A).
It is.

この図により従来の方法を説明すると、ます、シリコン
ウェーハ1の表向に高換度の鋤業を一ドーノして°P 
 m2を形成した後へこのP+層2の上に単結晶のシリ
コン層3.をエピタキシャル成長させ、さらに酸化・処
理してシリコンFm30表向に酸、化シリコン層4.t
−形成する。次に、少なくともマイクロ片持 に、電極および銚南を兼ねる金#I薄膜5を形成する。
To explain the conventional method with reference to this diagram, first, a high-concentration plowing operation is applied to the surface of the silicon wafer 1, and then the surface is heated.
After forming the P+ layer 2, a single crystal silicon layer 3. is epitaxially grown and further oxidized and treated to form an acidic silicon oxide layer 4 on the surface of the silicon Fm30. t
- form. Next, a gold #I thin film 5, which also serves as an electrode and a layer, is formed on at least the micro-cantilever.

そして、この金属薄膜5の周囲の酸化シリコン層4t−
凹戯に除去して開口部6Yr形成する。
Then, the silicon oxide layer 4t- around this metal thin film 5
It is removed in a concave manner to form an opening 6Yr.

(第1融参照) しかる後、この−口部−6を利用してシリーン層3の化
学エツチングを行う。この二ツテンダ鉱第2図、第3図
および第4図の朧に進む。すなわち、まず、−口部6に
より露出した部分のシリコン層3がV手製にエツチング
され、以俊、そのV字が次第に深くなると同時に、マイ
クロ片持ち梁となる部分の酸化シリコン#4下のシリコ
ンrfiI3へとエツチングが進む。よって、このエツ
チングを終了すると、前配鮨口部6で囲lれた部分の酸
化シリコン層4(上面に金属薄@5t−有する)が14
29片持ち梁7となる。なお、前記化学エラチンい深さ
となる。
(Refer to the first melting point) Thereafter, chemical etching of the silicone layer 3 is performed using this opening 6. Proceed to the vagueness of this Nitsutenda ore in Figures 2, 3, and 4. That is, first, the portion of the silicon layer 3 exposed by the opening 6 is etched in a V shape, and at the same time, as the V shape gradually becomes deeper, the silicon layer 3 under the silicon oxide #4 in the portion that will become a micro cantilever is etched. Etching progresses to rfiI3. Therefore, when this etching is completed, the silicon oxide layer 4 (having a metal thin layer @5t- on the upper surface) in the area surrounded by the front mouth part 6 has a thickness of 14 mm.
29 cantilever beam 7. Note that the depth of the chemical eratin is greater than that described above.

以上のようにして形成されたマイクロ片持ち梁7鉱、そ
の上面に蒸着しである金iii*膜5とシリ−コンウェ
ーハlとの間に静電場を印加することによル撓み、また
印加電圧によシ纏み量の制御が可能なことから、元偏向
素子中電気スゴツチなどに応用可能である。
By applying an electrostatic field between the micro cantilever 7 formed in the above manner, the gold III* film 5 deposited on its upper surface, and the silicon wafer 1, the beam is deflected. Since the amount of tightening can be controlled by voltage, it can be applied to electrical components in deflection elements, etc.

しかるに、上述したような従来の作製法線、以)に述べ
る大息を有している。まず、P”Jii2を設けるため
に極めて高−11111kK不純物をドープする必要が
あシ、このための専用拡散炉が必要な上、戸FfII2
の上にlOμw&8!度以上もの厚さのシリコン層3t
−エピタキシャル成長させるという極めて高友な技術t
″豐する欠点がある。次に、第2図ないし第4図に示す
単結晶シリコン層3のエツチングを完了するまでには長
時間を叢する上、エツチング速度が結1面方位によって
大きく異なるので、シリコンウェーハ11上に形成され
るiイクロ片持ち采゛7の向き線、特定の結晶面方向に
限られ自由度がない。次に、第4図で示すマイクロ片持
ち*7の下部のJ&面8、すなわち露出した21層2の
上面は蜆面ではなく拡散反射面であるため、光学素子と
して使用する際、底面8からの拡散反射光か、マイクロ
片持ち采7の上面からの正反射光束に°混入する欠点が
ある。
However, the conventional manufacturing normal as described above has a large difference as described below. First, in order to provide P"Jii2, it is necessary to dope extremely high -11111kK impurities, and a dedicated diffusion furnace is required for this purpose.
lOμw & 8 on top! 3 tons of silicon layer with a thickness of more than
- Extremely advanced technology of epitaxial growth
Second, it takes a long time to complete the etching of the single crystal silicon layer 3 shown in FIGS. 2 to 4, and the etching rate varies greatly depending on the crystal orientation. , the orientation line of the i-micro cantilever 7 formed on the silicon wafer 11 is limited to a specific crystal plane direction and has no degree of freedom. Since the surface 8, that is, the top surface of the exposed 21 layer 2, is not a mirror surface but a diffuse reflection surface, when used as an optical element, either the diffuse reflection light from the bottom surface 8 or the specular reflection from the top surface of the micro cantilever holder 7 is generated. The disadvantage is that it mixes into the luminous flux.

この発明紘上記の点に鑑みなされ良もので、上述し良従
−の欠点を解決できるシリ・ンクーー・・上への142
9片持ち梁の作製法を提供することを目的とする。〜 以下この発明の夷11kIpH誓−面を参照して説明す
る。第5図ないしII8図紘ζ0発明の実′1#A例を
示す図である。6図において、(A)は平面図、(B)
は(A)における点−で示す部分での断面図である。
In view of the above points, this invention is a good one and can solve the above-mentioned disadvantages.
The purpose of this paper is to provide a method for manufacturing a 9-cantilever beam. ~ Hereinafter, the present invention will be explained with reference to the 11kI pH aspect. Figures 5 to II8 are diagrams showing an example of the actual invention '1#A'. In Figure 6, (A) is a plan view, (B)
is a cross-sectional view at a portion indicated by a point - in (A).

この図によシ冥施ガを説明すると、まず、一面研磨した
シリコンウェーハ11を酸化処理して、シリコンウェー
ハ11上に約1μ講厚の酸化シリコン層(第109化シ
リ′コンMl)12t−生成する。
To explain the process using this figure, first, a silicon wafer 11 that has been polished on one side is oxidized, and a silicon oxide layer (109 silicon Ml) 12t- generate.

次に、その酸化シリs y @ 12 (D’lRm 
&C1CVD法などによって多結晶シリコン層13を約
20411生成し良後、そのlI!閏を一面研磨して、
多結晶シリコン層13を約lOμII @[0厚さの多
結晶シリコン層とする。その後、傳び酸化IIJ1!1
を行うことによp1多結晶シリコン113のIIl*に
約lμl厚の酸化シリコン層($I2の酸化シリコンj
li)14を生成する。しかる後、少なくともマイク−
片持ち梁となる部分の欧化シリ;ン層14上に金属薄1
115t′形成する。そして、この金属薄1[15の周
囲の酸化シリーンjllJを凹−に除去して一口部16
を形成する。(第5−参照) しかる後、この開口部16を利用して多結晶シリコン層
13ID化学エツチングを行う。このエツチング紘1t
la図、第7図および第8図の類に進む。
Next, the silicate oxide s y @ 12 (D'lRm
&C1 After approximately 20,411 layers of polycrystalline silicon layer 13 are formed by the CVD method, the lI! Polish one side of the screw,
The polycrystalline silicon layer 13 is a polycrystalline silicon layer having a thickness of about lOμII@[0. After that, Denbi Oxidation IIJ1!1
By doing this, a silicon oxide layer ($I2 silicon oxide j
li) Generate 14. After that, at least Mike-
Metal thin layer 1 is placed on the European silicon layer 14 of the part that will become the cantilever.
115t' is formed. Then, the oxidized silicone around the thin metal 1 [15 is removed in a concave manner to form the mouth portion 16.
form. (See No. 5-) Thereafter, chemical etching of the polycrystalline silicon layer 13ID is performed using this opening 16. This etching Hiro 1t
Proceed to figures la, figures 7 and 8.

すなわち、まず、−口部16によル無出した部分の多結
晶シリコン層13が浅くエツチングされ、以後、そのエ
ツチング渫さが次第に旅くな諷と同時に、マイクロ片持
ち梁となる部分の酸化シリーン層14下の多結晶シリコ
ン層l・3へとエツチングが進む。よって、このエツチ
ングが終了すると、前1e−ロ部16で囲まれた部分の
酸化シリーン層14(上面に金属薄1115に有する)
がiイクレ片持ち梁17となる。・なお、前記化学エツ
チングは酸化シリコン112で阻止される九め、142
9片持ち采17の下の空間の深さ嬬、多結晶シリコン層
13の厚さと等しい櫟さとなる。
That is, first, the portion of the polycrystalline silicon layer 13 that is not exposed by the opening 16 is etched shallowly, and then the etching process gradually slows down and at the same time, the portion that will become the micro cantilever is oxidized. Etching progresses to the polycrystalline silicon layer 1.3 below the silicone layer 14. Therefore, when this etching is completed, the oxidized silicone layer 14 (included in the metal thin layer 1115 on the upper surface) in the portion surrounded by the front 1e and bottom portions 16 is removed.
becomes the i-level cantilever beam 17.・Note that the chemical etching is blocked by silicon oxide 112.
The depth of the space under the cantilevered lock 17 is equal to the thickness of the polycrystalline silicon layer 13.

以上の説明から明らかなように、この発明の方法におい
で鉱、従来のP 層に代えて酸化シ、リコン層を用い、
かつシリーン層に代えて、CVD法な−どによって生成
する多結晶シリコン層を用いる。
As is clear from the above description, in the method of the present invention, a silicon oxide layer is used in place of the conventional P layer.
In addition, instead of the silane layer, a polycrystalline silicon layer produced by CVD or the like is used.

し九がって、この発明の作製法によれば、まず、作表工
程中に不純物音高’Ill [Kドーグする作業がない
ので、通常の牛導体素子製造工程が応用できる利点を持
つ。次に、高談度に不純物をドーグすることで荒れてい
るシリコンウェー八表面上に、lOμ1以上もの単結晶
シリコン1li1を成長させるという、高度の技術を要
しないで、CVD法などによシ多結晶シリコンを生成す
るといり簡単な手法が使用できる利点がある。ま九、従
来の方法で作製し九マイク四片持ち梁では、マイクル片
持ち采の下部の底面が鍵部にならないのに対して、この
方法で作製したマイク四片持ち梁では多結晶シリコン層
を生成する前の、−面仕上げされた状態の酸化シリコン
層(シリコンウェーハ*mt禽m研磨しておくことによ
シ、酸化シリコン層表叩は当然、鏡面仕上げされた−の
となる)が露出するため、このiイ、り四片持ち梁を光
偏向素子のような光学素子として使用する場合、底E[
18(第8−に示す)からの拡散反射光が極めて少な−
という利点がある。また、この作製法は、多結晶シリコ
ン層を化学エツチングすることで!イクp片持ち梁を形
成するので、−マイク四片持ち梁の方向が特定の方向に
限定されることがない上、エツチングに要する時間が非
常に少ないという利点を有する。を良、従来の作a法で
はエビ・タクシ−によp単結晶シリ;ン層を形成するの
て、マイクロ片持ち朱の上にさらにreIUlmの工程
tくp返えして!層構造のマイクロ片持ち梁を作成する
こと紘不可能であるが、この方法は多結晶シリコンws
を生成するので、多機構造が可能であるという利点があ
る。
Therefore, according to the manufacturing method of the present invention, first, there is no work to remove impurity pitch 'Ill [Kdawg] during the tabulation process, so there is an advantage that the normal process for manufacturing conductor elements can be applied. Next, on the surface of the silicon wafer, which has become rough due to the excessive doping of impurities, single-crystal silicon 1li1 with a size of 10μ1 or more can be grown using CVD or other methods without requiring sophisticated technology. The advantage is that a simple method can be used to produce crystalline silicon. Nine, in the four-microphone cantilever made using the conventional method, the bottom surface of the lower part of the microphone cantilever does not become the key part, whereas in the four-microphone cantilever made using this method, the polycrystalline silicon layer The silicon oxide layer in a polished state (by polishing the silicon wafer, the surface of the silicon oxide layer naturally becomes mirror-finished) before it is produced. Therefore, when using this four cantilever beam as an optical element such as a light deflection element, the bottom E[
18 (shown in No. 8) is extremely small.
There is an advantage. Also, this manufacturing method involves chemically etching the polycrystalline silicon layer! Since a cantilever beam is formed, the direction of the four-microphone cantilever beam is not limited to a specific direction, and there is an advantage that the time required for etching is very small. In the conventional production method, a layer of monocrystalline silicon is formed on the shrimp taxi, and then the reIulm process is repeated on top of the micro cantilever vermilion. Although it is impossible to create micro-cantilever beams with a layered structure, this method can be applied to polycrystalline silicon.
Since it generates , it has the advantage that a multi-organ structure is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

giri!Jないし第4図拡従来のマイクル片持ち梁の
作製法を示し、それぞれ(A) a平面図、それぞれC
B)は断向図、第5図ないし継8図拡この殆明の!イク
p片持ち梁の作製法を示゛シ、それぞれ(4)は平ma
r、それぞれCB) a断面−である。 11・・・シリーンウエーハ、12・・・酸化シリコン
層、13・・・多結晶シリコン階、14・・・酸化シリ
コン層、15・・・金楓薄膜、16・・・−口部、17
・・・マイクル片持ち采。 矛 1 図 矛4閃 矛 511 矛 sag 手続補正書 昭和57年5月28日 特許庁長官島 1)春 樹膜 1、事件の表示 昭和s6年 特許 願第 11NIIIIIT  号2
、尭@O名称                 −シ
リ;ンpエーハ上へのマイク筒片持ち乗O作製鍮3、補
正をする者 事件との関係    畳 許 出願人 (011?)沖電気工**wc自社 4、代理人 5、補正命令の日付  昭和  年  月  日(自I
I)第3図
Giri! Figures J to 4 show enlarged conventional micro cantilever manufacturing methods, respectively (A) a plan view and C respectively.
B) is a cross-sectional view, and the enlargement of Figures 5 to 8 is almost clear! The method for making cantilever beams is shown below, and (4) is flat.
r, respectively CB) a cross section -. DESCRIPTION OF SYMBOLS 11... Silicon wafer, 12... Silicon oxide layer, 13... Polycrystalline silicon layer, 14... Silicon oxide layer, 15... Gold maple thin film, 16... - Mouth part, 17
...Mikle cantilevered sash. Spear 1 Picture Spear 4 Flash Spear 511 Spear Sag Procedural Amendment May 28, 1980 Patent Office Commissioner Island 1) Spring Tree 1, Incident Indication 1937 Patent Application No. 11NIIIIT No. 2
, 尭@O Name - Siri;P Microphone cylinder cantilever mounted on the top of the amp; Person 5, date of amendment order Showa year month day (self I
I) Figure 3

Claims (1)

【特許請求の範囲】[Claims] 一面研WI!たシリコンウェー/S上に第1の酸化シリ
コン層を形成する工程と、その第1olk化シ、リコン
層上に多結晶シリコン〜を形成した後、その表面に*m
研暦を施す工程とJそ、の−面研m面上に第2の酸化シ
リコン層を形成し、さ、らに少なくともマイクロ片持、
ち呆とな・る部分の第2の酸化シリコン層上に金属薄膜
を形成する工程と、この全島*a周囲の第2の酸化シリ
コン層を凹微に除シ絡出した多結晶シリコン、層および
マイクロ片持ち采となる部分の#I2の酸化シリコン層
下の多結晶シリコン層を除去ンる工程とt−具備してな
るシリコンウェーハ上への1429片持ち梁の作製法。
Ichimenken WI! After forming a first silicon oxide layer on the silicon wafer/S and forming polycrystalline silicon on the first silicon wafer/S,
A second silicon oxide layer is formed on the -surface polished m surface of the J surface, and furthermore, at least a micro cantilever,
A process of forming a metal thin film on the second silicon oxide layer in the area where the area is slightly damaged, and a polycrystalline silicon layer formed by finely decaching the second silicon oxide layer around the entire island*a. and a step of removing the polycrystalline silicon layer under the #I2 silicon oxide layer in the portion that will become the micro cantilever.
JP56186837A 1981-11-24 1981-11-24 Fabrication method of micro cantilever on silicon wafer Granted JPS5889859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56186837A JPS5889859A (en) 1981-11-24 1981-11-24 Fabrication method of micro cantilever on silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56186837A JPS5889859A (en) 1981-11-24 1981-11-24 Fabrication method of micro cantilever on silicon wafer

Publications (2)

Publication Number Publication Date
JPS5889859A true JPS5889859A (en) 1983-05-28
JPH0113231B2 JPH0113231B2 (en) 1989-03-03

Family

ID=16195490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56186837A Granted JPS5889859A (en) 1981-11-24 1981-11-24 Fabrication method of micro cantilever on silicon wafer

Country Status (1)

Country Link
JP (1) JPS5889859A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266531A (en) * 1991-01-30 1993-11-30 Cordata Incorporated Dynamic holographic display with cantilever
WO1994018697A1 (en) * 1993-02-04 1994-08-18 Cornell Research Foundation, Inc. Microstructures and single mask, single-crystal process for fabrication thereof
US5426070A (en) * 1993-05-26 1995-06-20 Cornell Research Foundation, Inc. Microstructures and high temperature isolation process for fabrication thereof
US5640133A (en) * 1995-06-23 1997-06-17 Cornell Research Foundation, Inc. Capacitance based tunable micromechanical resonators
FR2757941A1 (en) * 1996-12-30 1998-07-03 Commissariat Energie Atomique METHOD FOR PRODUCING A SUSPENDED ELEMENT IN A MICRO-FACTORY STRUCTURE
US6515751B1 (en) 1999-03-11 2003-02-04 Cornell Research Foundation Inc. Mechanically resonant nanostructures

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266531A (en) * 1991-01-30 1993-11-30 Cordata Incorporated Dynamic holographic display with cantilever
WO1994018697A1 (en) * 1993-02-04 1994-08-18 Cornell Research Foundation, Inc. Microstructures and single mask, single-crystal process for fabrication thereof
US5719073A (en) * 1993-02-04 1998-02-17 Cornell Research Foundation, Inc. Microstructures and single mask, single-crystal process for fabrication thereof
US5426070A (en) * 1993-05-26 1995-06-20 Cornell Research Foundation, Inc. Microstructures and high temperature isolation process for fabrication thereof
US5640133A (en) * 1995-06-23 1997-06-17 Cornell Research Foundation, Inc. Capacitance based tunable micromechanical resonators
FR2757941A1 (en) * 1996-12-30 1998-07-03 Commissariat Energie Atomique METHOD FOR PRODUCING A SUSPENDED ELEMENT IN A MICRO-FACTORY STRUCTURE
WO1998029720A1 (en) * 1996-12-30 1998-07-09 Commissariat A L'energie Atomique Method for producing a suspended element in a micro-machined structure
US6365056B1 (en) * 1996-12-30 2002-04-02 Commissariat A L'energie Atomique Method for producing a suspended element in a micro-machined structure
US6515751B1 (en) 1999-03-11 2003-02-04 Cornell Research Foundation Inc. Mechanically resonant nanostructures

Also Published As

Publication number Publication date
JPH0113231B2 (en) 1989-03-03

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