JPS58161033A - Analog scan system - Google Patents

Abstract

PURPOSE:To shorten the occupation time of a bus line to make a high-speed transfer possible, by making instruction words and data, which are required for the execution of a CPU, compact and storing preliminarily them in a cache memory. CONSTITUTION:When A CPU 1 sends a start signal to a DMA device 4, the transfer of the output signal from an A/D converter to a main memory 3 through a bus line 6 is started. When the CPU1 sends the start signal to an auxiliary storage device 5, data having a designated size is transferred from the main memory 3 to the device 5 through the bus 6. A program is made small- sized so that contents of the main memory 3 which the CPU1 refers to are stored in a cache memory 2 and are executed while devices 4 and 5 are in the course of data transfer; and thus, the time when the bus 6 required for data transfer is occupied becomes shorter to make high-speed analog scanning possible.

Description

[Detailed description of the invention] (1k) Technical field lI! A large amount of sample data that has been transformed into M/D is stored in D.
Once transferred from the MA device to the King storage device via Path Twin.
The present invention relates to an analog scan method that enables high-speed transfer by shortening the occupancy rate of the I/O line when writing data from the main memory device to the auxiliary memory device through the memory twin.

lb) Description of the prior art In the conventional analog scan method, even during data transfer between the main memory device (hereinafter referred to as DMA device) and the DMA device,
The central processing unit SaW (hereinafter referred to as CPU) reads and writes data from the main memory, and because the pass line occupancy rate was high, this became a major constraint on speeding up analog scan.

(C1 Objective of the Invention) Therefore, an object of the present invention is to provide an analog scan method that removes the constraint conditions and enables faster analog scan.

(d) Structure and operation of the invention An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows a configuration diagram of the present invention, in which the CPU 1 executes an instruction, and the CPU 1 takes out the contents of the current cache memory 2 (if there is a duplicate address content, it is retrieved and executed; The content is taken out and executed from the CPU 1 through the pass line 6. When a start signal is sent from the CPU to the DMA device @4, the output signal from the A/DRA device is transferred to the main memory 34 through the path line 6. Transfer is started from the CPU 1 to the auxiliary memory. When a start signal is sent to the Makoto IIL 5, the data corresponding to the number of fingers added from the main memory 3 is transferred to the auxiliary storage device 5 through the pass line 6.

FIG. 2 shows that instructions or data executed by CPU 1 are sent from cache memory 2 (instead of cache memory 3), and are stored in three pass lines: CPU 1, DMA device 4, and auxiliary storage device 5 (called BULK). Since the line is divided and used, if the rate at which a 1 m long device occupies the pass line per unit time is h (or Pm), equation (1) becomes 9.

h (or PlB)--'Giant Ω9 (Enji x 100 (
Season: (1) Tc + Tn + T; however, Tc is the time that the CPU occupies the pass line;
The time TI during which the MAM device occupies the pass line is the time during which the auxiliary storage device occupies the pass line.

Therefore, while data is being transferred between the DMA device 4 and the auxiliary storage device 5, all the contents of the main memory 3 referred to by the CPU 1 are stored in 24 units of cache memory and executed.
Make the program smaller. Then, Tc in Fig. 2 disappears, and the data transfer (the occupancy rate h of the pass line 6, which is inevitable)
Also) W h) increases.

h (or Pm)-Tnsu94 direct) x □oo (%
), "98. (2) TD+Tm +e) Effects of the Invention According to the present invention described above (2), the number of sample points per unit time is significantly increased in high-speed analog scanning by an electronic computer (2). - It is possible to provide an analog scan method that enables high-speed analog scan without the need for additional software.

[Brief explanation of the drawing]

Figure 1 shows the electronic gt for high-speed analog scanning.
FIG. 2, a block diagram of the computer, is a timing chart when the cache memory is ineffective. 'rc: Time TD during which the CPU occupies the pass line
: DMA device is TB: Auxiliary storage device is

Claims (1)

[Claims] A central processing unit, a main memory device, and a main memory device (2) that directly writes data without going through the central processing unit.
an MA device, an A/D converter that converts analog signals into digital values and sends the DMA device (two digital values), and an auxiliary memory that reads and stores signed data from the main memory device via the central processing unit. a cache memory for copying and storing a portion of data frequently referenced by the central processing unit in the main memory; and a path for transferring data when reading and writing data from the main memory. A computer computer consisting of lines: At the same time, data is written from the DMA device to the upper storage device through the pass line (2. Pictures are written from the main memory device to the auxiliary storage device through the pass line, central processing In order for the device to execute (= the necessary instructions or data are compacted and stored in the cache memory in advance, the central processing unit amam retrieves the instructions or data from the main memory W& during the time it occupies the pass line. For this reason: An analog scan method that eliminates the time occupied and occupies the line only when data is transferred between the DMA device and the main memory and from the main memory to the auxiliary memory.