JPS5668988A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5668988A
JPS5668988A JP14310479A JP14310479A JPS5668988A JP S5668988 A JPS5668988 A JP S5668988A JP 14310479 A JP14310479 A JP 14310479A JP 14310479 A JP14310479 A JP 14310479A JP S5668988 A JPS5668988 A JP S5668988A
Authority
JP
Japan
Prior art keywords
memory
blocks
block
selection
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14310479A
Other languages
Japanese (ja)
Inventor
Masamichi Asano
Hiroshi Iwahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14310479A priority Critical patent/JPS5668988A/en
Priority to US06/192,203 priority patent/US4447895A/en
Priority to DE3037130A priority patent/DE3037130C2/en
Priority to GB8031956A priority patent/GB2060303B/en
Publication of JPS5668988A publication Critical patent/JPS5668988A/en
Priority to US06493605 priority patent/US4509148B1/en
Priority to GB08313395A priority patent/GB2120036B/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To secure the power-down state with every nonselection block and thus ensuring the low power consumption even when the chip is selected, by forming the memory into blocks in a semiconductor memory chip and then providing the power-down element at the memory block decoder part. CONSTITUTION:The X decoders 21-24 and the memory matrices 11-14 are divided into four memory blocks 211-214, and then the memory block selection/nonselection circuit 22 is actuated by the addresses A1 and A2 to select the memory blocks. The circuit 22 delivers the output to the Y decoders 21-22 and supplies the power- down signal to the blocks except for the selection block. Thus other blocks are set under the power-down state, and at the same time the X decoder 21 of the selected block is made active. Then the X selection is carried out by the addresses A3-A6; and the Y selection is done through the Y decoder 23 and by the addresses A7-A8 respectively.
JP14310479A 1979-10-04 1979-11-05 Semiconductor memory Pending JPS5668988A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP14310479A JPS5668988A (en) 1979-11-05 1979-11-05 Semiconductor memory
US06/192,203 US4447895A (en) 1979-10-04 1980-09-30 Semiconductor memory device
DE3037130A DE3037130C2 (en) 1979-10-04 1980-10-01 Address designation circuit
GB8031956A GB2060303B (en) 1979-10-04 1980-10-03 Semiconductor memory device
US06493605 US4509148B1 (en) 1979-10-04 1983-05-11 Semiconductor memory device
GB08313395A GB2120036B (en) 1979-10-04 1983-05-16 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14310479A JPS5668988A (en) 1979-11-05 1979-11-05 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPS5668988A true JPS5668988A (en) 1981-06-09

Family

ID=15330993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14310479A Pending JPS5668988A (en) 1979-10-04 1979-11-05 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5668988A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693177A (en) * 1979-12-26 1981-07-28 Nec Corp Static mos memory integrated circuit
JPS60167188A (en) * 1984-12-24 1985-08-30 Hitachi Ltd Semiconductor memory
JPS60170090A (en) * 1984-02-13 1985-09-03 Hitachi Ltd semiconductor integrated circuit
JPH01500469A (en) * 1986-07-15 1989-02-16 サンドストランド・データ・コントロール・インコーポレーテッド Terrain map memory matrixing
JPH01146190A (en) * 1987-08-17 1989-06-08 Texas Instr Inc <Ti> Solid memory system
JPH0391193A (en) * 1989-08-31 1991-04-16 Fujitsu Ltd Semiconductor storage device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693177A (en) * 1979-12-26 1981-07-28 Nec Corp Static mos memory integrated circuit
JPS60170090A (en) * 1984-02-13 1985-09-03 Hitachi Ltd semiconductor integrated circuit
US5311482A (en) * 1984-02-13 1994-05-10 Hitachi, Ltd. Semiconductor integrated circuit
JPS60167188A (en) * 1984-12-24 1985-08-30 Hitachi Ltd Semiconductor memory
JPH01500469A (en) * 1986-07-15 1989-02-16 サンドストランド・データ・コントロール・インコーポレーテッド Terrain map memory matrixing
JPH01146190A (en) * 1987-08-17 1989-06-08 Texas Instr Inc <Ti> Solid memory system
JPH0391193A (en) * 1989-08-31 1991-04-16 Fujitsu Ltd Semiconductor storage device

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