JPS5613599A - Memory assigning circuit - Google Patents
Memory assigning circuitInfo
- Publication number
- JPS5613599A JPS5613599A JP8942979A JP8942979A JPS5613599A JP S5613599 A JPS5613599 A JP S5613599A JP 8942979 A JP8942979 A JP 8942979A JP 8942979 A JP8942979 A JP 8942979A JP S5613599 A JPS5613599 A JP S5613599A
- Authority
- JP
- Japan
- Prior art keywords
- outputs
- input
- gate circuit
- information
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Input From Keyboards Or The Like (AREA)
Abstract
PURPOSE: To reduce hardware in scale by preventing double selection in terms of key-contact group input by using one OR gate circuit and one clock input control gate circuit.
CONSTITUTION: Assuming that key contact S2 of key contact group 1 for memory assignment is grounded by closing, binary-code converting circuit 2 detects that to obtain its binary code by converting and then outputs n-digit binary information from output lines SA1WSAn. Register 3 with clock input latches pieces of input information IlWIn at the rise of clock pulse ϕ and outputs them as Q1WQn. Those outputs Q1WQn are input to memory circuit 4. At this time, outputs Q1WQn contain information without fail, so that OR gate circuit 6 generates an output showing the existence of the information. Once this existence output is supplied to clock- pulse control gate circuit 5, the following signal ϕ is never accepted. Consequently, the double selection of the memory can be prevented.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8942979A JPS5613599A (en) | 1979-07-14 | 1979-07-14 | Memory assigning circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8942979A JPS5613599A (en) | 1979-07-14 | 1979-07-14 | Memory assigning circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5613599A true JPS5613599A (en) | 1981-02-09 |
Family
ID=13970406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8942979A Pending JPS5613599A (en) | 1979-07-14 | 1979-07-14 | Memory assigning circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5613599A (en) |
-
1979
- 1979-07-14 JP JP8942979A patent/JPS5613599A/en active Pending
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