JPS54158829A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS54158829A JPS54158829A JP6800078A JP6800078A JPS54158829A JP S54158829 A JPS54158829 A JP S54158829A JP 6800078 A JP6800078 A JP 6800078A JP 6800078 A JP6800078 A JP 6800078A JP S54158829 A JPS54158829 A JP S54158829A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- decoder
- operate
- bootstrap
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Abstract
PURPOSE:To make it possible to operate a device by a single power voltage and also to reduce the power consumption by composing the entire device of C-MOS and then by using a voltage converter circuit and a bootstrap circuit. CONSTITUTION:As Y decoder 15, a bootstrap circuit is used and controlled by programming circuit 20, and voltage converter circuit 21 is interposed between Y register 14 and decoder 15 in order to operate the bootstrap circuit. Further, X address 11, X decoder 12, Y address 14, Y decoder 15, data in/out circuit 18, and circuits 20 and 21 are all composed of C-MOSs, and circuit 21 is used to operate the input buffer circuit for addresses 11 and 14 by a single power supply during both read and write operations. In addition, a bootstrap circuit is used as circuit 20 to perform a write operation with a low voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6800078A JPS54158829A (en) | 1978-06-05 | 1978-06-05 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6800078A JPS54158829A (en) | 1978-06-05 | 1978-06-05 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54158829A true JPS54158829A (en) | 1979-12-15 |
Family
ID=13361179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6800078A Pending JPS54158829A (en) | 1978-06-05 | 1978-06-05 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54158829A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58153296A (en) * | 1982-03-05 | 1983-09-12 | Ricoh Co Ltd | Memory driving circuit |
| US7031197B2 (en) | 1990-09-14 | 2006-04-18 | Oki Electric Industry Co., Ltd. | EEPROM writing and reading method |
-
1978
- 1978-06-05 JP JP6800078A patent/JPS54158829A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58153296A (en) * | 1982-03-05 | 1983-09-12 | Ricoh Co Ltd | Memory driving circuit |
| US7031197B2 (en) | 1990-09-14 | 2006-04-18 | Oki Electric Industry Co., Ltd. | EEPROM writing and reading method |
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