JPH11511907A - Standard cell library optimization method and device - Google Patents

Abstract

(57) [Summary] The present invention relates to a method and apparatus for optimizing a standard cell library. A method for optimizing a device size in a CMOS standard cell library is described. The library is created by a compiler that allows parameterization of design rules and device size. Optimize device size to achieve low power, high speed, or minimal layout area cell libraries.

Description

DETAILED DESCRIPTION OF THE INVENTION Standard Cell Library Optimization Method and Apparatus Technical field The present invention relates to a method and apparatus for designing an integrated circuit, and more particularly, to a method and apparatus for optimizing a standard cell library used for designing an integrated circuit. Background of the Invention Digital standard cells are used in various integrated systems that use integrated circuits (ICs) made from standard cell libraries. These systems have wide variability in design requirements. In some systems, power consumption is significant, in other systems minimizing silicon area is important to reduce cost, and in some systems operating speed is a primary consideration. With the changing requirements of system design and the widespread use of digital standard cells, it is desirable to have a standard cell library that matches these particular needs. Previous optimizations of the standard cell library have focused on specific circuits and implementations. Typically, standard cell optimization has been limited to the design of buffers or inverter chains, which have been optimized to minimize power waste or signal delay. An example of low power optimization is "Energy Control and Accurate Delay Estimation in CMOS Buffer Design" by Sha Ma and Paul Franzon, IEEE Journal of Semiconductor Circuits, vol. 29, no. 9, pp. 1150-1153, 1994. September, 2005. SR. Vemura and AR. Thorbjornsen, "Variable Tape CMOS Buffers", IEEE Journal of Semiconductor Circuits, vol. 26, no. 9, pp. 1265-1269, September 1991, discusses examples of minimum delay buffer optimization. In fact, delay optimization efforts have primarily focused on the ratio of continuous stages, rather than the ratio of NMOS to PMOS. However, no references describe the benefits of providing a single optimization method and apparatus for any one of the selected parameter sets. Summary of the Invention According to one aspect, the present invention is a method for designing a set of device specifications for a library of standard cell elements used in integrated circuit fabrication. The method comprises the steps of: a) determining a process technique for creating an element; and b) determining an optimization criterion from a predetermined set of optimization criteria. The method further comprises c) specifying a set of library specific knowledge. The method further comprises: d) processing the set of library-specific knowledge as process technology and optimization criteria, and creating a set of device specifications therefrom. According to another aspect, the present invention is a method for designing a set of device specifications for a library of CMOS standard cell elements used in integrated circuit fabrication. Each CMOS standard cell element includes an N-type transistor and a P-type transistor. The method comprises the steps of: a) determining a process technique for creating a CMOS standard cell element; and b) determining one optimization criterion from a predetermined set of optimization criteria. The method further comprises c) specifying a set of library specific knowledge. The method also includes d) processing the set of library-specific knowledge as process technology and optimization criteria, and then generating a set of device specifications. According to yet another aspect, the present invention is an apparatus for designing a set of device specifications for a library of standard cell elements used in integrated circuit fabrication. The apparatus includes an input circuit that determines a process technique for creating the element, and an input circuit that determines one optimization criterion from a predetermined set of optimization criteria. The method further comprises storage for specifying a specific set of knowledge of the library. The apparatus further comprises processing circuitry for processing the set of library-specific knowledge as process technology and optimization criteria, and then generating a set of device specifications. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a block diagram of the method of the present invention. FIG. 2 is a flowchart of a method for designing a set of low power consumption device specifications. FIG. 3 is a more detailed flowchart of the method for designing the set of low power consumption device specifications shown in FIG. FIG. 4 is a flowchart of a method for checking a noise margin of a combination of logic gates. FIG. 5 shows the correct arrangement of FIGS. 5A and 5B. FIG. 5A is a first part of a flowchart of a method for checking a noise margin of a specific logic gate. FIG. 5B is a second part of a flowchart of a method for checking the noise margin of a particular logic gate. FIG. 6 shows the correct arrangement of FIGS. 6A and 6B. FIG. 6A is a first part of a flowchart of a method for minimizing the area of a logic gate. FIG. 6B is a second part of a flowchart of a method for minimizing the area of a logic gate. FIG. 7 shows the correct arrangement of FIGS. 7A and 7B. FIG. 7A is a first part of a flowchart of a method for optimizing the NMOS and PMOS widths of a logic gate. FIG. 7B is a second part of a flowchart of a method for optimizing the NMOS and PMOS widths of a logic gate. FIG. 8 shows the correct arrangement of FIGS. 8A and 8B. FIG. 8A is a first part of a flowchart of a method for optimizing the ratio of the NMOS width to the PMOS width of a given logic gate. FIG. 8B is a second part of a flowchart of a method for optimizing the ratio of the NMOS width to the PMOS width of a given logic gate. FIG. 9 shows the correct arrangement of FIGS. 9A and 9B. FIG. 9A is a first part of a flowchart of a method for optimizing the total width of a given logic gate. FIG. 9B is a second part of a flowchart of a method for optimizing the total width of a given logic gate. FIG. 10 is a flowchart of a method for optimizing either the NMOS width or the PMOS width of a predetermined logic gate. FIG. 11 shows the correct arrangement of FIGS. 11A and 11B. FIG. 11A is a first part of a flowchart of a method for optimizing the PMOS width of a given logic gate. FIG. 11B is a second part of a flowchart of a method for optimizing the PMOS width of a given logic gate. FIG. 12 shows the correct arrangement of FIGS. 12A and 12B. FIG. 12A is a first part of a flowchart of a method for optimizing the NMOS width of a given logic gate. FIG. 12B is a second part of a flowchart of a method for optimizing the NMOS width of a given logic gate. FIG. 13 shows the correct arrangement of FIGS. 13A and 13B. FIG. 13A is a first part of a flowchart of a method for maximizing the speed of a given logic gate. FIG. 13B is a second part of a flowchart of a method for maximizing the speed of a given logic gate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION FIG. 1 is a block diagram of the method of the present invention. Method 100 includes a step 102 of determining a process technique for fabricating a desired component. The method 100 also includes determining 104 one optimization criterion from the predetermined set of optimization criteria. All standard cell compilers of the present invention use one of three sets of transistor sizes. The three sets of transistor sizes are each optimized for low power, high speed or minimum area design, thereby creating a standard cell library that is optimized accordingly. For example, the height of a standard cell is a function of transistor size. This provides a means to determine area cost when performing device size optimization. Each set of transistor sizes consists of four NMOS and four PMOS sizes. The four sizes are selected based on the number of transistors connected in series. For example, a two-input NAND gate has two NMOS devices in series. Thus, such a gate would have a transistor size selected for two NMOS transistors in series. The notation used for this transistor size is N_2s. The same two-input NAND gate has one PMOS device in series. Thus, such a gate would use the transistor size, P_1s, selected for a single PMOS transistor in series. The goal of transistor size optimization is to determine the four NMOS and four CMOS transistor sizes that optimize the standard cell library to achieve minimum power waste, maximum operating speed, or minimum silicon area. . The details of the three optimization procedures are described below. Referring again to FIG. 1, size determination program 106 receives the results of steps 102 and 104 and information from library specific knowledge database 108. As will be described in more detail below, the sizing program 106 then processes the set of library-specific knowledge as a function of process technology and optimization criteria to create a set of device specifications 110. Subsequently, the device specification set 110 is made available to the parameterized library compiler 112, which compiles the desired standard cell elements and creates the resulting library 114. FIG. 2 is a flowchart of a method for designing a set of low power consumption device specifications. In integrated circuits, power waste is minimized by reducing capacitance where practical. This is done with the minimum device size, subject to a lower limit given by the setting of the minimum noise margin for the gate. Noise margin limitations ensure that standard cells have sufficient immunity to power supply noise. Noise margin is defined as the difference between the logic threshold of the gate and the power supply. The logic threshold of the gate is evaluated with the output of the inverting gate shorted to all inputs. Logic thresholds are evaluated for all gates in the standard cell library over temperature, power supply and process changes. The transistor size is adjusted when the gate fails to meet noise margin requirements and the process is restarted. This is repeated until all gates pass the noise margin requirements. Priorities for reducing transistor size are included in the process, but transistor size increases when required to meet noise margin requirements. In addition, the output rise and fall times for a gate are limited by limiting the maximum capacitance a single gate can drive. The maximum capacitance limits the through current flowing from the power supply through the PMOS and NMOS devices to the ground plane. FIG. 2 is a flowchart of a method for designing a set of low power consumption device specifications. The method 200 includes an initialization step 202 in which each of the four NMOS and four PMOS transistor sizes is set to ba, which is the minimum size allowed by the design rules of the particular process technology. Thereafter, at step 204, the static noise margin (NM) is checked by executing a subroutine Check (), which subroutine Check () will be described in more detail later. FIG. 3 is a more detailed flowchart of the method 200 for designing a set of low power consumption device specifications shown in FIG. Method 200 begins by initializing a minimum size device (step 202). Next, the static NM of the NOR gate constituted by the smallest size device is tested (step 300). If the NM of the NOR gate is too low, increase the size of the PMOS device (step 302) and execute step 300 again. Eventually, the NM of the NOR gate reaches a sufficiently high level and the method 200 proceeds to step 308. In step 308, the NM of the NAND gate is tested. If it is too high, method 200 proceeds to step 310, where the size of the NMOS device is increased and step 308 is performed again. Again, eventually the NM of the NAND gate will not be too high, at which point the method 200 determines the logic threshold of the composite gate, which is various combinations of NMOS and PMOS sizes (step 312). If the composite gate NM is outside the range bounded by the predetermined value, the method 200 determines whether the NM is too low (step 314). If so, the size of the PMOS device is increased and the method 200 returns to step 312. If the NM is not too low, it must be too high, in which case the method proceeds to step 318, where the size of the NMOS device is increased and step 312 is re-executed. If the value of NM is within the determined range, the method 200 proceeds to step 304 where it is determined whether there is a change for the composite gate. If there are changes, the method returns to step 300 and starts the process again. If there is no change in the composite gate, the method moves to stop step 306 and ends. FIG. 4 is a flowchart of a method for checking a noise margin of a combination of logic gates. The method 400 begins at step 402, which determines whether the PMOS and NMOS devices are changing when using the method 400. Initially, the PMOS and NMOS devices are changing, so the method 400 moves to step 404, where the four PMOS size values are changed using the subroutine Check NM_gate (), which will be described in greater detail below. Check the NOR gate by evaluating the effect. Next, the method 400 proceeds to step 408, where the NAND gate is checked again by evaluating the effect of changing the four NMOS gate size values using the subroutine Check NM_gate (). Finally, the method 400 moves to step 410, where again the subroutine Check NM_gate () is used to change three of the four NMOS sizes and three of the four PMOS sizes. Check the composite gate by evaluating the effect of causing it. The method 400 then returns to step 402 where it determines any changes for PMOS and NMOS. If there is no change, the method 400 moves to the return step 406. FIG. 5 shows the correct arrangement of FIGS. 5A and 5B. FIG. 5A is a first part of a flowchart of a method for checking a noise margin of a specific logic gate. FIG. 5B is a second part of a flowchart of a method for checking the noise margin of a particular logic gate. The method 500 begins at step 502, where the NMOS and PMOS sizes, minimum NMOS and PMOS step sizes, and logic thresholds LTmin and LTmax are set. After the method 500 proceeds to step 504, the logic threshold is compared with the current logic threshold values LTmin and LTmax. If the logic threshold is not too large or too small, the method 500 proceeds to step 506, where the values of the NMOS and PMOS sizes are established, and then to step 508, from which the subroutine returns. If the logic threshold is too large or too small, the method 500 proceeds to step 510, where the logic threshold is recalculated for high and low supply voltages, P and N intensity combinations, and minimum and maximum temperatures. After moving to step 512, the method 500 then compares the logic threshold to the threshold. If the logic threshold is too high, the method moves to comparison step 514 to determine if the logic threshold is too high. If so, the method 500 proceeds to step 516, where the new size of the PMOS is compared to the minimum allowable PMOS size. If the new size of the PMOS is larger than the minimum allowable PMOS size, the size of the increasing change in the PMOS size is reduced by a factor of 2 (step 520). Otherwise (step 524), the size of the increase in NMOS size is reduced by a factor of two. If the size of the increase in PMOS size has been reduced by a factor of two, the method proceeds to step 522, where the current PMOS size is reduced by the new value of the increase. On the other hand, if the size of the increase in the NMOS size is reduced by a factor of 2, the current NMOS size is increased by the new value of the increase in the PMOS size. At step 518 of the method 500, the logic threshold is tested. If it is too low, the method 500 moves to step 528. At this point, a test similar to that performed for the current value of the PMOS size in steps 516, 520, 522 and 526 is performed for the current value of the NMOS size. Eventually, method 500 reaches step 534, where the NM is reevaluated, and the method returns to step 504. Minimum area optimization is designed to achieve the fastest cells possible within the minimum area. The device is sized to meet the minimum standard cell height. In addition to checking the minimum noise margin, it controls the ratio between the gate output rise time and output fall time. To achieve this goal, an initial set of transistor sizes is selected taking into account standard cell height requirements. This initial set of transistor sizes is further optimized by using iterative SPICE simulations to minimize gate delay without increasing standard cell height. In this process, the maximum speed gate is obtained within the minimum layout area. The initial set of transistor sizes uses the current ratios specified in Table 1, "Initial Current Ratio for Area Optimization", to make the rise and fall times of the various gates approximately equal. It has been empirically found that these sets of currents provide a good trade-off between area and performance. These sizes are then used to calculate the standard cell height. This initial set of devices is then further optimized using a sequence similar to the fast optimization, with the exception that the initial standard cell height is not increased. Optimization is performed on the set of inverters, NAND and NOR gates shown in Table 2, "Minimum Area Gate Optimization Step". This process establishes the set of transistor sizes required for standard cell library optimization for minimum area. The optimization determines one, two and three series NMOS and PMOS transistor sizes. The four series NMOS and PMOS transistor sizes are set such that the four series devices provide the same pull-up and pull-down current as the three series transistor sizes. However, the size of the four series devices is limited to the maximum NMOS and PMOS device width, as calculated by the standard cell height routine in this step. Next, check the ratio of the pull-up and pull-down currents for the inverter, NAND and NOR gates. The ratio of this pull-up and pull-down current is limited. If possible, reduce the NMOS and PMOS transistor width; otherwise, increase the inverse (PMOS / NMOS) transistor size as needed. The final static noise margin check described for low power optimization ensures that the resulting standard cell library meets the same noise margin requirements as low power optimized cells. FIG. 6 shows the correct arrangement of FIGS. 6A and 6B. FIG. 6A is a first part of a flowchart of a method for minimizing the area of a logic gate. FIG. 6B is a second part of a flowchart of a method for minimizing the area of a logic gate. In the method 600, step 602 sets minimum NMOS and PMOS widths. Next, in step 604, the method 600 sizes the other NMOS device to match the N_1s pull-down current and the other PMOS device to match the P_1s pull-down current. Moving to step 606, the method 600 establishes a value HeightLimit for the standard cell height. This height is increased by 7% in step 608. In step 610, the minimum NMOS width is set to ba, and the same is applied to the minimum PMOS width. The series current of a single device of size min_n is determined in step 612, and then the maximum NMOS width is increased by two series widths needed to provide a current 33% greater than the series current of a single device of size min_n. Set equal to In step 616 of method 600, N_1s is set to min_n, N_2s is set to Max_n / 2, and N_3s is determined from these two values. At step 618, the series current of a single device of size min_p is determined. The maximum PMOS width is then set to the value of the three series widths required to provide a single device series current of size min_p (step 620). At step 622, the values of P_1s, P_2s, and P_3s are established. At step 624, the HeightLimit value is set to the standard cell height for the previous minimum and the value set at step 622. At step 626, the delay for the two-input NAND is minimized by iteratively using SPICE and adjusting the device size using the subroutine opt_np () discussed later. At step 628, the delay for the inverter is minimized by iteratively using SPICE and adjusting the device size. At step 630, the delay for the two-input NOR is minimized by iteratively using SPICE and adjusting the device size. At step 632, the delay for the 3-input NAND is minimized by iteratively using SPICE and adjusting the device size. Finally, at step 634, SPICE is used iteratively to minimize the delay for the 3-input NOR by adjusting the device size. Next, in step 636, three series currents N_3s and P_3s are determined. At step 638, the values N-4s and P-4s are determined by individually comparing the appropriate currents with the minimum space available for NMOS and PMOS. Step 640 checks the static NM, and step 642 checks that the rise and fall times are within a factor of three of each other. FIG. 7 shows the correct arrangement of FIGS. 7A and 7B. FIG. 7A is a first part of a flowchart of a method for optimizing the NMOS and PMOS widths of a logic gate. FIG. 7B is a second part of a flowchart of a method for optimizing the NMOS and PMOS widths of a logic gate. At step 702 of the method 700, the parameters are initialized. Next, the N-to-P ratio is optimized by using a subroutine opt_ratio () discussed later. The method 700 then moves to step 706, where the height is compared to a height limit. If the height is too high, the method 700 moves to step 708, where the total device width is optimized using the subroutine opt_total () with the reduced parameters. The subroutine opt_total () will be discussed later. The method 700 then moves to step 710. On the other hand, if the height does not exceed the height limit (step 706), the total device width is optimized using the subroutine opt_total () with the increased parameter. Again, the height is compared to the height limit (step 710). If the height is not greater than the height limit, the method 700 proceeds to step 714, where the N to P ratio is optimized using the subroutine opt_ratio () with the increased parameters. On the other hand, if the height is greater than the height limit, the method 700 proceeds to step 718, where the N: P ratio is optimized using the subroutine opt_ratio () with the reduced parameter. Regardless, the method 700 then proceeds to step 716, where the best delay within height limits is determined through this subroutine from a previous iteration. If the MatchCurrents parameter is set, the others are resized to match the PMOS and NMOS currents. At step 722 of the method 700, a check is made for a better limit if there are no hard limits specified as parameters. If there is a better restriction, the method 700 moves to step 724, where the percentage delay improvement is compared to the square of the percentage increase in height. If the percentage delay improvement is less than the square of the percentage increase in height, the method 700 proceeds to step 726, where the device size is approved. Regardless, if MatchCurrents is set, the other devices are resized at step 728 to match the current. FIG. 8 shows the correct arrangement of FIGS. 8A and 8B. FIG. 8A is a first part of a flowchart of a method for optimizing the ratio of the NMOS width to the PMOS width of a given logic gate. FIG. 8B is a second part of a flowchart of a method for optimizing the ratio of the NMOS width to the PMOS width of a given logic gate. In the method 800, step 802 determines whether the P / N ratio has converged. If not, the subroutine returns (step 804). Otherwise, the standard cell height is recalculated to establish a standard load capacity (step 806). Next, in step 808, the delay through the gate of the designated PMOS and NMOS size is calculated. At step 810, two evaluations are made. One evaluation is based on a comparison that determines whether the standard cell height is less than the height limit. If so, and if the delay has been improved, the method 800 proceeds to step 824. The other evaluation is used when there are no hard limits and the percentage delay improvement is greater than the square of the percentage increase in height. Again, if so, method 800 proceeds to step 824. If these two possibilities are not met, the method 800 moves to step 812, where the p-step size is compared to the smallest possible value. If it is too small, the method 800 establishes a p step size at step 814 and proceeds to step 816. Otherwise, the P / N ratio converges (step 818) and the method moves to step 816. At step 816, the direction in which the P / N ratio changes is determined. If so, the value of PMOS is decreased and the value of NMOS is increased (step 818). Then, the method 800 moves to step 820. Otherwise, increase the value of PMOS and decrease the value of NMOS, thereby increasing the direction of change. The method 800 then goes to step 820. Step 820 resizes the other device to match the NMOS and PMOS currents and then returns to step 802. If the test at step 810 passes, the method 800 proceeds to step 824, where the direction of change is also evaluated. If it is increasing, increase the PMOS value and decrease the NMOS value, then the method moves to step 820. If the direction of change is decreasing, the method 800 proceeds to step 826, where the PMOS value is decreased and the NMOS value is increased, and the method proceeds to step 820. FIG. 9 shows the correct arrangement of FIGS. 9A and 9B. FIG. 9A shows a first part of a flowchart of a method for optimizing the total width of a given logic gate. FIG. 9B shows a second part of a flowchart of a method for optimizing the total width of a given logic gate. In step 902 of the method, it is determined whether the value of the total width has converged. If not, the method 900 moves to the return step 904. If so, the method 900 moves to step 906, where the standard cell height and standard load capacity are set. At step 908, the delay through the gate type having the size of PMOS / NMOS is calculated, and the method 900 proceeds to step 910. At step 910, two evaluations are made. One evaluation is based on a comparison that determines whether the standard cell height is less than the height limit. If so, and if the delay has been improved, the method 900 moves to step 926. The other evaluation is used when there is no hard limit and the percentage delay improvement is greater than the square of the percentage increase in height. Again, if so, method 900 proceeds to step 926. If these possibilities are not taken, the method 900 proceeds to step 912, where the p-step size is compared to the smallest possible value. If it is too small, the method 900 decreases the p step size at step 914 and proceeds to step 916. Otherwise, the total width converges (step 918) and the method moves to step 916. At step 916, the direction of change of the total width is determined. If so, the value of the PMOS is decreased and the value of the NMOS is increased (step 920). Then, the method 900 moves to step 922. If not, the value of PMOS is increased and the value of NMOS is decreased, thereby increasing the direction of change. The method 900 also passes through step 922. Step 922 resizes the other device to match the NMOS and PMOS currents and then returns to step 902. If the test at step 910 passes, the method 900 proceeds to step 926, where the direction of change of the total width is also evaluated. If it is increasing, the PMOS value is increased and the NMOS value is decreased, then the method 900 moves to step 922. If the direction of change is decreasing, the method 900 proceeds to step 928, where the PMOS value is decreased and the NMOS value is increased, and the method 900 proceeds to step 922. FIG. 10 is a flowchart of a method for optimizing either the NMOS width or the PMOS width of a predetermined logic gate. In step 1002, parameters are initialized. At step 1004, a switch is made depending on whether the MOS is an NMOS. Otherwise, optimize the PMOS size using opt_p (), discussed later. If so, optimize the NMOS size using opt_n (), discussed below. In any case, the best delay within the height limit is determined from all previous runs, and the method moves to step 1012. Step 1012 determines if there is a better delay beyond the height limit, assuming that there is no height limit. If a better delay exists, the method 1000 proceeds to step 1014, where the percentage delay improvement is compared to the square of the percentage increase in height. If the percentage delay improvement is greater than the square of the percentage increase in height, the method 1000 proceeds to step 1018, where it approves the device size for this pass through the subroutine. The method 1000 then moves to step 1016. If the percentage delay improvement is not greater than the square of the percentage increase in height, the method 1000 simply proceeds to step 1016. FIG. 11 shows the correct arrangement of FIGS. 11A and 11B. FIG. 11A is a first part of a flowchart of a method for optimizing the PMOS width of a given logic gate. FIG. 11B is a second part of a flowchart of a method for optimizing the PMOS width of a given logic gate. At step 1102 of method 1100, it is determined whether the PMOS size has converged. If it has not converged, the method 1100 proceeds to return step 1104. If it converges, method 1100 proceeds to step 1106, where the standard cell height and standard load capacity are set. At step 1108, the delay through the gate type having the size PMOS is calculated, and the method 1100 proceeds to step 1110. At step 1110, two evaluations are made. One evaluation is based on a comparison that determines whether the standard cell height is less than the height limit. If so, and if the delay has been improved, method 1100 proceeds to step 1126. The other evaluation is used when there is no hard limit and the percentage delay improvement is greater than the square of the percentage increase in height. Again, if so, the method 1100 moves to step 1126. If these two possibilities are not taken, the method 1100 proceeds to step 1112, where the p step size is compared to the smallest possible value. If it is too small, the method 1100 decreases the p step size at step 1114 and proceeds to step 1116. Otherwise, the PMOS size converges (step 1118) and the method moves to step 1116. In step 1116, the change direction of the PMOS size is determined. If so, the PMOS value is decreased (step 1120). Then, the method 1100 moves to step 1122. Otherwise, increase the PMOS value, thereby increasing the direction of change. The method 1100 then proceeds to step 1122. Step 1122 does not make a resize decision for another device, but returns to step 1102. If the test at step 1110 passes, the method 1100 proceeds to step 1126, where the direction of change of the total width is also evaluated. If so, the PMOS value is increased, and then the method 1100 proceeds to step 1122. If the direction of change is decreasing, method 1100 proceeds to step 1128, where the PMOS value is decreased, and method 1100 proceeds to step 1122. FIG. 12 shows the correct arrangement of FIGS. 12A and 12B. FIG. 12A is a first part of a flowchart of a method for optimizing the NMOS width of a given logic gate. FIG. 12B is a second part of a flowchart of a method for optimizing the NMOS width of a given logic gate. At step 1202 of the method 1200, it is determined whether the NMOS size has converged. If it has not converged, the method 1200 moves to the return step 1204. If it converges, method 1200 proceeds to step 1206, where the standard cell height and standard load capacity are set. In step 1208, calculate the delay through the gate type with size NMOS, and the method 1200 moves to step 1210. At step 1210, two evaluations are made. One evaluation is based on a comparison that determines whether the standard cell height is less than the height limit. If so, and if the delay has been improved, the method 1200 moves to step 1226. The other evaluation is used when there is no hard limit and the percentage delay improvement is greater than the square of the percentage increase in height. Again, if so, the method 1200 moves to step 1226. If these two possibilities are not taken, the method 1200 proceeds to step 1212, where the n-step size is compared to the smallest possible value. If it is too small, the method 1200 reduces the n step size at step 1214 and proceeds to step 1216. Otherwise, the NMOS size converges (step 1218) and the method moves to step 1216. In step 1216, a change direction of the NMOS size is determined. If it is increasing, decrease the NMOS value (step 1220). The method 1200 then moves to step 1222. Otherwise, increase the NMOS value, thereby increasing the direction of change. The method 1200 then proceeds to step 1222. Step 1222 does not determine the resize of another device, but returns to step 1202. If the test at step 1210 passes, the method 1200 proceeds to step 1226, where the direction of change of the NMOS is also evaluated. If so, the NMOS value is increased, and then the method 1200 proceeds to step 1222. If the direction of change is decreasing, the method 1200 proceeds to step 1228, where the NMOS value is decreased, and the method 1200 proceeds to step 1222. The goal of fast optimization is to achieve a minimum gate delay without excessive area increase. Since the standard cell width does not change significantly with the device size, the area increase is determined by the cell height. To achieve this, the minimum standard cell height is calculated based on the minimum size NMOS and the minimum PMOS of 1 and 1.5 times. The standard cell height is allowed to increase to a nominal 25 percent increase of this minimum. The standard cell height is allowed to further increase beyond this 25% only if the speed increase exceeds the square of the height increase. The device size is calculated to fit this standard cell height using an iterative SPICE simulation that selects the optimal NMOS and PMOS transistor sizes to minimize gate delay. Gate delay is measured as the average of the input rise and fall delays for the three gates in series. Unused inputs are tied high for NAND gates and low for NOR gates. The load on each gate is the subsequent gate and the standard load. The standard load is the sum of the input delay of the four clocked inverters and the wiring capacitance determined by the standard cell height. This load changes as the device size is optimized and reflects the effect of the load capacitance as the device size changes. Optimization is performed on the set of NAND and NOR gates shown in Table 3, "Fast Gate Optimization Step", which determines the transistor size of that gate. Optimization by SPICE establishes the required one, two, and three series NMOS and PMOS transistor sizes to optimize the standard cell library for high speed operation. The four series NMOS and PMOS transistor sizes are set such that four series devices provide pull-up and pull-down currents equal to three series transistor sizes. However, the size of the four series devices is limited to the maximum NMOS and PMOS device width as calculated by the standard cell height routine of this step. The final static noise margin check ensures that the high-speed standard cell library meets the same noise margin requirements as low power optimized cells. FIG. 13 shows the correct arrangement of FIGS. 13A and 13B. FIG. 13A is a first part of a flowchart of a method for maximizing the speed of a given logic gate. FIG. 13B is a second part of a flowchart of a method for maximizing the speed of a given logic gate. In step 1302 of the method 1300, the minimum width of the NMOS is set to ba and the minimum width P_1s of the PMOS is set to 50% of ba. At step 1304, another NMOS device is sized to match the pull-down current N_1s, and another PMOS device is sized to match the pull-up current P_1s. Proceeding to step 1306, the height of the standard cell having the specified device size is calculated. Next, in step 1308, 17 percent is added to the height limit. At step 1310, the size of the two series NMOSs is initialized to be large (ie, a 50% increase in N_2s). In addition, initialization is performed so that the size of one series PMOS becomes small (= ba). Then, using the subroutine opt_np (), iteratively performs SPICE and adjusts the device size to minimize the delay of the 2-input NAND. Following this, step 1314 adds 7 percent to the height limit. At step 1316, the subroutine opt_np () is used to iteratively perform SPICE and adjust the device size to minimize the delay of the two-input NOR. Following this, in step 1318, the standard cell height is calculated with the new device size and used as the height limit. At step 1320, the subroutine opt_n_or_p () is used to iteratively execute SPICE and adjust the device size to minimize the delay of the 3-input NAND. Following this, in step 1322, the standard cell height is calculated with the new device size and used as the height limit. At step 1324, the subroutine opt_n_or_p () is used to iteratively perform the SPICE and adjust the device size to minimize the delay of the 3-input NOR. Following this, step 1326 finds three series N_3s currents and three series P_3s. These values are then used to establish, at step 1328, the minimum of the calculated values and the values of N_4s and P_4s as the individual spaces available for NMOS and PMOS. Finally, in step 1330, the static NM is checked. While the above is a detailed description of the preferred embodiments of the present invention, there are many alternative embodiments of the present invention made by those skilled in the art and within the scope of the present invention. Accordingly, the invention is defined by the appended claims.

────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Jensen, Joan, S.             United States of America, 98407 Washington,             Tacoma, N. 27 Tea H Story             3423 (72) Inventor Rossman, Thomas, F.             United States of America, 98029 Washington,             Isaqua, S. E. 45 tee             Chi Wei 24609

Claims (1)

[Claims] 1. Data on libraries of standard cell elements used in integrated circuit fabrication. In designing a set of vice specifications,   a) determining a process technology for creating the element;   b) determining one optimization criterion from a predetermined set of optimization criteria;   c) specifying a set of library specific knowledge;   d) processing the set of library specific knowledge as process technology and optimization criteria Creating a set of device specifications from it, A method comprising: 2. The predetermined set of optimization criteria is: element speed, element area, and element power. The method of claim 1, comprising power consumption. 3. The set of device specifications includes designation of device size and relative placement. The method of claim 1. 4. 4. The device according to claim 3, wherein the designation of the device size includes a transistor gate width. the method of. 5. 4. The method according to claim 3, wherein the designation of the relative arrangement includes an arrangement of landmarks. . 6. 4. The method according to claim 3, wherein the designation of the relative arrangement includes an assignment of a device type area. The described method. 7. The specification of the relative arrangement includes a specification of a connection point in the standard cell element. The method of claim 3. 8. Library of CMOS standard cell elements used for integrated circuit fabrication In designing a set of device specifications for   a) Determining process technology for creating CMOS standard cell elements Process and   b) determining one optimization criterion from a predetermined set of optimization criteria;   c) specifying a set of library specific knowledge;   d) processing the set of library specific knowledge as process technology and optimization criteria Creating a set of device specifications from it, A method comprising: 9. The predetermined set of optimization criteria is: element speed, element area, and element power. 9. The method of claim 8, including power consumption. 10. The set of device specifications includes device size and relative placement specifications. The method according to claim 8. 11. 11. The device according to claim 10, wherein the designation of the device size includes a transistor gate width. The described method. 12. The method according to claim 10, wherein the designation of the relative arrangement includes an arrangement of a landmark. Method. 13. The designation of the relative arrangement includes the assignment of the device type area. The method of claim 10 comprising: 14． The specification of the relative arrangement includes the specification of a connection point in the standard cell element. The method according to claim 10. 15. The device size is specified by an N-type transistor and a P-type transistor. The method of claim 10 including the relative size of the register. 16. f) The device specification is obtained by using a parameterized library compiler. 11. The method of claim 10, further comprising processing the set. 17． g) Create a library from a parameterized library compiler 17. The method of claim 16, further comprising the step of: 18. A library of standard cell elements used in integrated circuit fabrication. In an apparatus that designs a set of device specifications,   An input circuit that determines the process technology for creating the element;   An input circuit for determining one optimization criterion from a predetermined set of optimization criteria;   A storage device for specifying a set of library-specific knowledge;   Process a set of library specific knowledge as process technology and optimization criteria, A processing circuit for creating a set of device specifications from the An apparatus comprising: 19. The predetermined set of optimization criteria is: element speed, element area, and element 20. The method of claim 18, including power consumption. 20. The set of device specifications includes device size and relative placement specifications. The method according to claim 18.