JPH10319924A - Liquid crystal display panel driving circuit of digital system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce instantaneous power consumption by providing a multiplexer between an output amplifier array and data line of a liquid crystal display panel or the like thereby simplifying the circuit configuration. SOLUTION: This driving circuit 40 is provided with a first latch array 42, the second latch array cascaded to the first latch array 42, a multiplexer 46 and a D-A converter array 48. The first and the second latch arraies are respectively constituted of 2400 pieces of latches or the like. The multiplexer 46 separates 800 pieces of pixel data from the second latch array 44 at a time to transfer them to the D-A converter array 48 side while dividing them in three times. Consequently, the number of converters of the D-A converter array 48 and amplifiers of the output amplifier array 52 is reduced to the half, the one third the number of data lines DL1-DL2400 or a number less than these numbers. Thus, instantaneous power consumption of circuits is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device using a liquid crystal display panel, and more particularly to a digital liquid crystal display panel driving circuit for driving a liquid crystal display panel with a digital video signal.

[0002]

2. Description of the Related Art Recently, as a method for providing a viewer with a high-resolution image on a video medium, a method of transferring a digital video signal, which can easily compress information, instead of an existing analog video signal has been converted. It is a rising trend. As a result, one type of liquid crystal display panel of a video display device has to be driven by a digital video signal instead of an existing analog video signal. Therefore, a driving circuit for a liquid crystal display panel is newly configured to be suitable for driving a pixel or the like of a liquid crystal display panel that requires an analog signal. As a result, in the liquid crystal display panel driving circuit, an existing analog liquid crystal display panel driving circuit and a digital liquid crystal display panel driving circuit coexist.

In such a liquid crystal display panel driving circuit, it is necessary to secure a sufficient signal supply time for accurately applying a voltage corresponding to a video signal to each of pixels and the like on the liquid crystal display panel. In order to solve it, as an analog type liquid crystal display panel drive circuit,
Japanese Patent Application Laid-Open No. 199/1992 discloses a method of sequentially driving two or more pixels on one horizontal scanning line by a fixed number of two or more.
5 (1995) -181933. According to Japanese Patent Publication No. 1995-181933, an analog liquid crystal display panel driving circuit delays a video signal using a delay element, and the delayed video signal is transmitted from an intermediate portion on a horizontal line. The video signal which was not delayed was applied to the pixels reaching the right end, and the video signal which was not delayed was sequentially applied to the pixels reaching the center portion from the left end. Since such an analog type liquid crystal display panel driving circuit directly uses an analog video signal as a driving voltage of a pixel,
Even if the pixels on the horizontal line are driven sequentially two by two,
A sufficient signal supply time could be secured for each pixel.

On the other hand, since a digital liquid crystal display panel driving circuit requires a signal conversion time for converting a digital video signal into an analog video signal, the driving method is disclosed in Japanese Patent Application Laid-Open No. 1995-181933. Depending on such an analog type liquid crystal display panel driving method,
A sufficient signal supply time for each pixel could not be secured. Thereby, the digital liquid crystal display panel driving circuit is configured as shown in FIG. 1 so as to simultaneously drive pixels on one horizontal line.

Referring to FIG. 1, a liquid crystal display panel (1
0) includes 2400 data lines (DL1 to DL2400) connected to 600 pixels and the like arranged in the vertical direction, respectively. Then, the liquid crystal display panel (1
0), a driving circuit (20) for driving 600 × 2400 pixels or the like includes first to third data buses (Data Bulk).
s; a first latch array (22) connected to DB1 to DB3), a second latch array (24) cascade-connected to the first latch array (22), a digital-analog converter array (26), and an output amplifier. It consists of an array (28). First and second latch arrays (22, 2)
4) is composed of 2400 latches or the like. The 2400 latches and the like included in the first latch array (22) are divided into 800 pieces and distributed and connected to the first to third data buses (DB1 to DB3). At the same time, the 2400 latches and the like included in the first latch array (22) are sequentially driven three by three, and the first to third latches are sequentially driven.
Red (hereinafter referred to as “R”) and green (hereinafter referred to as “G”) for one horizontal line from the data buses (DB1 to DB3)
And blue (hereinafter referred to as “B”) pixel data.
And 2400 included in the second latch array (24).
The latches and the like simultaneously receive pixel data from the 2400 latches and the like of the first latch array (22) at the same time and transfer the pixel data to the DA converter array (26). Then, the DA converter array (26) converts all of the 2400 pixel data from the second latch array (24) into pixel signals, and converts the converted 2400 pixel signals into the output amplifier array (28). ).

For this purpose, a DA converter array (26)
Is a common input of a fixed number (for example, 5) of conversion source signals from a gamma correction unit (not shown).
It is composed of 00 DA converters and the like. This 2400
D / A converters and the like are respectively connected to the second latch array (2
4) According to the logical value of the pixel data from the corresponding latch,
A pixel signal is generated by adding a part or all of the converted source signal and the like. Finally, the output amplifier array (28) amplifies the 2400 pixel signals and the like from the DA converter array (26) at a constant amplification factor, and displays the amplified 2400 pixel signals and the like on a liquid crystal display. 2400 data lines (DL1 to DL1) of panel (10)
2400). To that end, the output amplifier array (28) also has a 240
It has 2400 output amplifiers and the like dispersedly connected to 0 DA converters and the like.

As described above, the conventional digital liquid crystal display panel driving circuit can simultaneously drive pixels and the like for one horizontal line on the liquid crystal display panel and sufficiently secure a signal supply time for each pixel. Was. However, in a conventional digital liquid crystal display panel driving circuit, a D / A converter and an output amplifier corresponding to the number of pixels included in a horizontal line of the liquid crystal display panel must be used. Needless to say, this becomes complicated, and its bulk also increases. In addition, in a conventional digital liquid crystal display panel driving circuit, a large number of DA converters and output amplifiers have to be driven at the same time, so that instantaneous power consumption becomes extremely large.

[0008]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital liquid crystal display panel driving circuit capable of simplifying a circuit configuration and reducing instantaneous power consumption. is there.

Another object of the present invention is to provide a digital liquid crystal display panel driving circuit capable of reducing the number of lead lines of the liquid crystal display panel.

[0010]

In order to achieve the above object, a digital liquid crystal display panel driving circuit according to the present invention comprises a multiplexer for selecting k digital pixel data from n digital pixel data. With an array,
A digital-to-analog converter array for converting k digital pixel data from the multiplexer array to k analog pixel signals, and k data lines connected to n data lines; And a demultiplexer array for transferring the k analog pixel signals from the digital-to-analog converter array to the selected k data lines at the same time.

A method of driving a digital liquid crystal display panel according to the present invention includes the steps of selecting k digital pixel data from n digital pixel data, and converting the k digital pixel data from a multiplexer array to k digital pixel data. Converting the k analog pixel signals from the digital-to-analog converter into k analog data signals; and selecting the k analog pixel signals from the n data lines. Transferring to a line.

In the digital liquid crystal display panel driving circuit according to the present invention, the number of lead lines of the liquid crystal display panel is minimized by mounting the multiplexer array on the liquid crystal display panel. A digital liquid crystal display panel driving circuit according to the present invention includes a demultiplexer array between a latch array for temporarily storing one line of pixel data and a DA converter array for converting the pixel data into pixel signals. And by installing a multiplexer between the output amplifier array and the data lines of the liquid crystal display panel, etc., the number of DA converters and output amplifiers can be reduced to half, one third or less of the number of data lines. Can be done. Accordingly, the digital liquid crystal display panel driving circuit according to the present invention can not only achieve simplification of the circuit configuration, but also can reduce instantaneous power consumption. In addition, the digital liquid crystal display panel driving circuit according to the present invention can reduce the number of lead-out lines of the liquid crystal display panel by mounting the multiplexer on the liquid crystal display panel.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the present invention other than the above will become apparent through the following detailed description of preferred embodiments with reference to the accompanying drawings.

Referring to FIG. 2, there is shown a liquid crystal display device including a digital liquid crystal display panel driving circuit according to an embodiment of the present invention. In FIG. 2, the liquid crystal display device includes a liquid crystal display panel driving circuit (40) connected to the liquid crystal display panel (30). LCD panel (3
0) are 2400 data lines (D) commonly connected to 600 pixels and the like arranged in the vertical direction, respectively.
L1 to DL2400).

On the other hand, 600 on the liquid crystal display panel (30)
× 2 400 driving circuits for driving pixels and the like (4
0) is the first to third data buses (DB1 to DB3)
, A second latch array (44), a multiplexer array (46), and a DA converter array (48) cascaded to the first latch array (42). . The first and second latch arrays (42, 44) each include 2400 latches and the like. The 2400 latches and the like included in the first latch array (42) are divided into 800 pieces each, and are distributedly connected to the first to third data buses (DB1 to DB3). In addition, the 24 included in the first latch array (42)
The 00 latches and the like are sequentially driven three by three, and input R, G, and B pixel data for one horizontal line from the first to third data buses (DB1 to DB3). The 2400 latches and the like included in the second latch array (44) simultaneously receive pixel data from the 2400 latches and the like of the first latch array (42) and transfer the pixel data to the multiplexer array (46) side. .

The multiplexer array (46) converts the 2400 pixel data from the second latch array (44) into 8
It is divided into 00 pieces and transferred to the DA converter array (48) three times. To this end, the multiplexer array (46) includes first to third control lines (S
L1 to SL3) to the first to third switching control signals (S
WS1 to SWS3) and 800 multiplexers (MP1 to MP800). Each of the 800 multiplexers is controlled by the first to third switching control signals (SWS1 to SWS3) which sequentially have a logical value of "1" for one horizontal period as shown in FIG. , The three pixel data from the three latches of the second latch array (44) are sequentially transferred to the DA converter array (48). For this purpose, each of the 800 multiplexers and the like (MP1 to MP800) receives the first to third switching control signals (SWS1 to SWS).
3) is constituted by three sets of MOS transistors (MF) that receive the respective signals on the gate side. Here, three sets of M
The number of OS transistors (MF) must be 15 when the pixel data is 5 bits, but is represented as 3 for convenience. 3 included in one multiplexer (MP)
The sources and the like of the set of MOS transistors (MF) are respectively connected to three latches included in the second latch array (44), and the three sets of MOS transistors (M
The drain and the like in F) are commonly connected for each bit of the pixel data. At the same time, three sets of MOS transistors (MF) included in one multiplexer (MP) are set to 1 by the first to third switching control signals (SWS1 to SWS3).
The pixel data is sequentially turned on during the horizontal period, and the pixel data from the corresponding latch of the second latch array (44) is applied to the D-
The data is transferred to the A converter array (46). Then D
The -A converter array (48) converts all 800 pixel data from the multiplexer array (46) to pixel signals. For this purpose, a DA converter array (48)
80 commonly receives at least a fixed number (for example, 5) of conversion source signals from the gamma correction unit (50).
It is composed of zero DA converters. These 800 D
Each of the -A converters and the like is provided with a corresponding multiplexer (M
The pixel data is converted into an analog pixel signal by selectively adding all or a part of a fixed number of conversion source signals from the gamma correction unit (50) to the logical value of the pixel data from P). As a result, 800 D-
Each of the A-converters and the like converts three pieces of pixel data into analog pixel signals in one horizontal scanning period.

The driving circuit (40) includes an output amplifier array (52) connected in series between the DA converter array (48) and the data lines (DL1 to DL2400) of the liquid crystal display panel (30). A demultiplexer array (54). The output amplifier array (52)
Amplify 800 pixel signals and the like from the -A converter array (48) at a constant amplification factor, and output the amplified 800 pixel signals and the like to the demultiplexer array (54) side. Therefore, the output amplifier array (52) is also DA
It is composed of 800 output amplifiers and the like dispersedly connected to 800 DA converters and the like of the converter array (48).
Finally, the demultiplexer array (54) converts the 800 amplified pixel signals from the output amplifier array (52) to 2400 data lines (DL1 to DL24).
00), the data is sequentially transferred three times for every 800 data lines. To this end, the demultiplexer array (54) includes first to third control lines (SL), respectively.
1 to SL3) from the first to third switching control signals (SW)
It is composed of 800 demultiplexers and the like (DMP1 to DMP800) that receive S1 to SWS3).
These 800 demultiplexers (DMP1 to DMMP)
P800) sequentially has a logical value of "1" for one horizontal period as shown in FIG.
The pixel signals from the output amplifier array (52) are sequentially transferred to three data lines (DL) according to the third to third switching control signals (SWS1 to SWS3). Therefore, 800 demultiplexers (DMP1 to DMP1)
MP800) is composed of three MOS transistors (MS) receiving the first to third switching control signals (SWS1 to SWS3) on the gate side, respectively. 1
Three Ms included in one demultiplexer (DMP)
The source and the like of the OS transistor (MS) are commonly connected to the output terminal of one output amplifier included in the output amplifier array (52), and the drain and the like are distributed and connected to three data lines (DL). You. In addition, the three MOS transistors (MS) included in one demultiplexer (DMP) are connected to the first to third switching control signals (SWS1).
SWS3) to turn on each other sequentially for one horizontal period, and distribute and supply pixel signals and the like from the corresponding output amplifier included in the output amplifier array (52) to three data lines (DL).

[0018]

As described above, the digital liquid crystal display panel driving circuit according to the present invention comprises a latch array for temporarily storing one line of pixel data and a DA converter for converting the pixel data into pixel signals. By installing a multiplexer array between the array and the output amplifier array and a data line of the liquid crystal display panel, etc., the number of DA converters and output amplifiers can be reduced to half of the number of data lines. It can be reduced to one third or less. Accordingly, the digital liquid crystal display panel driving circuit according to the present invention can achieve not only simplification of the circuit configuration but also reduction of instantaneous power consumption. In addition, the digital liquid crystal display panel driving circuit according to the present invention can reduce the number of lead lines of the liquid crystal display panel by mounting the multiplexer on the liquid crystal display panel.

From the above description, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore,
The technical scope of the present invention is not limited to the content described in the detailed description of the specification, but must be defined by the appended claims.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a liquid crystal display device to which a conventional liquid crystal display panel driving circuit for digital video signals is applied.

FIG. 2 is a view illustrating a liquid crystal display device to which a digital liquid crystal display panel driving circuit according to an embodiment of the present invention is applied;

3 is an operation timing chart of each part of the drive circuit shown in FIG. 2;

[Explanation of symbols]

 10, 30: liquid crystal display panel 20, 40: liquid crystal display panel drive circuit 22, 42: first latch array 24, 44: second latch array 26, 48: DA converter array 28, 52: output amplifier array 46: multiplexer Array 50: Gamma correction unit 54: Demultiplexer array

Claims (11)

[Claims] 1. A multiplexer array for selecting k digital pixel data from n digital pixel data, and k number of digital pixel data from the multiplexer array are converted into k analog pixel signals. And a digital-to-analog converter array connected to n data lines for selecting k from the n data lines and for converting k analog pixel signals from the digital-to-analog converter array. And a demultiplexer array for transferring the data to the selected k data lines. 2. The digital liquid crystal according to claim 1, further comprising: n data lines arranged in a line in a horizontal direction and commonly connected to m pixels arranged in a vertical direction. Display panel drive circuit. 3. The digital liquid crystal display panel driving circuit according to claim 2, wherein said demultiplexer array is mounted on a liquid crystal display panel. 4. The apparatus according to claim 1, further comprising a storage unit for temporarily storing the input n digital pixel data and inputting the n digital pixel data to the multiplexer array. Item 2. A digital liquid crystal display panel drive circuit according to item 1. 5. The apparatus according to claim 1, further comprising an output amplifier array provided between said digital-to-analog converter array and said demultiplexer array.
A digital liquid crystal display panel driving circuit as described in the above. 6. The digital liquid crystal display panel driving circuit according to claim 1, wherein said multiplexer array and said demultiplexer array are composed of MOS transistors. 7. The selection time of the demultiplexer is k.
2. The digital liquid crystal display panel driving circuit according to claim 1, wherein the driving circuit corresponds to / n. 8. Selecting k digital pixel data from n digital pixel data, and selecting the selected k digital pixel data.
Converting the digital pixel data into k analog pixel signals, selecting k from n data lines, and converting the converted k analog pixel signals into the selected analog pixel signals. transferring the data to k data lines. 9. The method as claimed in claim 8, further comprising temporarily storing n digital pixel data, wherein the stored data is used as the n digital pixel data.
The driving method of the digital liquid crystal display panel according to the above. 10. The digital liquid crystal display panel driving method according to claim 8, further comprising amplifying the converted k analog pixel signals. 11. The method of claim 1, wherein the step of selecting k from the n data lines comprises selecting k from the n data lines for a time corresponding to k / n. A method for driving a digital liquid crystal display panel according to claim 8.