JPH10284638A - Structure of ceramic chip size package - Google Patents

Abstract

(57) [Summary] [PROBLEMS] A high-speed LSI capable of forming a power supply / GND solid layer
CCSP that enables the application of solder, ensures the flatness of the tip of the solder ball, further improves productivity and reduces costs
Structure. A ceramic main substrate having a smaller outer shape and a land on which a solder ball is mounted is laminated on a ceramic sub-substrate around which bonding stitches are arranged so that the bonding stitches are exposed. An LSI that has a ceramic chip size substrate and has electrode pads around it has a structure in which the electrode pads are arranged outside the bonding stitches of the slave substrate, and the connection part that connects the bonding stitches and the electrode pads with wires is made of resin. A solder ball is provided on the land covered on the ceramic CSP substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a container for mounting a semiconductor device, and more particularly to a structure of a chip size package using ceramic.

[0002]

2. Description of the Related Art A conventional chip size package technology will be described with reference to the drawings.

FIG. 10 is a cross-sectional view showing an example of a configuration disclosed in Japanese Patent Application Laid-Open No. 7-32244 as a first prior art. Referring to FIG. 10, bumps 11 are mounted on electrode portions on LSI 8. In the package, a TAB lead 10-1 and a resin dam 10-3 are provided on the film carrier 10, and solder balls 6 are provided on the TAB lead on the outer periphery of the package.
Are connected. For mounting on the LSI, the LSI 8 and the film carrier 10 are connected by an adhesive layer (not shown) below the film carrier. At this time, the tip (the innermost peripheral portion) of the TAB lead has a structure electrically connected to the bump. After mounting the package on the LSI, the resin dam 10
The resin is allowed to flow into the inside of -3 to be cured.

FIG. 11 is a cross-sectional view showing a configuration disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 7-32244 as a second prior art. Referring to FIG. 11, this second prior art is:
The structure is substantially the same as that of FIG. The difference is the LSI
8 and bonding wires 5 instead of bumps
That's what we're doing.

FIG. 12 is a perspective view showing the appearance of a third conventional technique. Referring to FIG. 12, in the third prior art, an LSI 8 has a film carrier 10 of the same size in plan view.
It has. The core (important point) is the insulating film 10-
2 and an adhesive layer 10 on the lower side (the side connected to the LSI 8).
-6, an electrode lead 10-1 is provided around the upper part of the film carrier 10, and a land 10-8 is provided in the center, and both are electrically connected by a wiring 10-7. A via hole 10-5 is formed in a portion of the LSI 8 facing the electrode pad 8-1. The via hole 10-5 is electrically connected to the electrode lead 10-1, and the electrode pad 8-1 has a structure that slightly protrudes from the adhesive layer 10-6.

[0006] After alignment, the via holes 10-5 are thermocompression-bonded to the LSI 8 (using a TAB / ILB bonder).
Then, heat is applied to the whole to uniformly connect the film carrier 10 and the LSI 8. After that, the solder balls 6 are attached.

FIG. 13 is a perspective view showing the appearance of the fourth prior art. Referring to FIG. 13, the basic structure of the fourth prior art is the same as that of FIG. 12 (third prior art).
The difference is that an outer frame 10-9 is provided around the LSI 8, the electrode leads extend to the outer frame 10-9, and are connected to the lands of the outer frame by wiring. With this structure, it is possible to increase the number of terminals (the number of solder balls) without reducing the pitch of the solder balls 6. Also, since the package is larger than LSI 8, LS
In order to fix the outer frame to I, a structure in which the back surface of the LSI is covered with a resin 7 is adopted.

FIG. 14 is a sectional view showing the structure of the fifth prior art. Referring to FIG. 14, the structure of the fifth prior art is very similar to that of FIG. 12 (third prior art).
The difference is that the bump 11 is interposed at the connection between the TAB lead 10-1 and the LSI 8, the outer frame 15 is provided, and the resin 7 is provided between the outer frame 15 and the package.
To fix the outer frame.

FIG. 15 is a sectional view showing the structure of the sixth prior art. Referring to FIG. 15, the sixth prior art has a structure in which a bump 11 is provided on a peripheral electrode portion of an LSI 8 and is directly connected to a ceramic carrier 12, that is, a so-called flip-chip connection is performed. LSI8
The resin 7 is filled between the substrate and the ceramic carrier 12 by using a capillary phenomenon (underfill). Further, the pitch conversion is performed by forming the solder balls 6 on the lower part (the lower part in FIG. 14) of the ceramic carrier 12.

FIG. 16 is a sectional view showing the structure of a seventh conventional technique. Referring to FIG. 16, the structure of the seventh prior art is similar to that of the first and second prior arts.
That the electrode frame is provided at the center of the lead frame 13, that the lead frame 13 is attached via an adhesive layer 10-6 instead of the film carrier (LOC structure), and that the wire 5 is connected to the LSI 8 and the lead frame 13. The feature is that it is used. Also, the connection part is made of resin 7
And the outer periphery of the lead frame 13 is slightly exposed from the resin.

FIG. 17 is a sectional view showing the structure of an eighth prior art. Referring to FIG. 17, in the eighth prior art, a bump 11 is formed on an electrode pad on an LSI 8, and then the whole is covered with a mold resin. At this time, control is performed so that the tip of the bump 11 is slightly exposed from the resin 14. After that, the solder ball 6 is formed at the tip of the bump 11.

[0012]

Each of the above-mentioned prior arts has the following problems.

(1) The first problem is that L operates at high speed.
This is a point that application to SI is difficult.

The reason is that, in each package structure except for the sixth prior art (see FIG. 15), the lead-out from the connection portion with the LSI to the electrode (solder ball or the outer peripheral portion of the lead frame) outside the package is one-to-one. This is because the structure does not include (cannot exist) a GND layer lining the signal wiring and a power supply layer / GND layer capable of reducing the inductance of the power supply / GND.

Therefore, (a) the characteristic impedance of the signal wiring cannot be kept constant, (b) noise generated by the simultaneous operation of signals is applied to other wirings, and (c) the level of the reference GND potential. Fluctuated.

In the sixth prior art, since the ceramic carrier is used, the power supply and GND layers can be laminated inside. Therefore, the above problem can be avoided. However, since flip chip connection is performed, (A) It is necessary to form a bump (high-temperature solder) on the electrode portion of the LSI, (b) LS
I ~ Special bonder (flip chip bonder) is required to connect ceramic carrier, (c) Special resin sealing device for underfill (filling resin by capillary action while warming) is required, etc. There are problems such as the inability to apply a production line and the increase in costs due to a significant increase in processes.

(2) The second problem is that the multi-pin large LSI
Then, it is difficult to keep the external electrodes such as the solder balls and the lead frame tips flat.

The reason is that in each package other than the sixth and eighth prior arts, a film carrier is used as a base. Since the film carrier has a flexible structure, it is relatively easy to handle, but on the other hand, the unevenness of the adhesive layer corresponding to the connection portion with the LSI is directly reflected on the unevenness of the film carrier. Causes the flatness of the substrate to deteriorate. Therefore, as the size of the LSI increases, the in-plane uniformity deteriorates, and it becomes difficult to maintain the yield.

On the other hand, the sixth and eighth prior arts which do not use a film carrier also have a problem that the bump height must be suppressed because bumps are formed on LSI pads. In particular, since the bump pitch is the same as the electrode pad pitch of the LSI, the diameter of the bump is extremely smaller than that of the external solder ball. However, since the dimensional tolerance cannot be reduced accordingly, there is a problem that it is difficult to control the variation in height.

(3) The third problem is that in the first, third, fourth, fifth, sixth and eighth prior arts, a TAB bonder, a flip chip bonder, and an IBB bonder (inner bump bonding bonder). That is, the cost is increased because a general-purpose wire bonder is not used. The second and seventh prior arts are advantageous because they can be dealt with by a general-purpose wire bonder.

(4) The fourth problem is that chip components such as chip capacitors cannot be mounted.

The reason for this is that the space cannot be secured, and as described in the first problem, the power supply layer and the GN
This is because the D layer is not provided inside the package.

Therefore, the present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to solve the above-mentioned problems and to design a transmission line having good characteristics, thereby increasing the speed and transmission. It is an object of the present invention to provide a structure of a ceramic chip size package which can improve the efficiency, achieve the improvement of the productivity, suppress the increase in the cost, and further ensure the flatness of the tip of the solder ball.

[0024]

In order to achieve the above object, the structure of a ceramic chip size package according to the first invention of the present application has a structure in which a bonding stitch is arranged around a ceramic sub-substrate, which is smaller than the ceramic sub-substrate. A ceramic chip size substrate (referred to as a “ceramic CSP substrate”) having a structure in which a ceramic main substrate having a small outer shape and having a land for mounting solder balls is laminated so that the bonding stitches are exposed, and electrode pads are provided around the substrate. Has a structure in which the electrode pads are arranged outside the bonding stitches of the ceramic sub-substrate, a connection portion connecting the bonding stitches and the electrode pads of the LSI with wires is covered with resin, A solder ball is provided on the land on the ceramic CSP substrate. Comprising Te, characterized in that.

Further, the structure of the ceramic chip size package according to the second invention of the present application is a ceramic chip size substrate (hereinafter referred to as a ceramic chip size substrate) which is formed by laminating a ceramic main substrate having lands on which solder balls are mounted on a ceramic subsidiary substrate. A ceramic CSP substrate), the outer dimension of the ceramic sub-substrate is larger than the LSI to be connected, and a slit-shaped opening window is provided at a position corresponding to a peripheral electrode pad of the LSI. Bonding stitches are installed on one or both sides of the opening window in parallel, the ceramic main substrate includes an outer peripheral portion connected along the outside of the opening window, and a portion arranged in an island shape inside the opening window, and The ceramic sub-substrate and the ceramic main substrate are alternately exposed so that the bonding stitches of the ceramic sub-substrate are exposed. Laminated on said ceramic C
An SP substrate is connected so that the electrode pad of the LSI is exposed from the opening window, a wire is connected between the electrode pad of the LSI and the bonding stitch, and the LSI and the ceramic at the wire connection point and the back surface of the LSI are connected. The CSP substrate is covered with a resin, and a land portion is provided with a solder ball.

According to a third aspect of the present invention, in the second aspect, electrodes electrically connected to a power supply layer and a GND layer are provided on the ceramic CSP substrate outside the back surface of the LSI, respectively. And a chip component is mounted on the electrode portion.

The ceramic ceramic according to the fourth invention of the present application.
The structure of the chip size package may be the same as that of the first, second, or third aspect of the invention.
A power supply layer or a GND layer having a planar spread or at least one of these layers is formed inside the substrate.

[0028]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, the ceramic chip size package (CSP) substrate is divided into a ceramic main substrate (1-1 in FIG. 2) and a ceramic sub-substrate (1-2 in FIG. 2). These are laminated and integrated.

First, the ceramic sub-substrate has a bonding stitch (3-1 in FIG. 2) on the outer peripheral portion, and routes wiring from the bonding stitch to the internal connection via. The outer shape of the ceramic sub-board is made smaller than the peripheral electrode pad area of the LSI (8 in FIG. 2) to be mounted. A GND layer (solid layer) is provided below the wiring as needed.

The outer dimensions of the ceramic main substrate (1-1 in FIG. 2) are smaller than those of the ceramic sub-substrate (1-2 in FIG. 2), and bonding stitches (3- in FIG. 2) are formed on the sub-substrate.
Laminate so that 1) is exposed.

The vias (4 in FIG. 2) are connected from the wiring vias of the ceramic subsidiary substrate to the lands on the surface. A power supply layer and a GND layer (each solid layer) (3-3 in FIG. 2) are provided as needed between the surface (land surface) and the ceramic subsidiary substrate. In terms of shape, a layer configuration including a GND layer, a signal wiring (a wiring layer including from a bonding stitch to a connection via), a GND layer, a power supply layer, and a land above the LSI connection surface of the ceramic CSP substrate is advantageous in terms of electrical characteristics. It is.

Explaining the mounting, a ceramic CSP substrate (a substrate in which a slave substrate and a main substrate are integrated) is mounted on an LSI via an adhesive layer (see FIG. 3B). After that, the LSI electrode pad ~
Connect the bonding stitches (see FIG. 3C),
After sealing the connection portion with resin (see FIG. 4D), the solder ball 6 is connected to the land 2 portion (see FIG. 4E and FIG. 2).

With the above structure, the signal wiring is GN up and down.
Since it is sandwiched between D layers (solid layers), it is possible to design a transmission line having an arbitrary characteristic impedance based on the wiring width, GND to wiring interval, and the relative permittivity of ceramic. Margin against crosstalk noise (simultaneous operation noise) In addition, since the GND and the power supply are electrically connected with a low inductance, there is an effect on characteristics that a potential change hardly occurs.

In addition, the conventional problems such as the use of a general-purpose wire bonder, the process cost is low, and the unevenness of the land surface is small due to the use of the ceramic, so that the flatness of the tip of the solder ball is improved. Solvable. The mounting of chip components and the like will be described in detail in the embodiments described later.

[0035]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[First Embodiment] FIG. 1 is a perspective view showing an appearance of a first embodiment of the present invention, and FIG.
It is sectional drawing of the A 'line. In the present embodiment, the ceramic CSP substrate 1 has a structure in which two components of a ceramic main substrate 1-1 and a ceramic sub-substrate 1-2 are laminated and integrated.

The ceramic sub-substrate 1-2 has a bonding stitch 3-1 on the outer periphery and is connected to the via hole 4 by wiring. The outer shape of the ceramic main substrate 1-1 is smaller than that of the slave substrate, and the ceramic main substrate 1-1 is laminated on the ceramic slave substrate 1-2 so that the bonding stitches 3-1 of the ceramic slave substrate 1-2 are exposed to the outside. The wiring of the ceramic sub-board 1-2 is routed from the via hole 4 toward the land 2.

The signal wiring (routing portion from the bonding stitch 3-1 to the internal via hole 4) is GN up and down.
It has a structure sandwiched between D layers 3-3. This GND layer 3-3
Are connected in the vicinity of bonding stitches (corresponding to GND) by via holes (not shown), and are connected to each other by a plurality of via holes (not shown). Although not shown in the cross-sectional view of FIG. 2, the land portion and the GND layer 3-3
It is also possible to provide a power supply layer between them.

A method of manufacturing the ceramic chip size package (CCSP) will be described with reference to FIGS. FIG. 3 and FIG. 4 are perspective views showing the manufacturing of the present example in the order of steps.

The ceramic CSP substrate 1 is set on the LSI 8 via an adhesive layer (not shown). FIG. 3A shows a state after alignment, and FIG. 3B shows a state after mounting. The electrode pad 8-1 of the LSI 8 is designed in advance so as to be arranged outside the bonding stitch 3-1. That is, the outer peripheral portion of the ceramic CSP substrate 1 is
8 is designed to be inside the electrode pad region.

After that, as shown in FIG. 3C, the bonding pad 5 connects the electrode pad 8-1 to the bonding stitch 3-1.

Next, as shown in FIG.
Is sealed with resin. The resin 7 is formed using a molding die or the like.
A portion surrounded by a vertical line at the outer end of the SI8 and a horizontal line from the surface of the ceramic main substrate 1-1 is sealed.

Thereafter, the solder balls 6 are attached to the lands 2 (see FIG. 4E).

Now, the ceramic is made of alumina (relative permittivity =
9.6), if the distance between the signal wiring and the GND solid layer is 0.25 mm and the wiring width is 0.1 mm, the characteristic impedance of the signal wiring can be kept constant at about 50 ohms.

The clearances from the upper and lower GND solid layers to the outside are each 0.1 mm, and the thickness of the LSI is 0.1 mm.
If it is 35 mm, the package thickness excluding the solder ball portion is 1.05 mm, and the SOP (small o
ut line package).

[Second Embodiment] A second embodiment of the present invention will be described. FIG. 5 is a perspective view of a second embodiment of the present invention, FIG. 6 is a cross-sectional view taken along the line AA 'of FIG. 5, and FIG. 7 is a perspective view showing the manufacturing steps in order.

In this embodiment, unlike the first embodiment, the shapes of the ceramic main substrate 1-1 and the ceramic sub-substrate 1-2 constituting the ceramic CSP substrate 1 are changed. The ceramic sub-board 1-2 has an outer dimension larger than that of the LSI 8, and has a slit-shaped opening window 1-3 at a position corresponding to the electrode pad of the LSI 8 (see FIG. 7).
Bonding stitches 3-1 are arranged on both sides of the opening window 1-3 in parallel with the opening window 1-3. The ceramic main substrate 1-1 having the land portion 2 has a ring shape surrounding the outer peripheral portion of the outer bonding stitch and a ceramic main substrate 1-1 connected to the inner peripheral portion of the inner bonding stitch in an island shape. Are laminated on the ceramic main substrate 1-2.

The bonding stitches 3-1 on the inner and outer circumferences of the ceramic sub-board 1-2 are routed to the inner and outer via holes 4 by wiring. The wiring is routed from the via hole toward the land 2 inside and outside the main substrate (see FIG. 6). The signal wiring 3-2 (the part extending from the bonding stitch to the internal via hole window) is disposed above and below the GND layer 3-2.
Take a structure sandwiched by 3. The GND layer 3-3 is connected via a via hole (not shown) in the vicinity of a bonding stitch (corresponding to GND), and is connected to each other via a plurality of via holes (not shown). Although not shown in the cross-sectional view of FIG. 6, a power supply layer can be provided between the land portion and the GND layer 3-3.

The ceramic CSP substrate having the above structure is mounted on the LSI 8 via an adhesive layer (not shown). Thereafter, wire bonding is performed (see FIG. 7A), and the space between the ring-shaped main substrate and the island-shaped main substrate is filled with the resin 7. Further, a region surrounded by the side surface of the LSI and the ceramic CSP substrate is also filled with the resin (see FIG. 7B). Finally, a solder ball is mounted on the land 2 (see FIG. 7C).

With this structure, it is possible to increase the number of pins without increasing the solder ball pitch.

Now, the ceramic is made of alumina (relative permittivity = 9.
6), and set the distance between the signal wiring and the GND solid layer to 0.
If the wiring width is 25 mm and the wiring width is 0.1 mm, the characteristic impedance of the signal wiring can be kept constant at about 50 ohms.

The clearances from the upper and lower GND solid layers to the outside are each 0.1 mm, and the thickness of the LSI is 0.1 mm.
If it is 35 mm, the package thickness excluding the solder ball portion is 1.05 mm, and the height can be made smaller than the SOP.

[Third Embodiment] A third embodiment of the present invention will be described below. FIGS. 8A and 8B are perspective views of a third embodiment of the present invention, wherein FIG. 8A is a view from the front side and FIG. 8B is a view from the back side. FIG. 9 is a diagram showing a cross section taken along the line AA 'in FIG. The difference between the structure of the present embodiment and the second embodiment is that the power supply layer 3-4 is provided further below the GND layer 3-3 below the signal wiring 3-2. And a ceramic substrate 1 via a via hole from the GND layer 3-3.
-2 The back surface (the back surface of the ceramic CSP substrate) is formed with electrodes 3-5, and the chip capacitor 9 is provided between the electrodes. Note that the chip capacitor mounting side is not filled with resin in the figure, but may be filled with resin.

The present embodiment has a structure in which a plurality of chip capacitors can be inserted between the power supply and GND, so that the capacitance value between the power supply and GND is greatly increased as compared with the first and second embodiments. In addition, there is an effect that it becomes strong against noise of the power supply system.

[0055]

As described above, according to the present invention, the following effects can be obtained.

(1) The first effect of the present invention is that electric characteristics are improved. That is, by sandwiching the signal wiring between the upper and lower sides of GND, the characteristic impedance of the wiring can be arbitrarily set (designed), the inductance of GND / power supply can be reduced, potential fluctuation can be prevented, and crosstalk between signal lines can be reduced. However, there is an effect that simultaneous operation noise can be prevented. By this, GTL
(Gunning tranceiver logic), HSTL (high sp
It is possible to mount an LSI for handling a signal having a small amplitude such as eed transmission logic) and operating at a high speed.

The reason is that, in the present invention, ceramics which can easily realize multilayer wiring are used for the substrate.

(2) A second effect of the present invention is that the use of general-purpose equipment for assembly can suppress an increase in cost.

The reason is that, in the present invention, a general-purpose wire bonding apparatus can be used by devising the shape.

(3) The third effect of the present invention is that the flatness (about 50 microns) of the solder ball portion can be ensured.

The reason for this is that, in the present invention, a ceramic having good flatness and high hardness is used.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a sectional view showing a configuration of a first exemplary embodiment of the present invention.

FIG. 3 is a perspective view showing a manufacturing process of the first embodiment of the present invention in the order of processes.

FIG. 4 is a perspective view showing the manufacturing steps of the first embodiment of the present invention in the order of steps.

FIG. 5 is a perspective view showing a second embodiment of the present invention.

FIG. 6 is a sectional view showing a second embodiment of the present invention.

FIG. 7 is a view showing the manufacturing steps of the second embodiment of the present invention in the order of steps.

FIG. 8 is a perspective view showing a configuration of a third exemplary embodiment of the present invention.

FIG. 9 is a sectional view showing a configuration of a third example of the present invention.

FIG. 10 is a cross-sectional view showing a configuration of a first related art (Japanese Patent Laid-Open No. 7-32244).

FIG. 11 is a cross-sectional view showing a configuration of a second related art (Japanese Patent Laid-Open No. 7-32244).

FIG. 12 is a perspective view showing a configuration of a third conventional technique.

FIG. 13 is a perspective view showing a configuration of a fourth conventional technique.

FIG. 14 is a sectional view showing a configuration of a fifth conventional technique.

FIG. 15 is a sectional view showing a configuration of a sixth conventional technique.

FIG. 16 is a sectional view showing a configuration of a seventh conventional technique.

FIG. 17 is a perspective view showing a configuration of an eighth conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Ceramic CSP board 1-1 Ceramic main board 1-2 Ceramic sub-board 2 Land 3 Wiring layer 3-1 Bonding stitch 3-2 Signal wiring 3-3 GND layer 3-4 Power supply layer 3-5 Electrode 4 Via hole 5 Bonding wire Reference Signs List 6 solder ball 7 resin 8 LSI 8-1 electrode pad 9 chip capacitor 10 film carrier 10-1 TAB lead 10-2 insulating film 10-3 resin dam 10-4 electrode lead 10-5 via hole 10-6 adhesive layer 10-7 Wiring 10-8 Land 10-9 Outer frame 11 Bump 12 Ceramic carrier 13 Lead frame 14 Mold resin 15 Outer frame

Claims (5)

[Claims] 1. A ceramic main substrate having a land smaller than a ceramic sub-substrate and having a solder ball mounted thereon is formed on a ceramic sub-substrate having a bonding stitch disposed therearound so that the bonding stitch is exposed. An LSI having a ceramic chip size substrate (hereinafter referred to as a “ceramic CSP substrate”) having a laminated structure and having electrode pads around the LSI has a structure in which the electrode pads are arranged outside the bonding stitches of the ceramic subsidiary substrate. A connection portion for connecting the bonding stitch and an electrode pad of the LSI with a wire is covered with a resin, and the land on the ceramic CSP substrate is provided with a solder ball; Package (CCSP) structure. 2. A ceramic chip-size substrate ("Ceramic CSP") comprising a ceramic main substrate having a land on which solder balls are mounted on its surface, laminated on a ceramic sub-substrate.
The ceramic sub-substrate has an outer dimension larger than an LSI to be connected, and has a slit-shaped opening at a position corresponding to a peripheral electrode pad of the LSI. A bonding stitch is installed on one side or both sides of the opening window, and the ceramic main substrate is composed of an outer peripheral portion extending along the outside of the opening window, a portion arranged in an island shape inside the opening window, and the ceramic sub-substrate. The ceramic sub-substrate and the ceramic main substrate are laminated on each other so that the bonding stitches are exposed, and the ceramic CSP substrate is connected such that the electrode pads of the LSI are exposed from the opening windows. And the bonding stitch are connected by a wire, and the LS on the wire connection point and the backside of the LSI Said ceramic CSP and the substrate covered with a resin, comprising comprises a solder ball on the land portion, and wherein the ceramic chip size package and (CCSP)
Structure. 3. The ceramic C outside the back surface of the LSI.
3. The electrode according to claim 2, wherein electrodes electrically connected to the power supply layer and the GND layer are provided on the SP substrate so as to face each other, and a chip component is mounted on the electrode. Ceramic chip size package (C
CSP) structure. 4. The ceramic CSP substrate according to claim 1, wherein at least one of a power supply layer, a GND layer, and at least one of these layers is formed to have a two-dimensional spread. The structure of the ceramic chip size package (CCSP) according to one of the above. 5. The structure of a ceramic chip size package (CCSP) according to claim 1, wherein said ceramic material is made of at least one of alumina, mullite, and AlN. .