JPH10275484A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [PROBLEMS] To provide an AND-type flash memory capable of miniaturizing a memory cell and having an operation method in which deterioration due to hot holes is suppressed. SOLUTION: A data line D1 (D2) and a source line S1 are provided.
Memory cells M11 and M12 connected between (S2)
One or more MOS transistors TR1 (TR2) are connected in parallel to (M21, M22). Since the source terminal is charged and discharged via the MOS transistor and the dummy memory cell, hot electrons are not injected into the non-selected memory cells on the same word line, and the threshold voltage does not change. A dummy memory cell having the same configuration as the memory cell may be used instead of the MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having an electrical rewriting function, and more particularly, to an AND gate.
The present invention relates to a nonvolatile semiconductor memory device having a memory array structure, suitable for miniaturization, and in which a memory cell is not deteriorated by injection of a hole oxide film.

[0002]

2. Description of the Related Art Conventionally, as a non-volatile semiconductor memory device, for example, a memory device called an electric flash type NOR flash memory disclosed in Japanese Patent Application Laid-Open No. 3-219496 is known. In this conventional NOR flash memory, as shown in FIG. 36, memory cells M11 to M26 are arranged in a matrix, the drain terminals of the memory cells are connected to data lines BL, and the source lines are connected to a common source line SL. And the control gate is connected to the word line WL. Erasing and writing of data in the conventional NOR type flash memory configured as described above are performed as follows.

In a NOR flash memory, data in a memory cell is erased by applying a negative voltage to a control gate and a positive voltage to a source. At this time, a tunnel phenomenon between the source and the floating gate causes electrons accumulated in the floating gate to be drawn out to the source side, and the threshold voltage of the memory cell decreases. This state where the threshold voltage is low is the erased state. On the other hand, data writing to a memory cell is performed by applying a positive voltage to the control gate and the drain, generating hot electrons near the drain junction surface, and injecting electrons into the floating gate. This operation increases the threshold voltage of the memory cell. The state where the threshold voltage is high is the write state. The conventionally known NOR type flash memory has a function of collectively erasing memory cells in a whole or part of a coherent area of a chip, and has a circuit configuration in which a source wiring is common to all bits to reduce the area. Reduction has been achieved.

On the other hand, for example, Japanese Patent Laid-Open Publication No.
There is also known a nonvolatile semiconductor memory device called an AND-type flash memory as described in Japanese Patent Publication No. 37-37. In the AND-type flash memory, as shown in FIG. 37, the control gates of the memory cells M11 to M24 are connected to the word lines WL, and the drains are connected to the sub-data lines formed by the diffusion layers. M
Connected to data lines BL1 and BL2 formed by metal wiring via OS transistors TB1 and TB2,
It is configured to be connected to a sub-source line formed of a diffusion layer and then connected to a common source line SL via source selection MOS transistors TS1 and TS2, respectively. Writing and erasing data to and from memory cells in an AND flash memory are both performed using the Fowler-Nordheim tunnel phenomenon (hereinafter referred to as "FN tunnel phenomenon").

In erasing data from a memory cell in an AND flash memory, a positive voltage is applied to a control gate,
This is performed by setting the source and the drain to the same potential as the substrate. As a result, an FN tunnel phenomenon occurs through the gate oxide film, and electrons are injected into the floating gate from the entire channel region of the memory cell. This implantation increases the threshold voltage of the memory cells on the same word line. The state where the threshold value is high is the erase state. On the other hand, data writing to a memory cell is performed by applying a negative voltage to the control gate, applying a positive voltage to the drain, and setting the source to the same potential as the substrate. As a result, an FN tunnel phenomenon occurs through the gate oxide film, and electrons are emitted from the floating gate to the drain diffusion layer side through the overlap region (drain diffusion layer edge region) between the drain diffusion layer and the floating gate, and the memory The threshold voltage of the cell becomes low. The state where the threshold value is low is the write state. In this method, data is rewritten using a very small current called a tunnel current by the FN tunnel phenomenon, which is effective in reducing power consumption and advantageous in using a single power supply. The NOR flash memory and the AND flash memory are described in “Applied Physics” Vol. 65, No. 11
No. (1996), pp. 1114-124.

[0006]

In the former NOR type flash memory, although the memory cell structure is fine, current consumption at the time of writing is large and it is difficult to operate with a single power supply. That is, since the operation of injecting electrons into the floating gate is performed by the hot electron injection method, the injection efficiency is poor and a large current needs to be supplied. For example, with a single power supply of 3.3 V, the area of the booster circuit required to supply this large current increases, which has been an obstacle to reducing the chip area.

On the other hand, in the latter AND type flash memory, data is rewritten by using a very small current called a tunnel current, which is effective in reducing power consumption and lowering the voltage required for small portable equipment. Is possible. In addition, since writing and erasing are performed in sector units using memory cells on one word line as one sector, rewriting in small units is possible, and the writing unit and erasing unit that are essential for file use are the same. It has the advantage of being a size.

As described above, in the AND type flash memory, data lines and source lines are hierarchized, and are formed by metal wiring after being connected to sub data lines or sub source lines formed by diffusion layers. Connected to a global data line or a common source line. By reducing the number of contact holes to the global data line, the effective cell area can be reduced, and the cost can be reduced by miniaturization. Thus, it can be said that the AND type flash memory is a cell array having advantages such as a single power supply, sector rewriting, and reduction of contact holes.

However, in the write operation of the conventional AND type flash memory, a negative voltage is applied to the control gate to open the source line, and a positive voltage is applied to the drain diffusion layer. Tunneling occurs and electron-hole pairs are generated. Holes in the holes are accelerated by an electric field in the horizontal direction of the channel and injected into the gate oxide film. As the number of times of rewriting increases, the amount of injected holes also increases, which appears as deterioration of retention characteristics and disturb characteristics of memory cells. Also, in order to realize high-speed writing, it is necessary to secure a sufficient overlap region between the floating gate and the drain diffusion layer to secure a tunnel current. For this reason, a memory cell always needs to be about 0.1 μm as an overlap region between a gate and a diffusion layer, and there is a limit to miniaturization.

Accordingly, an object of the present invention is to provide an electrically rewritable nonvolatile semiconductor memory device having the above-mentioned AND type memory array structure, suitable for miniaturization, and having a memory cell deterioration caused by injection of a hole oxide film. An object of the present invention is to provide a nonvolatile semiconductor memory device having an operation method that does not occur. At the same time, a high-precision threshold voltage control method for improving data retention characteristics and disturb characteristics of memory cells and preventing over-erasing, a high-speed and highly reliable writing operation method, and a multi-value system for realizing a large capacity. An object of the present invention is to provide a semiconductor memory device including a memory cell.

[0011]

The present invention has the following means in order to achieve the above object. That is, the semiconductor memory device of the present invention performs writing and erasing of a memory cell by applying positive and negative voltages to a gate terminal,
An operation system realized by injecting and extracting electrons through the entire surface of the channel is provided. In particular, one or a plurality of memory cells connected between a data line and a source line are connected in parallel. A dummy memory cell having the same configuration as the MOS transistor or the memory cell is connected.
Since the source terminal is charged and discharged via the MOS transistor and the dummy memory cell, hot electrons are not injected into the non-selected memory cells on the same word line, and the threshold voltage does not change.

Further, in the semiconductor memory device of the present invention, the gate positive voltage at the time of writing is boosted in two stages.
According to this configuration, the current for charging the source line flows through the channel of the non-selected memory cell on the same word line, but the gate voltage is low, so that the threshold voltage does not change due to hot electron injection. Further, in the semiconductor memory device of the present invention, when erasing a memory cell, a first erase is performed by applying a negative voltage to the gate until the threshold voltages of all target memory cells become equal to or lower than the first voltage. And a second erasing operation in which a positive voltage is applied to the gate of the memory cell whose threshold voltage is equal to or lower than the second voltage to perform a write-back operation. Thus, the variation in the threshold value after erasing can be suppressed to the same level as the variation in the threshold value after writing.

Further, in the semiconductor memory device of the present invention, when writing data to a memory cell in the semiconductor memory device, the write operation is divided into a plurality of operations, and the data line voltage of the selected memory cell is reduced as the number of times increases. It has an operation method. As a result, an excessive electric field is not applied to a memory cell having a high writing speed, and writing is performed with a higher electric field to a memory cell which is difficult to write, so that high-speed and highly reliable writing can be performed. Become. Further, the semiconductor memory device of the present invention has a configuration in which one sense latch is shared by two or more data lines, and a configuration in which one data line is shared by two sub-data lines, thereby miniaturizing a memory cell. Layout becomes possible even for Further, the semiconductor memory device of the present invention has means capable of writing two or more bits of information in one memory cell and reading the information. This enables a large-capacity semiconductor memory device.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) First, a first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 1 is a circuit configuration diagram in the first embodiment. In the circuit configuration diagram shown in FIG. 3, four memory cells are arranged in an array using two word lines W1 and W2 and data lines D1 and D2, respectively. The number of data lines and the number of data lines are not limited to the present embodiment, and it goes without saying that any number and any number of data lines can be taken.

As shown in FIG. 1, in this embodiment, memory cells M11 to M1 connected between a data line and a source line are provided.
2, MOS transistors TR1 and TR2 are connected in parallel to M21 to M22. In the figure, WD
Is a word decoder, D1 and D2 are data lines, W1 and W2 are word lines, EL is a well wiring, CS is a common source line, SD is a gate signal line for controlling a drain-side switch MOS transistor, and SS is a source-side switch MO.
A gate signal line for controlling an S transistor, SV is a gate signal line for controlling a source-drain equipotential MOS transistor, and DC is a gate signal line for controlling a data line discharge MOS transistor. The invention of the non-volatile semiconductor circuit itself in which each data line is connected to the source line via a MOS transistor connected in parallel to the memory cell is disclosed by the present applicant in Japanese Patent Application No. Hei.
No. 140,329 (see Japanese Patent Application Laid-Open No. 6-349289).

Next, a write operation to a memory cell in the circuit configuration of FIG. 1 will be described. FIG. 2 shows one memory cell in FIG. 1, for example, a memory cell M11 on a word line W1.
FIG. 9 is a timing chart showing an example of timing when writing is performed to the memory. As shown in FIG.
When writing data to the memory cell, the voltage of the data line D1 is set to the ground voltage, and the word line W1 is set to a positive high voltage VWW, for example, 15V. The gate signal line SS is set to 0 V, and the source lines S1 and S2 are opened. In this case, since the positive high voltage VWW is applied to the control gate also to the unselected memory cell M21 existing on the same word line W1, it is necessary to prevent writing by applying a write blocking voltage to the source and drain of M21. For this purpose, for example, 5 V is applied to the data line D2 as a write blocking voltage.

After a write blocking voltage (for example, 5 V) is applied to the data line D2 of the non-selected memory cell M21 (a), a voltage (for example, 7 V) is applied to the gate signal line SD (b).
Thereafter, a voltage (for example, 7 V) is applied to the gate signal line SV to turn on the MOS transistors TR1 and TR2, whereby the voltage of the data line D2 (for example, 5
V) via the MOS transistor TR2 to the source line S
2 is charged (c). By this operation, the data line D
2 and the potential of the source line S2 become equal. After the potentials of the data line D2 and the source line S2 become equal, the word line W1
Is boosted to VWW, and electrons are injected into the floating gate of the selected memory cell M11 (d). At this time, since the write inhibit voltage (for example, 5 V) is applied to both the data line D2 and the source line S2 of the unselected memory cell, writing to the unselected memory cell M21 is not performed.

When stopping the injection of electrons, the word line W1
(E), the gate signal line SD is lowered to turn off the drain selection MOS transistor, a voltage is applied to the gate signal line SS and the gate signal line DC, and the source selection MOS transistor and the discharge MOS transistor are turned on. The state is turned on, and the electric charges accumulated in the source line and the data line are extracted (f). At this time, the MOS transistors TR1 and TR2 are kept ON to prevent a transient current from flowing through the memory cell. As described above, the charge and discharge of the source terminal are performed by the source selection MOS
This is performed via the transistor and the discharge MOS transistor. At that time, since the MOS transistors TR1 and TR2 provided in parallel with the memory cell also keep the ON state, hot electron injection does not occur in the unselected memory cell. , The threshold voltage does not change.

FIGS. 3A and 3B are diagrams for explaining the operation when the threshold voltage after writing and the threshold voltage after erasing are both positive voltages. FIG. 3A shows an example of voltage conditions in that case. (B) shows the threshold distribution after writing and after erasing, respectively. FIGS. 4A and 4B are diagrams for explaining the operation when the threshold voltage after writing is a positive voltage and the threshold voltage after erasing is a negative voltage, and FIG. In the example, (b) shows a threshold distribution state after writing and after erasing, respectively. Note that FIG.
In the memory cell threshold voltage distribution examples of FIG. 4B and FIG. 4B, the vertical axis indicates the threshold voltage, and the horizontal axis indicates the number of memory cells having the threshold value.

(Second Embodiment) A second embodiment of the present invention is directed to a nonvolatile memory cell forming a memory array instead of the ordinary MOS transistors TR1 and TR2 in the first embodiment. In this case, a MOS transistor having the same configuration as that described above is used. FIG. 5 shows a configuration example of the second embodiment of the present invention. In the figure, a MOS transistor MT having the same structure as the memory cells M11 to M22 as a source / drain same potential MOS transistor
R1 and MTR2 are used. In the case of the present embodiment, a normal memory cell connected to one word line or a plurality of word lines in the memory array can be used as a source-drain equipotential MOS transistor for setting the data line and the source line to the same potential. The manufacturing process is simplified as compared with the case where they are manufactured separately, and the occupied area can be reduced as compared with the configuration in which MOS transistors TR1 and TR2 shown in FIG. 1 are provided separately from the memory cells for the memory array. .

(Third Embodiment) A third embodiment of the present invention will be described with reference to the configuration diagram of FIG. 6 and the timing chart of FIG. In the present embodiment, as shown in FIG. 6, a MOS transistor (parallel to a memory cell) connected in parallel with a memory cell to make the source and the drain have the same potential as in the first embodiment and the second embodiment. This eliminates the need for TR1 and TR2 in FIG. 1, MTR1 and MTR2 in FIG. 5, and a gate signal line (SV) for controlling the gate of the MOS transistor.

This embodiment is characterized in that there is provided operating means for increasing the gate voltage in two stages when electrons are injected into the memory cell floating gate. Hereinafter, in this embodiment, for example, an operation when writing to the memory cell M11 on the word line W1 will be described in detail. FIG. 7 is a timing chart at that time. When writing data to the memory cell M11, the voltage of the data line D1 is set to the ground voltage, and the word line W1 is set to a positive high voltage, for example, 15V.
And The gate signal line SS is set to 0 V, and the source lines S1 and S2 are opened. Here, 15V is also applied to the control gate of the unselected memory cell M21 existing on the same word line.
Is applied, it is necessary to apply a write blocking voltage to the source and drain of M21. Writing data to a memory cell is performed by applying a positive voltage to the control gate and injecting electrons into the floating gate.

The operation will be described below step by step. The word line W1 of the selected memory cell M11 is boosted to VEW1, and the gate voltage SD of the drain selection MOS transistor is increased to 7V.
After the voltage is boosted to about (a), a write blocking voltage, for example, 5 V is applied to the data line D2 of the non-selected memory cell M21 (b). At this time, VWW1 is a voltage sufficient to turn on all the memory cells on the word line W1, and a voltage sufficient to charge the source line with the write inhibit voltage, for example, 7
V. Also, the gate voltage SD of the drain selection MOS transistor is set to a voltage sufficient to apply the write blocking voltage to the drain of the memory cell.

When a write inhibit voltage (for example, 5 V) is applied to the data line D2 of the non-selected memory cell, all the memory cells connected on the word line W1 are in the ON state, so that the data line D2 is connected via the memory cell M21. From the source line S2
To charge. At this time, the ground voltage is applied to the data line D1 of the selected memory cell, and the ground potential is also applied to the source line S1 via the drain selection MOS transistor and the memory cell (c).

After the charging of the source line is completed, the voltage of the word line W1 is set to VWW. While VWW is applied to the word line, electrons are injected into the floating gate of the selected memory cell, and data is written (d). When the injection of electrons is stopped, the word line W1 is set to the ground voltage (e), and then the gate signal line SD is lowered to set the drain selection MOS.
The transistor is turned off, and, for example, 7 V is applied to the gate signal line SS of the source selection MOS transistor and the gate signal line DC of the discharge MOS transistor, and the electric charges stored in the source line and the data line, respectively, are extracted (f). Thereafter, the gate signal line SD is lowered (g).

According to the above-described operation method, a current for charging the source line flows through the channel of the non-selected memory cell M21. However, since the gate voltage is low, a change in the threshold voltage due to hot electron injection is suppressed. You. When writing is performed in a plurality of times, it is necessary to charge the source line for each writing pulse, and the charging time slightly slows down the writing. However, it is a serious problem that the threshold voltage of the unselected memory cell changes due to the disturb, and according to the present embodiment, the disturb can be avoided with a slight increase in the writing time, and the practical effect is reduced. large.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 8, the circuit in the fourth embodiment includes nonvolatile semiconductor memory cells M11 to Mnm, word lines W1 to Wm, and data lines D1 to Dm.
Dn, word decoder WD, drain selection MOS transistor gate signal line SD, source selection MOS transistor gate signal line SS, precharge signal PC, data line and transformer MOS transistor gate signal line WS of the sense section, sense latches SL1 to SLn, erase It comprises an end detection signal line CC1, a write end signal line CC2, a data line discharge MOS transistor gate signal line DC, and a common source line CS.

FIG. 9 shows an example of a memory cell threshold voltage distribution in the fourth embodiment. Conventionally, the variation in the threshold voltage distribution in the erased state is larger than the variation in the threshold voltage distribution in the written state. It is for the following reasons.
When writing, a write voltage is applied only to the memory cell to be written, and threshold verification is performed for each bit,
Since no further write voltage is applied to the memory cell for which the write operation has been completed, the variation in threshold voltage is small. On the other hand, erasing is performed in units of word lines, and an erasing voltage is applied until all memory cells to be erased have a predetermined threshold voltage or less. Therefore, the variation in the threshold voltage of the memory cell before erasing and the variation in the erasing characteristics of the memory cell are reflected in the variation in the threshold voltage after erasing.

In order to prevent this, if the memory cells existing on the same word line are to be erased collectively, the erase time varies due to the variation of the tunnel current, and an excessive erase voltage is applied to the memory cell erased first. This causes another problem that the threshold voltage becomes negative. On the other hand, the memory cell threshold voltage distribution in the fourth embodiment is characterized in that the threshold voltage distribution in the erased state is suppressed to about the same variation as the threshold voltage distribution in the written state. have. In this embodiment, means for performing the first erasing operation and the second erasing operation is provided as shown in FIG.

First, a negative voltage is applied to a word line, and an erase voltage is applied until the threshold voltages of all the memory cells connected to the word line become equal to or lower than the first voltage VEV1. This is referred to as a first erase operation. FIG. 10A shows the threshold voltage distribution after the completion of the first erase operation. Subsequent to the first erase operation, a read operation for the second erase operation is performed. In this read operation, the threshold voltage becomes the second
Is selected (the hatched portion in FIG. 10B: the memory cell in the area 1), and the memory cell in the area 1 is written back. In the second erase operation, a positive voltage is applied to the control gate, a ground voltage is applied to the data line of the memory cell existing in the area 1, and
(A region where the threshold voltage is equal to or higher than VEV2 and equal to or lower than VEV1)
Is applied to the data line of the memory cell existing in the memory cell. This is a second erasing operation. FIG. 10C shows the threshold voltage distribution after the completion of the second erase operation. This indicates that the variation of the threshold voltage distribution after the end of the erase operation can be reduced according to the fourth embodiment.

FIGS. 11 and 12 show specific examples of timing charts of the first erasing operation and the second erasing operation, respectively. First, the first erasure will be described with reference to FIG. Here, for example, an operation of erasing a memory cell on the word line W1 will be described. When the erase mode is selected, the word line W is set by the word decoder WD.
1 is selected and the negative voltage VEW is output. At this time, the source and the drain are at the ground potential (a).

Each time an erase pulse is applied, a threshold voltage verifying operation is performed, and a threshold voltage of V
When at least one memory cell equal to or greater than EV1 exists, the nodes DS1 to DSn corresponding to the memory cell become high as a result of amplification by the sense latches SL1 to SLn, and the corresponding MOS transistors MS1 to MSn are turned on.
In this state, the voltage of the write end signal line CC2 drops. Therefore, the end determination is NG, and the erase pulse is continuously applied (b). When the threshold voltages of all the memory cells on the word line W1 become equal to or lower than VEV1, all the memory cells on the word line W1 are turned on by the verification operation and the nodes DS1 to DSn are all at a low level. Since all of MS1 to MSn are in the OFF state and the write end signal line CC2 is not discharged, the end determination is OK.
(C).

Next, the second erase operation will be described with reference to FIG. After the end of the first erase operation, first, a read operation for the second erase operation is performed. In this read operation, RSAL and RSAR are activated and the node DS1 is activated.
To DSn and DB1 to DBn are lowered (d).
Thereafter, the drain selection MOS transistor is turned on, the precharge signal PC is activated, the MOS transistors MP1 to MPn are turned on, and the data line D1 is turned on.
To Dn (e). As a result, the data lines D1 to Dn are charged to a desired level. At the same time or after this, the second voltage VEV2 is applied to the word line W1.
Is output (f).

At this time, since the memory cell whose threshold voltage is equal to or lower than VEV2, for example, M21, is in the ON state,
Data line D2 is discharged. Since the memory cell whose threshold voltage is equal to or higher than VEV2, for example, M11 is in the OFF state, the data line D1 remains charged. here,
When WS is activated to connect the sense latch to the data line and activate the sense latches SL1 to SLn, the DB potential of the undischarged data line becomes the ground voltage, and the node DS potential rises. In this figure, for example, node DS
1 remains at the high level. DB1 becomes the ground voltage,
The potential of DS1 rises, and the sense latches SL1 to SLn
Power supply voltage. At this time, the potential of the node DB and the potential of the DS of the discharged data line are amplified to opposite levels (g).

At this point, the potential of the DB connected to the memory cell whose threshold voltage is equal to or lower than VEV2 is at a high level, and the potential of the DB connected to the memory cell whose threshold voltage is equal to or higher than VEV2. Is the ground voltage (h). Therefore, the threshold voltage of the memory cell on word line W1 is V
If there is one below EV2, the erase end detection signal CC
1 is the ground voltage, and the end determination is NG. When the end judgment is NG, the power supply voltage of the sense latch is raised,
The signals at the nodes DS1 to DSn are amplified to a desired high level. As a result, in the example of FIG.
And DSn attain a high level, and the node DS2 remains at the ground voltage (i). The memory cells corresponding to DS1 and DSn that have become high level have a threshold voltage of VEV2.
As described above, the threshold voltage of the memory cell corresponding to the ground voltage DS2 is equal to or lower than VEV2.

By amplifying sense latches SL1 to SLn, a ground potential is applied to the data line of a memory cell having a threshold voltage lower than VEV2, and
A high level voltage is applied to the data line of the memory cell higher than EV2 (j). This is the write blocking voltage.
In the present embodiment, the write voltage VWW is applied to the word line W1 after the data line and the source line have the same potential by the method of boosting the word line in two stages (k). Here, as a method for setting the data line and the source line to the same potential, a MOS transistor or a dummy memory cell connected in parallel with the memory cell as described in the first embodiment may be used.

As a result, a positive voltage is applied to the gate and a ground voltage is applied to the source and drain of the memory cell whose threshold voltage is equal to or lower than VEV2, so that electrons are injected into the floating gate. In addition, since a write-blocking voltage is applied to the source and the drain of a memory cell having a threshold voltage of VEV2 or more, electrons are not injected into the floating gate. In this manner, the threshold voltage can be increased (write-back) only for the memory cells of VEV2 or less. After one write pulse is applied, DC is activated to discharge the data line, and the read operation is performed again (l). The threshold voltage of all memory cells on word line W1 is VE
When the voltage exceeds V2, all of DB1 to DBn become the ground voltage, the erase end detection signal CC1 becomes high level, and it is determined that the write-back is completed (m).

(Fifth Embodiment) FIG. 13 shows a fifth embodiment of the present invention. This embodiment is an embodiment in the case where the second voltage VEV2 is higher than the first voltage VEV1 in the above-described fourth embodiment. FIG. 13A shows a state in which the first erase operation has been completed, and FIG. 13B shows a state in which the second erase operation has been completed. In this embodiment, all the memory cells to be erased are subjected to the second erase operation.

(Sixth Embodiment) A sixth embodiment of the present invention will be described with reference to the circuit configuration of FIG. 14 and an example of operating voltages of FIG. The write / erase characteristics of the memory cells vary, and some of the memory cells have a very high write speed. On the other hand, conventionally, a method has been adopted in which writing is divided into a plurality of times and the pulse width at the beginning of writing is shortened. However, when the characteristic variation of the memory cell is large, the threshold voltage of the memory cell may not be controlled with the pulse width that can be output.

There is a method in which the pulse voltage is made variable in contrast to a method in which the pulse width is made variable. As a method of making such a pulse voltage variable, for example, Japanese Patent Application Laid-Open No. H08-1155
As described in JP-A-99-99, there is a variable word line writing method in which a pulse having a high voltage and a long pulse width is sequentially applied to a word line as writing proceeds. In this method, it is necessary to change a high voltage pulse applied to a word line, and a circuit for realizing this is complicated. Therefore, the present embodiment proposes a variable bit line system in which a pulse applied to a selected bit line is set to a low voltage as writing proceeds. According to this method, the voltage of the bit line may be made variable within the range of the power supply voltage, so that a voltage variable circuit can be easily realized. In the example of FIG. 14, four memory cells M11 to M22 are arranged in an array using two word lines W1 and W2 and data lines D1 and D2, respectively. It goes without saying that the number of data lines is not limited to this.

First, upon entering the write mode, data is transferred to K1.
And K2. The output voltage of the latch when writing to the memory cell is VWD1, and the output voltage when not writing to the memory cell is VND. At this time, VWD1
Is smaller than VND. The signal SD is set to a high voltage V2, for example, 7 V so that the voltage of the bit line is applied to the drain of the memory cell, and the source line is set to the same potential as the bit line by the method described in the first and second embodiments. And As a result, a voltage difference between VWW and VWD1 is applied between the control gate of the memory cell to be written and the substrate, and a somewhat smaller voltage is applied between the floating gate and the substrate. Will be injected. At this time, the electric field applied to the memory cell is small enough to sufficiently control the threshold voltage of the memory cell to which writing is performed earliest. VW is applied to the memory cells that are not written.
Since a voltage difference between VWW and VND that is smaller than the voltage difference between W and VWD1 is added, no charge injection occurs.

After this state is maintained for a certain period of time, verification is performed. At this time, the word line is set to VWV, the bit line voltage is set to V1, the signal SD is set to the high voltage V2, the gate signal line SS is set to V3, and the memory cell currents are set to K1 and K2.
To determine whether the writing has been completed. If, for example, the threshold voltage of the memory cell M11 is sufficiently high, the writing is terminated, and VND is latched in K1 thereafter. Therefore, thereafter, the write inhibit voltage VND is applied to the data line of this memory cell.

In the next write cycle, the selected data line is set to V
WD2. This VWD2 is a lower voltage than VWD1. In this state, VWW is applied to the word line of the memory cell to which data is written, and VND is applied to the data line of the memory cell to which writing has been completed such as the memory cell to which data is not written and the memory cell M11. As a result, a voltage difference between VWW and VWD2, which is larger than VWW and VWD1, is applied between the control gate of the memory cell to be written and the substrate. Writing can be performed in a short time.

In the following verification operation, the same voltage relationship as in the previous verification operation is used, and it is determined whether or not each memory cell has been written. For example, if the memory cell M21 is written, the write block voltage VND is latched in K2 thereafter, and no further writing is performed. In the next write cycle, VWD3 is applied to the data line of the memory cell to be written.
Is applied. Here, VWD3 is smaller than VWD2. In this state, VWW is applied to the word line of the memory cell to be written, and VND is applied to the data line of the memory cell where writing is not performed and the memory cell where writing is completed such as M11 and M21. As a result, between the control gate of the memory cell to be written and the substrate, VWW and VWW larger than VWD2 are set.
And VWD3. This allows V
A memory cell that is difficult to write even with a voltage difference between WW and VWD2 can be written at a higher speed with a voltage difference between VWW and VWD3.

As described above, when writing is performed in a plurality of times, the operation method of lowering the data line voltage of the selected memory cell with an increase in the number of times causes an excessive amount of memory cells with a high writing speed. Since the application of an electric field can be suppressed, and writing is performed with a higher electric field on a memory cell that is difficult to write, writing can be performed at high speed and with high reliability.

Next, an embodiment of the present invention relating to a circuit configuration suitable for miniaturization of a memory cell will be described. In general, with the miniaturization of memory cells, the layout of sense amplifiers connected to data lines to read out memory cell currents and latches for storing information to be written in memory cells becomes difficult. Two embodiments will be described below as embodiments for coping with the narrowing of the bit line pitch. -An embodiment of a circuit configuration in which one sense latch is shared by two or more data lines-An embodiment of a circuit configuration in which one data line and one sense latch are shared by two or more sub-data lines

(Seventh Embodiment) A seventh embodiment of the present invention is an embodiment of a circuit configuration in which one sense latch is shared by two or more data lines, and the circuit configuration is shown in FIG. . In FIG. 16, for example, n is set to 512B, and
The circuit configuration is such that the B sense latch and the 1024B memory cell share one sense latch with two data lines.
In this case, writing is performed twice in units of 512 B, and erasing is performed in units of 1024 B. Therefore, small-scale rewriting is possible, and the advantage that the writing unit and the erasing unit, which are essential for file use, have the same size is maintained. I have.

FIG. 16 shows memory cells M11 to Mnm, MO
S transistors Tr1 to Trn, word lines W1 to Wn,
Data lines D1 to Dn and a word decoder WD. Adjacent data lines include odd-numbered data lines via MOS transistors MO1 to MOn, and even-numbered data lines include MOS transistors ME1 to MEn. Through the common sense latches SL1 to SLn. MOS transistors MO1 to MOn are SD
1 and the MOS transistors ME1 to MEn are S
Controlled by D2.

Next, the circuit operation of FIG. 16 will be described in detail. To erase a memory cell, the erase voltage VE is applied to the word line W1.
This is performed by applying W and applying an erase pulse until the threshold voltages of all the memory cells on the word line W1 become equal to or lower than a predetermined value. At the time of the erasing operation, the threshold voltage after erasing may be narrowed by using the erasing method described in the fourth embodiment (see FIG. 10).

Next, a write operation of a memory cell will be described with reference to FIG. Before writing data, SV,
A high voltage, for example, 7 V is applied to SD2, and all the latches SL1
ＳＬSLn through all the even-numbered data lines D2 to D2n to charge the source lines S2 to S2n and the sub-data lines to a write blocking voltage, for example, 5 V (step 101). Thereafter, first, write data to the memory cell connected to the odd-numbered data line is latched. Next, SD2 is set to 0V and SD
1 is applied with a high voltage, and a voltage corresponding to information to be written to an odd-numbered data line is applied. By applying the write voltage VWW to the word line W1 in this state, data is written to the memory cells on the odd-numbered data lines (step 10).
2). At this time, writing is not performed because the write inhibit voltage is charged to the drain and source of the memory cell connected to the even-numbered data line. After the writing of the odd number is completed (Step 103: Y), the writing of the even number is performed.

In writing an even number, first, the SV and SD
1 to all odd data lines D1 to D2n-
1 to the source lines S1 to S2n-1 and the corresponding drain lines are charged to a write blocking voltage, for example, 5 V (step 104). Thereafter, the write data to the memory cell connected to the even-numbered data line is latched. With SD1 set to 0 V, a high voltage is applied to SD2, and a voltage corresponding to the information to be written is applied to the even-numbered data lines. In this state, the word line W
When 1 is set to VWW, writing is performed on even-numbered memory cells (step 105). When the writing of the even-numbered memory cells is completed, the writing process is completed (step 10).
6). For example, when writing the odd-numbered memory cells, the writing of the write-inhibiting voltage to the source and drain of the even-numbered memory cells is performed every time a write pulse is applied.

(Eighth Embodiment) An eighth embodiment of the present invention will be described with reference to FIG. In the seventh embodiment, the MO
S transistor MOi (i = 1 to n), MEi (i = 1)
To n) and one sense latch SLi (i = 1 to n), a circuit configuration is shown in which one sense latch is shared by two data lines. In the seventh embodiment, the drain selection M
MDOi (i = 1 to n), MD as OS transistor
Ei (i = 1 to n) are provided in two stages, odd-numbered sub-data lines are via MDOi, and even-numbered sub-data lines are M
It is connected to a common metal data line via DEi.

Next, the operation of the eighth embodiment will be described with reference to FIG. Before writing data, SV, ST
2 is applied with a high voltage, for example, 7V, and all the latches SL1 to SL
From Ln, all even-numbered sub-data lines and corresponding source lines are charged to a write blocking voltage, for example, 5 V (step 101). Thereafter, first, the write data to the memory cell connected to the odd-numbered sub-data line is latched. S
T2 is set to 0 V, a high voltage is applied to ST1, and a voltage corresponding to information to be written to the odd-numbered sub-data line is applied. By applying the write voltage VWW to the word line W1 in this state, writing is performed on the memory cells on the odd-numbered sub-data lines (step 102). At this time, writing is not performed because the write inhibit voltage is charged to the drain and source of the memory cell connected to the even-numbered sub data line.

After the writing of the memory cells connected to the odd-numbered sub-data lines is completed (step 103), the writing of the even-numbered sub-data lines is performed. A high voltage is applied to SV and ST1 to charge odd-numbered sub-data lines and corresponding source lines to a write-inhibiting voltage, for example, 5 V (step 1).
04). Thereafter, the write data to the memory cell connected to the even-numbered data line is latched. ST1 is set to 0V and S
A high voltage is applied to T2, and a voltage corresponding to the information to be written is applied to the even-numbered sub-data lines. When the word line W1 is set to VWW in this state, writing is performed on the memory cell connected to the even-numbered sub-data line (step 105).
When the writing of the even-numbered memory cells is completed, the writing process ends (step 106).

(Ninth Embodiment) Next, a ninth embodiment which is a modification of the eighth embodiment will be described with reference to FIG. In this embodiment, of the sub-source lines, odd-numbered sub-source lines are connected via the source-side selection MOS transistors MSO1 to MSOn, and even-numbered sub-source lines are connected to the source-side selection MOS transistors MSO1 to MSOn.
It is connected to the common source line CS via the OS transistors MSE1 to MSEn. First, when writing is performed to the memory cell connected to the odd-numbered data line, SS
2, a high voltage, for example, 7V, is applied to the SV and the common source line CS
, And a write inhibition voltage is applied to even-numbered sub-source lines and corresponding sub-data lines. At the same time, the data to be written to the odd-numbered sub-data line is taken into the sense latch, and a high voltage of 7 V is applied to ST1.
And applies a voltage corresponding to the write data to the odd-numbered sub-data lines. By applying the write voltage VWW to the word lines in this state, writing is performed on the memory cells on the odd-numbered sub-data lines. At this time, no write is performed because the write inhibit voltage is applied to the drain and source of the memory cell connected to the even-numbered sub data line.

After the writing to the memory cells connected to the odd-numbered sub-data lines is completed, writing is performed to the memory cells connected to the even-numbered sub-data lines. This writing,
A high voltage, for example, 7V is applied to SS1 and SV, a write inhibit voltage, for example, 5V, is applied to the common source line CS, and a write inhibit voltage is applied to the odd-numbered sub-source lines and the corresponding sub-data lines. At the same time, data to be written to the even-numbered sub-data line is taken into the sense latch, a high voltage of 7 V is applied to ST2, and a voltage corresponding to the write data is applied to the even-numbered sub-data line. In this state, the write voltage VW is applied to the word line.
By applying W, writing is performed on the memory cells on the even-numbered sub-data lines. At this time, no write is performed because the write inhibit voltage is applied to the drain and source of the memory cell connected to the odd-numbered sub data line. When the writing of the memory cell connected to the even-numbered sub data line is completed, the writing process ends.
According to this configuration, during the writing of the even-numbered data, the write-inhibiting voltage is applied from the common source line to the odd-numbered sub-data line and the sub-source line, and the write-inhibiting voltage is charged. In this case, the writing can be more reliably prevented.

(Tenth Embodiment) In the seventh and eighth embodiments described above, for example, when an odd-numbered memory cell has already been written, its data is once saved, and then the odd-numbered memory cell is rewritten. There is a need to erase even numbered memory cells simultaneously. After the erasure is completed, the saved odd-numbered data is written again, and thereafter, writing to the even-numbered memory cells is performed. Therefore, as a tenth embodiment, as shown in FIG. 20, the sense latches SL1 to SLn
And SK1 in each of the sense latches SL1 to SLn.
And data latches DL1 to DL1 connected by SK2.
A circuit configuration connecting DLn is proposed.

First, if the odd-numbered memory cells have already been written, the odd-numbered memory cells are read. After the reading is completed and the sense latch is determined, the switch SK1 is turned on to connect the data latch and the sense latch. After the data latch is determined, S
K1 is turned off to disconnect the data latch from the sense latch. By the above operation, the data written to the odd number is stored in the data latch. After that, erasing is performed.

After erasing, the odd-numbered memory cell data stored in the data latch is written. First,
SK2 is turned on, the data latch and the sense latch are connected, and write data is transmitted to the sense latch. With SK2 turned off, the sense latch and the data latch are separated, and the same write operation as in the sixth and seventh embodiments is performed based on the data taken into the sense latch. After the above rewriting is completed, write data for which a new write request has been issued is taken into the sense latch, and writing to the memory cell is performed in the same manner. FIG. 20 shows a configuration in which the data latch is connected to the sense latch of FIG. 17 shown in the eighth embodiment, but the data latch is connected in the same manner as the sense latch of FIG. 16 shown in the seventh embodiment. It is also possible to connect.

Next, when viewed from the outside, a method in which writing and erasing are apparently the same unit is shown in the circuit configuration diagram of FIG.
This will be described with reference to the flowchart of FIG. In FIG. 20, n is set to, for example, 512B, and SK1 and SK2 are set to the 512B sense latches SL1 to SLn and the sense latches.
And data latches connected by switches. When a write request for one sector (= 1024B) comes from outside (step 201), first, all the memory cells of the sector for which the write request was made are erased (step 20).
2). Thereafter, first, for example, write data to an odd-numbered memory cell is stored in a data latch (step 20).
3) The data written to the even-numbered memory cell is stored in the sense latch (step 204).

Next, data is written to the even-numbered memory cells using the data stored in the sense latch (step 205). When the writing to the even-numbered memory cells is completed (Step 206: Y), writing to the odd-numbered memory cells is performed (Step 207). When the writing to the odd-numbered memory cells is completed (step 208: Y),
The writing process ends. In this operation method, since the write unit 1024B is divided into the sense latches SL1 to SLn and the data latches DL1 to DLn and fetched at once, and the write process is performed sequentially, when viewed from the outside, the write and erase are apparently the same. Can be treated as a unit.

(Eleventh Embodiment) FIG. 22 shows a first embodiment of the present invention.
FIG. 1 is an embodiment of the present invention, and is an overall configuration diagram of a flash memory capable of writing 2-bit information in one memory cell and reading the information. In the present embodiment, three different values are set as write verify voltages to be applied to the word lines at the time of the write operation, these are switched, and the write operation is performed three times, and write is performed in these write operations. Binary (1 bit) write data "0" or "1" to be held by the sense latch circuit
A buffer for temporarily holding (“LOW” or “High”) is provided in the chip, and is combined with three types of write information by a write data conversion circuit and then taken into a sense latch. Also, in order to read four-level (two-bit) data written in one memory cell into two-level (one-bit) data, three types of voltages are applied to the word lines during a read operation, and three times are provided. Buffer temporarily stores binary (1 bit) data read from the memory cell in the read operation of
It is characterized in that means for converting a value (2 bits) into binary (1 bit) data is provided.

Next, an outline of the write operation and the read operation of this embodiment will be described with reference to the overall configuration diagram of FIG. In the write operation, a binary (1 bit) data string to be written to the memory array 3 is input from Din 16 and amplified by the main amplifier 10 to the write data conversion circuit 1 via the bus 2.
Send through 2. The binary (1 bit) data string to be written by the write data conversion circuit 1 is separated into odd bits and even bits, and the write binary data is transferred to the buffer 21 through the bus 23 and held. "Write 1"-
In order to synthesize binary (1 bit) data corresponding to “write 3”, the data separated into the odd and even bits is transferred from the buffer 21 to the write data conversion circuit 1 through the bus 23. This write data conversion circuit 1
Is transferred to the sense latch 4 via the bus 23, the buffer 21, and the bus 24 and latched in each of the operations of "write 1" to "write 3", and write and write verify operations are performed.

On the other hand, in the read operation, the binary data (1 bit) read from the memory array 3 is transferred from the sense latch 4 to the buffer 21 through the bus 24 and held by "read 1" to "read 3". Let it. These binary data are transferred to the read data conversion circuit 2 via the bus 25, and the upper and lower bits of the quaternary (2 bits) data are synthesized. These are alternately output, sent to the main amplifier 10 through the bus 26 as a binary (1 bit) data string, amplified, and output from the Dout 17.

Hereinafter, the above-described write operation and read operation will be described in more detail. (1) Write Operation Individual operations in the write operation used in the present invention will be described with reference to FIGS. FIG. 23 shows the relationship between the voltage applied to a word line at the time of write verification and the threshold voltage distribution of a memory cell in which quaternary (2-bit) data is written in this embodiment. In this case, the threshold value of the memory cell and the four values (2
Bit) is associated with the lowest threshold V
th0 is a state where information "00" is written, Vth1 having the second lowest threshold is a state where information "01" is written, and Vth2 having a third lowest threshold is information "10" is written. Vth3, which has the highest threshold value, is a state in which information "11" is written.

In order to store quaternary (2-bit) information in one memory cell, the threshold voltage distribution of the memory cell is shown in FIG.
What is necessary is just to make it quadrupolar like 3. In order to control the distribution of the threshold value of the memory cell by the write operation and the subsequent write verify operation, the write verify voltage is set to four memory cell thresholds V as shown in FIG.
Vt for th0, Vth1, Vth2, and Vth3
h0 <Vv1 <Vth1 <Vv2 <Vth2 <Vv3 <
Three types of voltages Vv1, Vv2, Vv3 satisfying Vth3
Is applied to the word line during the write verify operation.

FIG. 24 shows an example of the word line applied voltage. Each operation of “write 1”, “write 2”, and “write 3” in FIG. 24 is composed of a combination of one write and one verify operation. The threshold value of the memory cell in which the four-level data “01”, “10”, “11” is to be written is made higher than Vv1 by the operation of “write 1”, and the four-level data “10” is written by the operation of “write 2”. ”,
The threshold value of the memory cell to which “11” is to be written is set to Vv2
The threshold value of the memory cell where the quaternary data “11” is to be written is set to Vv3 by the operation of “write 3”.
Higher.

Next, a method of controlling the threshold voltage of a memory cell in writing four values (two bits) to the memory cell will be described. Now, as shown in FIG. 25, four memory cells MC1 to MC4 connected to one word line WL
It is assumed that four-valued (2-bit) data of "00", "01", "10", and "11" are written in each of them. These four
The value data “00” “01” “10” “11” is obtained by dividing a binary (1 bit) data string “00011011” by two. Normally, eight memory cells are required to write these eight data. However, as described above, eight 1-bit data are divided into two pieces each of four values (2 bits).
Bit) data "00", "01", "10", and "11", if each quaternary data is written into one memory cell, four data are required to store eight data. Only memory cells are required, and the capacity of the memory can be doubled.

First, an erasing operation is performed before writing, and the threshold voltages of memory cells MC1 to MC4 are adjusted to a low Vth0 (FIG. 26). The erasing operation is the same as in the above-described binary case. At this time, the fourth embodiment (see FIG. 10)
By performing the erasing operation in two stages according to the operation method described in (1), the threshold voltage distribution after erasing can be narrowed. In the operation of "write 1" (FIG. 27), first, the memory cell M
Sense latch circuit SL connected to each of C1 to MC4
The write binary data W1T (0111) is latched in 1 to SL4. Sense latch S connected to memory cell MC1
L1 is set to a high level (“0” is latched), and the sense latch circuits SL2 to SL4 connected to the other memory cells MC2 to MC4 are set to “Low” (latch “1”), and the memory cells MC2 to MC4 Write to. Thereafter, the write and write verify operations are performed with the word line voltage set to VWW, for example, 15 V at the time of write, and set to Vv1 at the time of write verify. Memory cells MC2
When the threshold value of MC4 becomes Vth1, "write 1"
Ends, and then the operation proceeds to the “write 2” operation.

In the operation of "write 2" (FIG. 28), first, a sense latch circuit S connecting write binary data W2T (0011) to memory cells MC1-MC4, respectively.
L1 to SL4 are latched. Sense latches SL1 and SL2 connected to memory cells MC1 and MC2 are set to high level (“0” is latched), and sense latch circuit SL connected to other memory cells MC3 and MC4
3 and SL4 are set to "Low" (latch "1"), and write is performed to the memory cells MC3 and MC4. Thereafter, the voltage of the word line is set to VWW, for example, 15 V at the time of writing, and V is set at the time of write verification, as in the case of “writing 1”.
When the threshold value of the memory cells MC3 and MC4 becomes Vth2 as v2, "write 2" ends, and the operation shifts to "write 3".

In the operation of "write 3" (FIG. 29), first, sense latch circuit S connecting write binary data W3T (0001) to memory cells MC1 to MC4, respectively.
L1 to SL4 are latched. Memory cells MC1, MC
, And sense latches SL1, SL connected to MC3
2 and SL3 to high level (latching "0"), and the sense latch circuit S connected to the memory cell MC4.
L4 is set to “Low” (latch “1”), and writing is performed on the memory cell MC4. Thereafter, as in the case of “write 1” and “write 2”, when writing the voltage of the word line,
For example, the voltage is set to 15 V, and the voltage is set to Vv3 at the time of write verification. When the threshold value of the memory cell MC4 becomes Vth3, "write 3" is completed, and the entire write operation is completed, and each of the memory cells MC1 to MC4 has four values ( This means that two bits of information "00", "01", "10", and "11" have been written.

As described above, the voltage applied to the word line at the time of the above-described write verification is set to Vv1 to Vv3, and the three write operations of “write 1” to “write 3” are performed, whereby one memory cell is obtained. Four-valued (two-bit) information can be written. The word line voltage application example in FIG. 23 shows a case where the threshold control is completed by one write verify operation after the write operation at each stage. As for the method of applying the write pulse, high-speed writing can be realized by using the operation method of the sixth embodiment described above.

(2) Read Operation First, FIG. 30 to FIG. 35 show a method of reading 2-bit (4-level) data written in one memory cell and converting it into a 1-bit (binary) data string. It will be described using FIG. For each threshold value of the quadrupolarized memory cell as shown in FIG. 23 generated by the above-described (1) write operation,
The read voltage applied to the word line during the read operation is shown in FIG.
Vth0 <Vr1 <Vth1 <Vr2 <V
Voltage Vr that satisfies th2 <Vr3 <Vth3
1, Vr2 and Vr3. FIG. 31 shows an example of the word line applied voltage at that time. Here, the operation of performing reading by applying Vr1 to the word line is referred to as “reading 1”.
The operations of performing reading by applying Vr3 and Vr3 are referred to as "reading 2" and "reading 3", respectively. In this example, by performing the read operation three times as described above, the quaternary (2-bit) information written in the memory cell is read from "read 1" to "read 1".
It is characterized in that it is read as binary (1 bit) information for each read operation of “read 3”.

Next, the four values (2 bits) written to the memory cells in the respective operations of "read 1" to "read 3"
32, four values (2 bits) of "00", "01", "10", and "11" are respectively applied to four memory cells MC1 to MC4 connected to one word line as shown in FIG. The case where the data is written will be described as an example. These four-valued (two-bit) values are written into the MC1 to MC4 by dividing the binary data string "00011011" by two by the above-described write operation, as "00", "01", "10", and "11". These are read and latched by the sense latches SL1 to SL4. According to the present example, the multi-level (quaternary) stored in one memory cell by such a simple configuration of the sense latch circuit.
Can be read.

FIG. 33 shows the operation of "read 1".
Relationship between threshold values of memory cells MC1 to MC4 and read voltage Vr1 applied to a word line,
Sense latches SL1 to SL4 read from C1 to MC4
FIG. 5 is a diagram schematically showing binary (1 bit) data RT1 latched in FIG. Similarly, FIG. 34 and FIG.
The relationship between the threshold voltage of each of the memory cells MC1 to MC4 and the read voltages Vr2 and Vr3 applied to the word line,
FIG. 11 is a diagram showing binary (1 bit) data RT2 and RT3 read from memory cells MC1 to MC4 and latched in sense latches SL1 to SL4 by respective operations of "read 2" and "read 3". . 2 read by the above-described operations of "read 1" to "read 3"
The value (1 bit) data RT1 to RT3 are read by the read data conversion circuit 2 in FIG. 15 and the four value (2 bit) data “00” “01” “10” stored in the memory cell.
Converted to "11".

In this way, the voltage applied to the word line at the time of reading is written to the memory cell by three reading operations of "read 1" to "read 3" set to Vr1 to Vr3. 2 corresponding to quaternary (2 bits) information
The value data is read and converted by the data conversion circuit 2 into a binary data string, so that quaternary (2-bit) information can be read.

[0077]

According to the present invention, writing and erasing are performed by a tunnel current through the entire surface of the channel region by utilizing the tunnel phenomenon between the floating gate electrode and the substrate. It is not necessary to increase the overlap region with the gate, and a memory cell having a symmetrical source and drain can be employed, so that miniaturization is possible. Further, since it is not necessary to apply a high voltage to the drain to extract electrons from the floating gate as in the conventional case, injection of holes into the oxide film can be suppressed, and deterioration of the memory cell can be reduced. Further, the distribution of the threshold voltage in the erased state can be narrowed, and the retention and disturb characteristics of the memory cell due to the threshold voltage variation can be improved.

Further, depending on the operation method of increasing the gate voltage in two stages at the time of writing into the memory cell and the circuit configuration in which a MOS transistor or a dummy memory cell is connected between the data line and the source line in parallel with the memory cell, non-selection is performed. Disturb to the memory cell can be reduced. In addition, when writing is performed in a plurality of times, an excessive electric field is applied to a memory cell in which writing is fast due to an operation method in which the data line voltage of a selected memory cell is decreased with an increase in the number of times. And writing is performed with a higher electric field on a memory cell that is difficult to write, so that writing can be performed at high speed and with high reliability.

Further, by adopting a configuration in which one sense latch is shared by two or more data lines and a configuration in which one data line is shared by two sub-data lines, miniaturization of memory cells can be achieved. Layout becomes possible. Further, a large capacity can be realized by providing an operation method in which information of 2 bits or more can be written to and read from a memory cell.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a write operation timing in the first embodiment of the present invention.

FIG. 3 is a diagram showing an operating voltage condition (a) and an example of a threshold voltage distribution (b) in the case where both the threshold after writing and the threshold after erasing are both positive in the first embodiment of the present invention. It is.

FIG. 4 shows an operating voltage condition (a) and a threshold voltage distribution example (b) when the threshold value after writing is positive and the threshold value after erasing is negative in the first embodiment of the present invention. FIG.

FIG. 5 is a diagram showing a circuit configuration according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a write operation timing in a third embodiment of the present invention.

FIG. 8 is a diagram showing a circuit configuration according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing an example of a memory cell threshold voltage distribution according to a fourth embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of an erase operation according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a first erase operation timing in the fourth embodiment of the present invention.

FIG. 12 is a diagram showing a second erase operation timing in the fourth embodiment of the present invention.

FIG. 13 is a diagram for explaining a fifth embodiment of the present invention.

FIG. 14 is a diagram showing a circuit configuration according to a sixth embodiment of the present invention.

FIG. 15 is a diagram showing a write operation timing in a sixth embodiment of the present invention.

FIG. 16 is a diagram showing a circuit configuration according to a seventh embodiment of the present invention.

FIG. 17 is a diagram showing a circuit configuration according to an eighth embodiment of the present invention.

FIG. 18 is a flowchart showing the operation of the seventh and eighth embodiments of the present invention.

FIG. 19 is a diagram showing a circuit configuration according to a ninth embodiment of the present invention.

FIG. 20 is a diagram showing a circuit configuration according to a tenth embodiment of the present invention.

FIG. 21 is a diagram showing a flowchart of the operation of the tenth embodiment of the present invention.

FIG. 22 is a diagram showing an overall view in an eleventh embodiment of the present invention.

FIG. 23 is a diagram showing a relationship between a write verify word line voltage and a memory cell threshold voltage in an eleventh embodiment of the present invention.

FIG. 24 is an example of a word line applied voltage at the time of a write operation in FIG. 22;

FIG. 25 is a diagram showing correspondence between write four-level data and memory cells in an eleventh embodiment of the present invention.

FIG. 26 is a diagram illustrating a memory cell threshold value before writing according to an eleventh embodiment of the present invention.

FIG. 27 is a diagram illustrating a change in the memory cell threshold value due to writing in the eleventh embodiment of the present invention (part 1).

FIG. 28 is a diagram illustrating a change in the memory cell threshold value due to writing in the eleventh embodiment of the present invention (part 2).

FIG. 29 is a diagram illustrating a change in the memory cell threshold value due to writing in the eleventh embodiment of the present invention (part 3).

FIG. 30 is a diagram showing a relationship between a read word line voltage and a threshold voltage of a memory cell according to an eleventh embodiment of the present invention.

FIG. 31 is a diagram showing an example of a word line applied voltage at the time of a read operation in the eleventh embodiment of the present invention.

FIG. 32 is a diagram showing correspondence between written 4-level data and memory cells in the eleventh embodiment of the present invention.

FIG. 33 is a diagram showing a threshold value of a memory cell and read binary data in the eleventh embodiment of the present invention (part 1).

FIG. 34 is a diagram showing a threshold value and read binary data of a memory cell in an eleventh embodiment of the present invention (part 2).

FIG. 35 is a diagram showing a threshold value and read binary data of a memory cell in an eleventh embodiment of the present invention (part 3).

FIG. 36 is a configuration diagram of a conventional NOR flash memory.

FIG. 37 is a configuration diagram of a conventional AND flash memory.

[Explanation of symbols]

M11 to M22: memory cell, W1, W2: word line, D1, D2: data line, WD: word decoder, DS1 to DSn: node, SD: drain selection MOS transistor gate signal line, SS: source selection MOS transistor gate signal Line, DC: data line discharge MOS transistor gate signal line, EL: memory cell well voltage, CS: common source line, 1: write data conversion circuit, 2: read data conversion circuit, 3: memory cell array, 4: sense latch 5, bit line, 6: word line, 7: word driver, 8: row decoder, 9: power supply switching circuit, 10: main amplifier, 11: column decoder, 12: control circuit, 13: address buffer, 14: verify End signal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masataka Kato 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Kazuhiro Komori Gojokami-cho, Kodaira-shi, Tokyo No. 20-1, Hitachi Semiconductor Co., Ltd.Semiconductor Division (72) Inventor Hitoshi Kume 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Tokyo, Japan Inside the Central Research Laboratory, Hitachi, Ltd. 280 Chome, Central Research Laboratory, Hitachi, Ltd.

Claims (21)

[Claims] 1. A memory array in which nonvolatile semiconductor memory cells capable of electrically writing and erasing data to a floating gate are arranged in a matrix in a well region formed in a semiconductor substrate, and a drain of the memory cell is diffused. Connected to a data line formed of metal wiring via a drain selection MOS transistor after being connected to a sub data line formed of a layer, and connected to a sub source line formed of a diffusion layer through a drain selection MOS transistor. In a nonvolatile semiconductor memory device having a structure connected to a common source line via a source selection MOS transistor, when performing an electric write operation of a memory cell, a tunnel phenomenon between a floating gate and a well is used to pass through the entire channel. Injecting electrons into the floating gate and performing the erase operation, the tunneling phenomenon between the floating gate and the well is used to pass through the entire channel. Operation method to perform electrical rewriting by extracting electrons from the floating gate, and for the memory cell connected between the data line and the source line,
When one or a plurality of MOS transistors or dummy memory cells are connected in parallel and the write operation is performed, the M transistor is applied before a positive voltage is applied to the gate of the memory cell.
A nonvolatile semiconductor memory device in which an OS transistor or a dummy memory cell is turned on to set a data line and a source line to the same potential. 2. A memory array in which nonvolatile semiconductor memory cells capable of electrically writing and erasing data to and from a floating gate are arranged in a matrix in a well region formed in a semiconductor substrate, and a drain of the memory cell is diffused. Connected to a data line formed of metal wiring via a drain selection MOS transistor after being connected to a sub data line formed of a layer, and a source of a memory cell is formed of a diffusion layer paired with the sub data line In a nonvolatile semiconductor memory device having a structure connected to a sub-source line and then connected to a common source line via a source selection MOS transistor, a tunnel phenomenon between a floating gate and a well occurs when an electric write operation of a memory cell is performed. Inject electrons into the floating gate through the entire surface of the channel using An operation method of electrically rewriting by extracting electrons from the floating gate through the entire surface of the channel by using one or a plurality of memory cells connected between the data line and the source line in parallel. MO
When an S transistor or a dummy memory cell is connected and the write operation is performed, the MOS transistor or the dummy memory cell is turned on before applying a positive voltage to the gate of the memory cell, and the data line and the source line are connected. A nonvolatile semiconductor memory device which is set to a potential. 3. A memory array in which nonvolatile semiconductor memory cells capable of electrically writing and erasing data to and from a floating gate are arranged in a matrix in a well region formed in a semiconductor substrate, and a drain of the memory cell is diffused. Connected to a data line formed of metal wiring via a drain selection MOS transistor after being connected to a sub data line formed of a layer, and a source of a memory cell is formed of a diffusion layer paired with the sub data line In a nonvolatile semiconductor memory device having a structure connected to a sub-source line and connected to a common source line via a source selection MOS transistor, a well is connected to a floating gate of the memory cell when performing an electric write operation of the memory cell. The floating gate through the entire channel using the tunneling phenomenon between the floating gate and the well by applying a positive high voltage to the During the erasing operation, a high negative voltage is applied to the well to the control gate of the memory cell, and tunneling between the floating gate and the well is used to cause electrons from the floating gate to pass through the entire channel. The operation method of performing electrical rewriting by pulling out the data line, the memory cell connected between the data line and the source line,
One or a plurality of MOS transistors or dummy memory cells are connected in parallel, and when a write operation is performed, the M transistor is applied before a positive voltage is applied to the gate of the memory cell.
A nonvolatile semiconductor memory device in which an OS transistor or a dummy memory cell is turned on to set a data line and a source line to the same potential. 4. A memory array in which non-volatile semiconductor memory cells capable of electrically writing and erasing data to a floating gate are arranged in a matrix in a well region formed in a semiconductor substrate, and a drain of the memory cell is diffused. Connected to a data line formed of metal wiring via a drain selection MOS transistor after being connected to a sub data line formed of a layer, and connected to a sub source line formed of a diffusion layer through a drain selection MOS transistor. In a nonvolatile semiconductor memory device having a structure connected to a common source line via a source selection MOS transistor, a positive high voltage is applied to the control gate of the memory cell with respect to the well when performing an electric write operation of the memory cell. By applying a voltage to the floating gate and injecting electrons into the floating gate through the entire surface of the channel using the tunnel phenomenon between the well, the erase operation When rewriting, electrical rewriting is performed by applying a high negative voltage to the well to the control gate of the memory cell and extracting electrons from the floating gate through the entire channel using the tunnel phenomenon between the floating gate and the well. Before the write operation of the memory cell is performed, a high positive voltage is applied to the gate before applying a high positive voltage to the floating gate to inject electrons into the floating gate. A non-volatile semiconductor memory device, wherein a memory cell is turned on to set a data line and a source line to the same potential. 5. A memory array in which nonvolatile semiconductor memory cells capable of electrically writing and erasing data to a floating gate are arranged in a matrix in a well region formed in a semiconductor substrate, and a drain of the memory cell is diffused. Connected to a data line formed of metal wiring via a drain selection MOS transistor after being connected to a sub data line formed of a layer, and a source of a memory cell is formed of a diffusion layer paired with the sub data line In a nonvolatile semiconductor memory device having a structure connected to a sub-source line and connected to a common source line via a source selection MOS transistor, a well is connected to a control gate of the memory cell when performing an electric write operation of the memory cell. The floating gate through the entire channel using the tunneling phenomenon between the floating gate and the well by applying a positive high voltage to the During the erasing operation, a high negative voltage is applied to the well to the control gate of the memory cell, and tunneling between the floating gate and the well is used to cause electrons from the floating gate to pass through the entire channel. An operation method in which electrical rewriting is performed by pulling out the gate, before the write operation of the memory cell is performed, before a high positive voltage is applied to the gate to inject electrons into the floating gate, and electrons are not injected. Wherein the memory cell is turned on by applying the positive voltage to the gate, and the data line and the source line are set to the same potential. 6. A memory array in which nonvolatile semiconductor memory cells capable of electrically writing and erasing data to and from a floating gate are arranged in a matrix in a well region formed in a semiconductor substrate, and a drain of the memory cell is diffused. Connected to a data line formed by metal wiring via a drain selection MOS transistor via a drain selection MOS transistor, connected to a sub data line formed of a layer, and connected to a source selection MOS transistor by connecting a source of a memory cell to the sub data line. A nonvolatile semiconductor memory device having a structure connected to a common source line via
Electrons are injected into the floating gate through the entire surface of the channel using the tunneling phenomenon between the floating gate and the well during the electrical writing operation of the memory cell, and the tunneling phenomenon between the floating gate and the well is performed during the erasing operation. And an operation method of electrically rewriting by extracting electrons from the floating gate through the entire surface of the channel by using the semiconductor memory device. When the erase operation is performed, the threshold voltages of all the memory cells to be erased are set to be equal to or lower than the first voltage. A first erasing operation until an erasing operation is performed, and a second erasing operation in which writing back is performed by selectively injecting electrons into a floating gate only for a memory cell having a threshold voltage equal to or lower than a second voltage. A nonvolatile semiconductor memory device characterized by the above-mentioned. 7. A memory array in which nonvolatile semiconductor memory cells capable of electrically writing and erasing data to and from a floating gate are arranged in a matrix in a well region formed in a semiconductor substrate, and a drain of the memory cell is diffused. Connected to a data line formed of metal wiring via a drain selection MOS transistor after being connected to a sub data line formed of a layer, and a source of a memory cell is formed of a diffusion layer paired with the sub data line In a nonvolatile semiconductor memory device having a structure connected to a sub-source line and then connected to a common source line via a source selection MOS transistor, a tunnel phenomenon between a floating gate and a well occurs when an electric write operation of a memory cell is performed. Inject electrons into the floating gate through the entire surface of the channel using And an operation method of electrically rewriting by extracting electrons from the floating gate through the entire surface of the channel by using the semiconductor memory device. When the erase operation is performed, the threshold voltages of all the memory cells to be erased are set to be equal to or lower than the first voltage. A first erasing operation until an erasing operation is performed, and a second erasing operation in which writing back is performed by selectively injecting electrons into a floating gate only for a memory cell having a threshold voltage equal to or lower than a second voltage. A nonvolatile semiconductor memory device characterized by the above-mentioned. 8. A memory array in which nonvolatile semiconductor memory cells capable of electrically writing and erasing data to and from a floating gate are arranged in a matrix in a well region formed in a semiconductor substrate, and a drain of the memory cell is diffused. Connected to a data line formed of metal wiring via a drain selection MOS transistor after being connected to a sub data line formed of a layer, and a source of a memory cell is formed of a diffusion layer paired with the sub data line In a nonvolatile semiconductor memory device having a structure in which the memory cell is connected to a sub-source line and then connected to a common source line via a source selection MOS transistor, a control gate of the memory cell is connected to a well when an electric write operation of the memory cell is performed. By applying a positive high voltage to the floating gate through the entire channel using the tunneling phenomenon between the floating gate and the well At the time of injecting electrons and performing an erase operation, a high negative voltage is applied to the well to the control gate of the memory cell, and electrons are emitted from the floating gate through the entire channel using the tunnel phenomenon between the floating gate and the well. An operation method of performing electrical rewriting by pulling out is provided. When performing an erasing operation, a negative voltage is applied to the control gate with respect to the well until the threshold voltages of all target memory cells become equal to or lower than the first voltage. A positive voltage is applied to the control gate to the well, source, and drain only for the first erase in which a high voltage is applied and only for the memory cell whose threshold voltage is lower than the second voltage, and selectively to the floating gate. A write-back operation of injecting electrons is performed. For a memory cell having a threshold voltage equal to or higher than the second voltage, a positive high voltage is applied to the control gate with respect to the well, and the source and the drain are applied with a higher voltage than the well. The nonvolatile semiconductor memory device which comprises carrying out the second erasing operation is not performed write-back operation by applying a voltage of ITadashi. 9. The nonvolatile semiconductor memory device according to claim 6, wherein in the erasing operation, the first voltage is higher than the second voltage. 10. The erase operation has a function of outputting an error signal to the outside when there is a memory cell whose threshold voltage after a write-back operation is equal to or higher than a predetermined voltage. 10. The nonvolatile semiconductor memory device according to any one of 6 to 9. 11. In the erase operation, when there is a memory cell whose threshold voltage after a write-back operation is equal to or higher than a predetermined voltage, a write operation is performed on all memory cells to be erased, 11. The nonvolatile semiconductor memory device according to claim 6, wherein the nonvolatile semiconductor memory device has a function of increasing the threshold voltage. 12. In the erase operation, when there is a memory cell whose threshold voltage after a write-back operation is equal to or higher than a predetermined voltage, error information is written to a management bit provided in a word line to be erased. 7. The method according to claim 6, wherein
12. The nonvolatile semiconductor memory device according to any one of items 11 to 11. 13. When writing and erasing the memory cell, the source and the drain of the target memory cell are set to the same potential as the well, and a positive or negative voltage is applied to the control gate to the well. The nonvolatile semiconductor memory device according to claim 1, wherein 14. A writing operation for said memory cell,
14. The nonvolatile semiconductor memory device according to claim 1, wherein the sub-source line is in an open state. 15. The threshold voltage after writing and the threshold voltage after erasing are both positive voltages, or the threshold voltage after writing is positive and the threshold voltage after erasing. 15. The nonvolatile semiconductor memory device according to claim 1, wherein is a negative voltage. 16. A means for dividing the write operation into a plurality of times when performing the write operation on the memory cell, and reducing the data line voltage and the source line voltage of the memory cell to be written as the number of times increases. The nonvolatile semiconductor memory device according to claim 1, further comprising: 17. The method according to claim 1, wherein one sense latch is shared by two or more of said data lines.
7. The nonvolatile semiconductor memory device according to claim 6. 18. The nonvolatile semiconductor memory device according to claim 1, wherein one data line and one sense latch are shared by two or more sub data lines. 19. The data processing apparatus according to claim 17, further comprising means for performing a write operation by dividing the number of data lines or sub data lines sharing the sense latch into several.
9. The nonvolatile semiconductor memory device according to 8. 20. When performing the write operation, a data line to which a memory cell to be written is not connected is opened after charging a positive voltage, and then a data line to which a memory cell to be written is connected is connected. 20. The nonvolatile memory according to claim 17, further comprising means for applying a voltage corresponding to write information to the line, and thereafter applying a positive high voltage to the control gate to the well. Semiconductor memory device. 21. The apparatus according to claim 1, further comprising means capable of writing information of 2 bits or more in one memory cell and reading the information. Nonvolatile semiconductor memory device.