JPH10200058A - Semiconductor memory device having ferroelectric capacitor - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To significantly improve the memory capacity per unit area without increasing the cell area. SOLUTION: A selection transistor 2 in which one of a source and a drain is connected to one of a pair of bit lines BL, and a storage node electrode 3 is connected in parallel to the other side of the source or the drain. A plurality of ferroelectric capacitors C ₀ and C ₁ capable of storing different storage data
Form the memory cell 1 and the capacitors C ₀ ,
The plate line selection signal AP which is connected to the plate electrode 4 of C ₁ and is inputted on condition that the word line WL is excited.
There is provided a plate line selection circuit 5 for selectively connecting any one of the plate electrodes 4 of the ferroelectric capacitors C ₀ and C ₁ to the plate voltage supply line PL in accordance with O and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a plurality of ferroelectric capacitors capable of storing different storage data in one memory cell. The present invention relates to an arrangement structure and a circuit configuration for selectively switching a capacitor.

[0002]

2. Description of the Related Art Conventionally, a ferroelectric memory element has a cell type in which one bit is composed of two select transistors and two ferroelectric capacitors (2Tr-2C).
(1 ap type) and one bit composed of one selection transistor and one ferroelectric capacitor (1 Tr
-1 Cap method). 2Tr-2Ca
In the p-method, the reference at the time of data reading can be set inside the cell,
There are advantages that the data read operation is not easily affected by variations in processes and film characteristics, and that a low-voltage operation is possible. In contrast, in the 1Tr-1Cap method,
In order to be suitable for high integration, a memory cell itself is simplified by sharing a cell serving as a reference for data reading for each bit line pair.

[0003]

These ferroelectric memory elements are also required to have a large capacity like other memory elements. When increasing the total storage capacity, it is necessary to minimize the chip area. Controlling is an important issue. For this reason, in order to improve the capacitance value per unit area, various studies such as the development of a ferroelectric thin film having a high dielectric constant and the increase of the electrode surface area have been advanced, and some results have been achieved. However, even if it is attempted to increase the capacitance per unit area of the ferroelectric memory element in the conventional cell format, due to the difficulty in developing the ferroelectric thin film itself and the difficulty in handling the ferroelectric thin film, It is not easy to greatly increase the storage capacitance value.

The present invention has been made in view of such circumstances, and has proposed and used a new cell structure capable of greatly improving the memory capacity per unit area without increasing the cell area. An object of the present invention is to provide a large-capacity, high-performance ferroelectric memory element.

[0005]

In order to solve the above-mentioned problems of the prior art and achieve the above object, a ferroelectric memory device according to the present invention employs a plurality of ferroelectric capacitors having a common selection transistor. Are provided in the memory cell, and a circuit for controlling which of the data is stored and which storage data is read is provided. That is, in the ferroelectric memory device of the present invention, a selection transistor in which one of a source and a drain is connected to one of a pair of bit lines, and a storage node electrode is connected to the other side of the source or the drain of the selection transistor. Are connected in parallel, and a plurality of ferroelectric capacitors each capable of storing different storage data constitute a memory cell, which is connected to the plate electrodes of the plurality of ferroelectric capacitors and a word line is excited. And a plate line selection circuit for selectively connecting any one of the plate electrodes of the plurality of ferroelectric capacitors to the plate voltage supply line in accordance with the input plate line selection signal.

It is preferable that the plurality of ferroelectric capacitors be spaced apart from each other in a direction perpendicular to the semiconductor substrate surface with the selection transistor interposed therebetween, since the memory capacity per unit area can be at least twice as large as that of the prior art.

Further, when the select transistor and the plurality of ferroelectric capacitors are arranged in a form buried in a thick insulating layer on the semiconductor substrate, the select transistor becomes S
OI (Silicon On Insulator) type element isolation structure,
Higher speed and lower power consumption of the selection transistor
Further, electrical interference between the plate lines of the capacitor can be reduced, which is preferable.

In the ferroelectric memory device having such a configuration,
A plurality of bits of information can be stored in one memory cell, and a storage capacity several times that of a conventional memory can be achieved. Further, by arranging the ferroelectric capacitors in a three-dimensional manner, the occupied area can be equalized or the area increase can be suppressed as much as possible. In addition, the performance of the selection transistor can be improved, and as a result, a large-capacity, high-speed operation ferroelectric memory device can be easily realized.

On the other hand, when two ferroelectric capacitors are provided in a memory cell, a specific configuration of a plate line selection circuit for selectively connecting the two ferroelectric capacitors to a plate line is as follows. Control gates may be provided in the middle of each of the connection paths, and the two control gates may be operated to invert each other by a plate line selection signal. That is, in the plate line selection circuit in this case, the word line is connected to the first input terminal,
An AND gate to which the plate line selection signal is connected to a second input terminal; and an AND gate connected between one plate electrode of the two ferroelectric capacitors and the plate voltage supply line. An output is connected between a first control gate connected to the other plate electrode and the plate voltage supply line, and the AND gate is connected to the gate.
The output of the gate is connected via an inverter,
A second control gate inverting the control gate of
It is characterized by having.

Further, when these control gates are constituted by transmission gates operated by a plate line selection signal and its inverted signal, it is possible to achieve a low impedance when conducting and a high impedance when not conducting, which is preferable. . That is, in the plate line selection circuit in this case, the AND gate has a first AND terminal having the first input terminal and the second input terminal.
A first AND gate having a second input terminal to which the plate line selection signal is inputted and an output of which is a gate of a transistor constituting the first control gate. Connected to the second
Of the AND gate receives an inverted signal of the plate line selection signal at a second input terminal thereof, and outputs the inverted signal of the second line to the second input terminal.
The transistor forming the first control gate is connected to the gate of the transistor forming the control gate of the first control gate, and the output of the first AND gate is connected to the gate through the inverter. Together with a transistor of the second conductivity type, the transistor forming the second control gate is a transistor of the opposite conductivity type, the output of which is connected to the gate of the second AND gate. It is characterized by constituting a transmission gate.

Such a plate line selection circuit has a simple circuit configuration. The 1Tr-2Cap type ferroelectric storage device newly proposed in the present invention for the purpose of increasing the memory capacity per unit area is described in the following. It is suitable as a capacitor switching circuit in a memory cell.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A ferroelectric memory device (ferroelectric memory) according to the present invention will be described below in detail with reference to the drawings. The feature of the ferroelectric memory of the present invention is that, as described above, each memory cell has a plurality of ferroelectric capacitors capable of storing different data, and a circuit for controlling the selection is provided. It is in. Therefore, the number of ferroelectric capacitors in the memory cell is not limited, and the arrangement is not particularly limited. However, in order to suppress an increase in the cell area, it is desirable to arrange the capacitors three-dimensionally in a direction perpendicular to the substrate surface.

Here, the present invention will be described by taking as an example a case where two ferroelectric capacitors are provided vertically symmetrically with a common selection transistor interposed therebetween and the memory capacity can be doubled without changing the cell area. . FIG. 1A is an equivalent circuit diagram showing a configuration example of a memory cell of the ferroelectric memory device of the present invention, and FIG. 1B is a circuit diagram showing a configuration example of a plate line selection circuit. In the figure, reference numeral 1 denotes a memory cell of a ferroelectric memory, and 2 denotes a selection transistor. C ₀ and C ₁
Denotes two ferroelectric capacitors, an electrode serving as a storage node (referred to as a storage node electrode in the present invention) is denoted by reference numeral 3, and a plate electrode is denoted by reference numeral 4. Also,
BL is a bit line, WL is a word line, and PL ₀ and PL ₁ are plate lines connected to plate electrodes of the ferroelectric capacitors C ₀ and C ₁ , respectively.

In the present invention, one of the impurity diffusion regions (for example, drain) of the common selection transistor 2 is used.
The two ferroelectric capacitors C ₀ and C ₁ are connected in parallel from the storage node electrode 3 side to form a memory cell. Then, memory cells having the same configuration are regularly arranged at each intersection of the bit line BL and the word line,
The entire memory array is configured.

On the other hand, in the ferroelectric memory of the present invention, FIG.
As shown in (a), for example, a plate line selection circuit 5 is provided around a memory array. The plate line selection circuit 5 includes the word line WL and the two plate lines PL.
₀ , PL ₁ and the plate voltage supply line PL are connected. In addition, a selection signal line (not shown) and the like are also connected. The function and specific configuration of the plate line selection circuit 5 will be described later.

FIG. 2 is a schematic sectional view of the memory cell 1 and the plate line selection circuit 5 of FIG. 1 and another memory cell adjacent to the memory cell 1 and sharing the bit line BL.
In FIG. 2, the structure for taking out the plate line of another memory cell is omitted for simplification. Also, FIG.
The connection between the plate line selection circuit 5 and the plate line is schematically shown, and does not correspond to an actual circuit (for example, FIG. 1B).

In FIG. 2, reference numerals 10b and 10c denote active regions of a MOS transistor left by etching back a silicon substrate (not shown), 11 denotes a first interlayer insulating layer, 16 denotes a second interlayer insulating layer, and 17 denotes a second interlayer insulating layer. A connection plug, 18 indicates a third interlayer insulating layer, 19 indicates a semiconductor substrate, and 20 indicates an adhesive layer. In the ferroelectric memory device of the present embodiment, two ferroelectric capacitors C ₀ and C ₁ are arranged in a direction perpendicular to the surface of the semiconductor substrate 19 with the selection transistor 2 interposed therebetween. Therefore, the size of the memory cell 1 is almost determined by the area occupied by the select transistor 2, and the memory cell 1 has two ferroelectric capacitors C ₀ and C ₁ and can store 2-bit data. Therefore, compared with the case where the selection transistor 2 and the ferroelectric capacitor are arranged on a plane, the capacitance value per unit area is improved about four times, and a structure suitable for an extremely large-capacity ferroelectric memory is provided. I have.

Next, in the method of manufacturing the ferroelectric memory thus configured, FIG.
9 will be described. In FIG. 3A, first, a silicon substrate 10 is prepared, and a groove 10a having a predetermined depth is formed on the surface of the silicon substrate 10 by ordinary photolithography and anisotropic etching such as RIE. As will be described next, by filling the space between the trenches 10a with an insulating film, element isolation is achieved for the selection transistor 2 of the memory cell 1 or the transistor constituting the plate line selection circuit 5. The left end (reference numeral 10b) of the figure becomes an active region of the select transistor 2 of the memory cell 1 among the groove intervals, and the other groove interval 10c
Are active regions of the transistors constituting the plate line selection circuit 5.

In FIG. 3B, after a silicon oxide film (not shown) is thinly formed on the silicon substrate 10 in which the trench 10a is formed, the first interlayer insulating layer 11 and the etching stopper film 12 are formed, for example. CVD (Chemical Vapor Deposition)
The film is formed by a method. Also, this etching stopper film 1
A relatively thick sacrifice layer 13 is formed on the substrate 2 by using, for example, a CVD method or an SOG (Spin on Glass) method. As the first interlayer insulating layer 11, for example, a silicon oxide film can be used, and the sacrifice layer 13 is formed of a silicon oxide-based film. The etching stopper film 12 is made of a material having a high etching selectivity with respect to the sacrifice layer 13 on the upper side, for example, a silicon nitride film or the like. After the first interlayer insulating layer 11 is formed, it is desirable that the first interlayer insulating layer 11 be flattened by, for example, chemical mechanical polishing (CMP). Then, a groove interval portion 10b serving as an active region on the memory cell side
Is formed by anisotropic etching such as RIE.

In FIG. 4C, first, a film is formed by embedding a storage node electrode material in the contact hole 14, and the plug-shaped storage node electrode 3 is formed by etching back. Thereafter, the sacrificial layer 13 is removed with a hydrofluoric acid-based etchant, and the etching stopper film 12 is removed with a phosphoric acid-based etchant.

In FIG. 4D, first, a film to be the ferroelectric film 15 and the plate electrode 4 is formed continuously, for example, by a CVD method. Then, the laminated film is processed into a predetermined shape by ordinary photolithography and anisotropic etching such as RIE. As a result, the ferroelectric capacitor C ₀ is set up from the active region 10b of the select transistor.
Is formed.

In FIG. 5E, first, a second interlayer insulating layer 16 is formed on the entire surface. The second interlayer insulating layer 16 is made of, for example, a silicon oxide film. A contact hole is formed in second interlayer insulating layer 16 and first interlayer insulating layer 11. This contact hole is opened on the plate electrode of the ferroelectric capacitor C ₀ and on the active region 10 c of the predetermined transistor forming the plate line selection circuit 5. Then, a film made of polysilicon or the like is formed so as to fill these contact holes, and this film is etched back to form the connection plug 17. Further, a stacked film of tungsten (W), or W and aluminum (Al) was deposited, by conventional photolithography and anisotropic etching such as RIE, forming a plate line PL _0.

In FIG. 6 (f), first, a relatively thick silicon oxide-based third interlayer insulating layer 18 is formed on the entire surface by a CVD method or the like. After forming an adhesive layer 20 made of, for example, polysilicon as an adhesive material with a semiconductor substrate 19 such as a silicon wafer on the formed third interlayer insulating layer 18,
The upper surface of the adhesive layer 20 is flattened by CMP or the like. Then, the semiconductor substrate 19 is adhered from the side of the adhesive layer 20 and brought into close contact by heat treatment.

In FIG. 7 (g), the semiconductor substrate 19, which has just been bonded, is turned up, and the upper surface thereof is polished by mechanical polishing, CMP, or the like, so that the first interlayer insulating layer 11 is exposed on the surface. Finish the polishing. As a result, the active regions 10b, 10b of the transistor are formed on the surface of the first interlayer insulating layer 11.
c is left in an embedded form.

In FIG. 8 (h), first, the active regions 10b,
After impurity is implanted into the active region 10b on the memory cell 1 side, the word line ML serving as the gate electrode of the selection transistor 2 and the gate electrode of the transistor on the plate line selection circuit 5 side are implanted into the active region 10b. 21 and
It is formed by ordinary photolithography and anisotropic etching such as RIE. These electrode materials are polysilicon films. Next, by using these electrodes ML and 21 as a mask, impurities are implanted into the entire surface according to the channel conductivity type by ion implantation, whereby each active region 10b, 10
A source region 22 and a drain region 23 are formed in c. After an insulating film such as silicon oxide is formed on the entire surface, a bit line B made of polysilicon is formed using the same processing technique.
L is formed so as to be connected to the source region 22 of the select transistor 2 of the memory cell 1. Then, the first interlayer insulating layer 11 made of silicon oxide or the like is formed again on the entire surface, and the upper surface is flattened.

Thereafter, a second ferroelectric capacitor C ₁ is formed by the same method as that of the above-described step of FIG. 4 (FIG. 9I), and this is connected to the plate line selection circuit 5. a second plate line PL ₁ to be formed (FIG. 2). Thereafter, the ferroelectric memory can be completed through formation of a protective film, opening of a pad window, and the like.

Finally, the specific configuration and operation of the plate line selection circuit 5 illustrated in FIG. 1B will be described.
Note that the data write and data read operations to the memory cell
Since the operation is basically the same as that in the normal case, the operation here will be described for the selective switching of the plate line.

In the figure, reference numerals TG ₀ and TG ₁ indicate transfer gates. The transfer gate TG ₀ is
It is connected between the plate voltage supply line PL and the plate line PL _0. Also, the transfer gate TG ₁
It is connected between the plate voltage supply line PL and the plate line PL _1. Each transfer gate TG ₀ , TG
Reference numeral ₁ denotes a P-channel MOSFET (PMOS 30) having sources and drains interconnected, and an N-channel MOSFET (NMOS 31).

On the other hand, the symbols AND ₀ and AND ₁ indicate AND gates. A word line WL is connected to one input of AND ₀ and AND ₁ . The other input of the AND _0, the plate line selection signal APO are input. In contrast, the other input of the AND _1, the inverted signal / APO of the plate line selection signal APO are input. The output of AND ₀ is output to the NMOS 31 constituting the transfer gate TG _0.
Is connected to the gate of, via the inverter INV _0, PMOS constituting the transfer gate TG ₀
30 gates. Similarly, the output of the AND ₁ includes a gate of NMOS31 of the transfer gate TG _1, is connected to the gate of the PMOS30 of the transfer gate TG ₁ via an inverter INV _1.

When the ferroelectric capacitor C _{0 in} FIG. 1A is selected and the word line WL is excited, a plate line selection signal APO is input to the plate line selection circuit 5 having such a configuration. If this plate line selection circuit 5 is active high, the output of AND ₀ becomes “high (H)”, and the NMOS 31 constituting the transfer gate TG ₀
And PMOS 30 both conduct, and plate line PL
₀ is connected to the plate voltage supply line PL. On the other hand, AND
The output of the ₁ remains "low (L)", in the plate line PL ₁ of the ferroelectric capacitor C ₁ of the non-selection, the plate voltage is not supplied.

[0031] Conversely, the ferroelectric capacitor C ₁ is selected and the word line WL is energized, the plate line selection signal APO is not input, the inverted signal / APO are input. Therefore, the output of the AND ₀ is "L", the output of the the AND ₁ becomes "H", the transfer gates TG ₁ and cut off the transfer gate TG ₀ is conductive. Therefore, the plate line connected to the plate voltage supply line PL is PL ₀
It is switched to PL ₁ from.

[0032]

As described above, according to the semiconductor memory device having the ferroelectric capacitor according to the present invention, one memory cell is constituted by one selection transistor and a plurality of ferroelectric capacitors. A plurality of bits of data can be stored in a cell. At this time, by arranging a plurality of ferroelectric capacitors in a three-dimensional manner, an increase in the occupied area of the memory cell can be suppressed as much as possible.
Further, by adopting the SOI type element isolation structure, the speed of the selection transistor can be increased and the power consumption can be reduced. In addition, the electric connection between two plate lines connected to the plate electrodes of the two ferroelectric capacitors can be achieved. Interference is small, and stable operation of the ferroelectric capacitor is ensured.

Therefore, according to the present invention, a new cell structure capable of greatly improving the memory capacity per unit area without increasing the cell area is proposed. A dielectric memory device can be provided.

[Brief description of the drawings]

FIG. 1A is an equivalent circuit diagram showing a configuration example of a memory cell of a ferroelectric memory device according to an embodiment of the present invention. FIG. 1B is a circuit diagram illustrating a configuration example of the plate line selection circuit.

FIG. 2 is a schematic cross-sectional view of the memory cell and plate line selection circuit of FIG. 1 and another memory cell adjacent to the memory cell and sharing a bit line.

FIG. 3 is a schematic cross-sectional view showing each manufacturing process of the ferroelectric memory shown in FIGS. 1 and 2, up to a step of opening a contact hole for forming a storage node electrode.

FIG. 4 is a schematic cross-sectional view subsequent to FIG. 3, showing the steps up to the first step of forming a ferroelectric capacitor.

FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4 and shows up to a step of forming a plate line.

FIG. 6 is a schematic cross-sectional view subsequent to FIG. 5, showing the steps up to the step of bonding the semiconductor substrates.

FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6, showing a process up to the step of forming a transistor active region by polishing a silicon substrate.

FIG. 8 is a schematic cross-sectional view following FIG. 7, showing the steps up to the step of forming a transistor, a bit line, and a word line.

FIG. 9 is a schematic cross-sectional view following FIG. 8, showing the steps up to the step of forming a second ferroelectric capacitor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell, 2 ... Selection transistor, 3 ... Storage node electrode, 4 ... Plate electrode, 5 ... Plate line selection circuit,
10: silicon substrate, 10a: groove for element isolation, 10
b, 10c: active region of transistor, 11: first interlayer insulating layer, 12: etching stopper film, 13: sacrificial layer, 14: contact hole, 15: ferroelectric film, 16: second interlayer insulating layer, Reference Signs List 17 connection plug, 18 third interlayer insulating layer, 19 semiconductor substrate, 20 adhesive layer, 21 gate electrode, 22 source region, 23 drain region, 30
... PMOS forming a transfer gate, 31 NMOS forming a transfer gate, C ₀ , C _1, two ferroelectric capacitors, BL bit line, WL word line, PL plate voltage supply line, PL ₀ , PL ₁ plate line, TG ₀ , TG ₁ transfer gate, AND ₀ ,
AND ₁ ＡＮAND gate, INV ₀ , INV ₁イ ン バ ー タ inverter, APO プ レ ー ト plate line selection signal, / APO 反 転 inversion signal of plate line selection signal.

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[Procedure amendment]

[Submission date] February 14, 1997

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 H01L 29/78 371 29/29/788 29/792

Claims (5)

[Claims] 1. A selection transistor in which one of a source and a drain is connected to one of a pair of bit lines, and a storage node electrode is connected in parallel to the other side of the source or the drain of the selection transistor. And a plurality of ferroelectric capacitors capable of storing different stored data, a memory cell is formed, connected to plate electrodes of the plurality of ferroelectric capacitors, and input under a condition that a word line is excited. A semiconductor memory device having a ferroelectric capacitor having a plate line selection circuit for selectively connecting any one of a plurality of ferroelectric capacitors to a plate voltage supply line in response to a plate line selection signal. 2. The semiconductor memory according to claim 1, wherein the plurality of ferroelectric capacitors are spaced apart from each other in a direction perpendicular to a semiconductor substrate surface with the select transistor interposed therebetween. apparatus. 3. The semiconductor memory having the ferroelectric capacitor according to claim 2, wherein the select transistor and the plurality of ferroelectric capacitors are arranged so as to be embedded in a thick insulating layer on a semiconductor substrate. apparatus. 4. The ferroelectric capacitor is provided in a pair in a memory cell, the plate line selection circuit includes a word line connected to a first input terminal, and a plate line selection signal supplied to a second input terminal. An AND gate connected to a terminal; a first control connected between one plate electrode of the two ferroelectric capacitors and the plate voltage supply line, and an output of the AND gate connected to the gate; A second control that is connected between a gate and the other plate electrode and the plate voltage supply line, an output of the AND gate is connected to the gate via an inverter, and an inversion operation is performed on the first control gate; 2. A semiconductor memory device having the ferroelectric capacitor according to claim 1, comprising a gate. 5. The AND gate according to claim 1, wherein:
AN having an input terminal of the first AN and the second input terminal
The first AND gate has a second input terminal to which the plate line selection signal is input, and an output of the first AND gate, which is a transistor of the first control gate. The second AND gate has a second input terminal to which an inverted signal of the plate line selection signal is input, and an output of which is connected to the gate of a transistor constituting the second control gate by the inverter. And a transistor forming the first control gate is a first transistor.
And a transistor of the opposite conductivity type whose output is connected to the gate via an inverter, constitutes a first transmission gate, and the transistor constituting the second control gate is a second control gate.
5. The semiconductor memory device having a ferroelectric capacitor according to claim 4, wherein a second transmission gate is formed together with a transistor of an opposite conductivity type whose output of said AND gate is connected to the gate.