JPH0982949A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device having a small leak current and an operating speed higher than that in the case where a metal silicide layer or a metal layer is not formed on a source or a drain, and a manufacturing method thereof. According to the present invention, a metal silicide layer (13a) or a metal layer (13) is used as a source (15).
a) and a semiconductor device formed on the drain (15b), which has an offset layer (12) for offsetting an interface between the pn junction of the source and drain and the end of the metal silicide layer or the metal layer. A device is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a semiconductor device such as a MOS transistor and has a small leak current and a higher operation speed than a semiconductor device in which a metal silicide layer or a metal layer is not formed on a source or a drain. The present invention relates to a device and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a conventional technique for manufacturing a semiconductor device as described above, there is one disclosed in Japanese Patent Laid-Open No. 4-196442.

This is a technique for preventing an electrical short circuit between the source and drain and the gate electrode which is a problem when the salicide technique is used.

The cause of the above-mentioned short circuit is that the side wall film of the gate (referred to as a side wall spacer in the above publication) is damaged by the impurity ion implantation for forming the source and the drain.

As a result, the silicon in the silicon oxide film of the sidewall reacts with the metal, so that the silicon on the gate electrode surface and the source / drain surface, which is a feature of the salicide process, is metal silicide in self-alignment with the metal. The formation reaction occurs, and the unreacted metal on the side wall is selectively removed by the selective wet etching after that, so the metal remains on the side wall and the above source is removed. That is, a short circuit occurs between the drain and the gate.

Therefore, in the above-mentioned conventional technique, a certain amount is removed in order to remove the defective layer of the sidewall spacer formed by ion implantation, and then the sidewall is backfilled by the amount removed again, so that the wet process in the salicide process is performed. It is intended to improve the etching selectivity and prevent a short circuit between the source / drain and the gate.

[0007]

However, although the above-mentioned improvement is certainly expected to prevent the short circuit, in practice, the formation of a metal silicide layer or a metal layer on the surface of the source or drain causes the following problems. Exist essentially.

That is, pn in the source and drain
If the junction interface and the edge of the metal silicide layer or the metal layer are too close to each other, the leak current generated between the source and the drain increases, which is not practical.

In view of the above problems, the present invention provides an offset layer between the pn junction interface of the source and drain and the end of the metal silicide layer or the metal layer, and actively establishes an appropriate distance between them. It is an object of the present invention to provide a semiconductor device capable of suppressing the generation of a leak current between a source and a drain and a method for manufacturing the same by providing the semiconductor device.

This is expected to have a great effect as the device size becomes smaller.

[0011]

According to the present invention, in order to solve the above problems, in a semiconductor device in which a metal silicide layer or a metal layer is formed on a source and a drain, an end portion of the metal silicide layer or the metal layer is formed. There is provided a semiconductor device having an offset layer for offsetting an interface of a pn junction of a source and a drain.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized in that the offset layer is formed as an insulating layer on a gate sidewall portion in plural times.

Further, according to the present invention, in the above claim 1 or 2, the offset layer is formed by ion-implanting the impurities of the source and the drain into the gate sidewall at an inclined angle, and the metal silicide layer is also formed. Alternatively, there is provided a method of manufacturing a semiconductor device, wherein the metal layer is formed in self-alignment with the same gate sidewall.

That is, the features of the semiconductor device and the manufacturing method thereof according to the present invention are as follows.

(1) In order to separate the junction interface of the source / drain and the end of the metal silicide layer or the metal layer by an appropriate offset distance, the first sidewall that has already been formed on the side wall of the gate electrode is newly formed. A second sidewall spacer different from the spacer is formed as an offset layer, and then a metal silicide layer or a metal layer is formed.

(2) In order to separate the junction interface of the source / drain and the end of the metal silicide layer or the metal layer by an appropriate distance, ion implantation for forming the source / drain is performed on the first sidewall spacer. Is inclined at a predetermined angle with respect to the vertical direction of the substrate, and then a metal silicide layer and a metal layer are formed.

(3) In order to properly set the distance between the lower end of the metal silicide layer or the metal layer and the lower interface of the pn junction of the source and drain, the upper limit of the film thickness of the metal silicide layer or the metal layer is set. A metal silicide layer or a metal layer which is set and limits the leak current generated in the pn junction is formed.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment of a semiconductor device and a method of manufacturing the same according to the present invention is shown in FIGS.

The details will be described below in the order of manufacturing steps.

In this embodiment, a method for manufacturing a MOS type transistor will be described, and particularly a method for manufacturing an N channel transistor formed in a P type well region will be described.

A case where a metal silicide layer is formed on the source, the gate and the drain to reduce the resistance will be described.

First, as shown in FIG.
After a gate oxide film 17 is formed by a thermal oxidation method in a P-type well region 18 that is electrically isolated from other well regions by an S oxide film or a trench-type insulating layer, a polycrystalline silicon film to be a gate electrode is formed. 14 is formed by the LPCVD method or the like, and then heat-treated in a gas containing phosphorus to reduce the resistance.

Next, as shown in FIG. 1B, a polycrystalline silicon film 14 coated with a resist or the like is irradiated with ultraviolet rays or an electron beam, and then patterned into a desired pattern with a developing solution or the like. Patterning is performed by etching using an anisotropic dry etching method or the like.

Then, the resist is removed by a resist stripping solution or an O ₂ ashing method. Next, FIG. 1 (c)
As shown in FIG. 3, phosphorus or arsenic for forming the electric field relaxation layer 16 is ion-implanted.

Next, as shown in FIG. 1D, an insulating film such as an oxide film is formed by the CVD method or the like, and then the first side is formed on the side wall of the polycrystalline silicon gate electrode 14 by the anisotropic dry etching method. The wall spacer layer 11 is formed.

Next, as shown in FIG. 1E, the thermal oxide film 1
After forming 11, the phosphorus and arsenic ions for forming the source layer 15a and the drain layer 15b are ion-implanted.

In order to improve the film quality of the metal layer or metal silicide layer to be formed later, the crystal of the underlying silicon substrate is suppressed in this state by suppressing the three-dimensional distribution of the ion-implanted impurities by heat treatment for a short time as much as possible. It is more preferable to improve the property.

Next, as shown in FIG. 1F, in order to remove the damage layer on the surface of the sidewall spacer due to the above-mentioned ion implantation, the surface layer of the sidewall spacer is removed by an appropriate amount using hydrofluoric acid or the like. .

Note that this step can be omitted in the present invention.

Next, as shown in FIG. 2A, an insulating film such as an oxide film is formed by the CVD method or the like, and then the second sidewall spacer layer 12 is formed by the anisotropic dry etching method. An offset layer for reducing the leak current is used.

Next, as shown in FIG. 2B, a metal layer 13 is formed by a sputtering method, an electron beam evaporation method or the like.

Next, as shown in FIG. 2C, heat treatment is performed for a short time using the RTP method to change only the metal layer on the source, drain and gate surfaces to the metal silicide layer 13a.

Next, as shown in FIG. 2D, the unreacted metal layer 13b is selectively removed by wet etching using an aqueous solution of ammonia or hydrogen peroxide.

Then, the heat treatment is again performed for a short time using the RTP method to reduce the resistance of the metal silicide layer 13a.

Next, as shown in FIG. 2E, an insulating film such as an oxide film is formed by the CVD method or the like.

Finally, as shown in FIG. 2F, the wiring N-channel MOS type transistor is completed by applying the known wiring technique and passivation technique. FIG. 3 shows a second embodiment.

Also in the second embodiment, the N channel M is formed in the P well region as in the first embodiment described above.
The case of forming an OS transistor will be described.

A case where a metal silicide layer is formed on the source and drain will be described.

Also in the second embodiment, almost the same steps are applied to FIGS. 1A to 1D of the first embodiment to form the side wall spacers.

However, this time, the thickness in the lateral direction of the first sidewall spacer is set to a value in advance in order to optimize the distance between the pn junction interface of the source and drain and the end of the metal silicide layer or the metal layer. It needs to be slightly thicker than in the first embodiment.

Next, as shown in FIG. 3A, in order to set the pn junction interface of the source and drain to the lower part of the sidewall spacer 21, the source 25a and the drain 25b are inclined with an inclination angle with respect to the substrate vertical direction. Ion implantation of phosphorus or arsenic for forming is performed.

At this time, the substrate is preferably rotated about the vertical axis.

The setting value of the ion implantation angle at this time is set so that the distance from the end of the sidewall spacer to the pn junction interface of the source and drain is such that the leak current between the source and drain does not increase. There is a need to.

Next, as shown in FIG. 3B, the metal layer 2
3 is formed by a sputtering method, an electron beam evaporation method, or the like.

Thereafter, by applying the same steps as those in FIGS. 2C to 2F of the first embodiment, the N-channel MOS type shown in FIG. 3C is finally obtained. The transistor is completed.

FIG. 4 shows an essential part of the third embodiment.

In FIG. 4, 31 is a first side wall spacer, 32 is a second side wall spacer, and 3 is a side wall spacer.
3a is a metal layer or a metal silicide layer, 34 is a polycrystalline silicon gate electrode, 35b is a drain, 36 is an electric field relaxation layer, 37 is a gate oxide film, 38 is a P well region, 3
Reference numeral 9 is a wiring, 310 is a passivation film, and 312 is an insulating film.

The third embodiment basically applies the structure and the manufacturing method based on the structure of the semiconductor device and the manufacturing method thereof according to the first embodiment or the second embodiment. It is important that a proper distance be provided between the metal layer 33a or the lower end of the metal silicide layer 33a formed by heat-treating the metal layer 33a and the pn junction interface below the source / drain 35b as shown in FIG. By providing, the amount of leak current generated between the source and the drain 35b is suppressed.

Therefore, it is necessary to suppress the film thickness of the metal layer 33a before silicidation in order to realize the above distance.

For example, a titanium silicide film or a cobalt silicide film is formed by forming a titanium film or a cobalt film by a sputtering method or an electron beam vapor deposition method and heat-treating for a short time by the RTP method. , About 2.3 to 3.6 times the film thickness of the initial metal layer (that is, the titanium film or the cobalt film). Therefore, it is necessary to set the initial metal film thickness in consideration of this increase.

In FIG. 4, arrow A indicates the distance between the lower end of the metal silicide layer or the metal layer and the pn junction interface under the source and drain.

As described above, according to the first and second embodiments of the present invention, in the semiconductor device such as the MOS transistor having the metal silicide layer or the metal layer on the gate electrode and the source and drain regions, By providing an offset layer for maintaining an appropriate distance between the pn junction interface between the source and drain and the end of the metal silicide layer or the metal layer, the amount of leakage current generated between the source and drain is suppressed to a low level. There is a great effect that can be done.

According to the first embodiment, the source,
Since the damaged layer on the surface of the first sidewall spacer formed by the ion implantation for forming the drain is effectively covered with the second sidewall spacer layer, the method is disclosed in Japanese Patent Laid-Open No. Hei.
There is also an effect that the step of removing the damaged layer by etching, which is performed in Japanese Patent Laid-Open No. 196442, can be omitted.

[0055]

Therefore, as described in detail above, according to the present invention, an offset layer is provided between the pn junction interface of the source and drain and the end of the metal silicide layer or the metal layer, and an appropriate offset layer is provided between the two. By proactively providing such a distance, it is possible to provide a semiconductor device and a manufacturing method thereof capable of suppressing the generation of a leak current between the source and the drain.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment.

FIG. 3 is a sectional view showing a method of manufacturing a semiconductor device according to a second embodiment.

FIG. 4 is a sectional view of a semiconductor device formed by a manufacturing method based on a third embodiment.

[Explanation of symbols]

 11 ... 1st side wall spacer, 12 ... 2nd side wall spacer, 13 ... Metal layer, 13a ... Metal silicide layer, 13b ... Unreacted metal layer, 14 ... Polycrystalline silicon gate electrode, 15a ... Source, 15b ... Drain, 16 ... Electric field relaxation layer, 17 ... Gate oxide film, 18 ... P well region, 19 ... Wiring, 110 ... Passivation film, 111 ... Thermal oxide film, 112 ... Insulating film, 21 ... First sidewall spacer, 23 ... Metal layer, 23a ... Metal silicide layer, 24 ... Polycrystalline silicon gate electrode, 25a ... Source, 25b ... Drain, 26 ... Electric field relaxation layer, 27 ... Gate oxide film, 28 ... P well region, 29 ... Wiring, 210 ... passivation film, 211 ... thermal oxide film, 212 ... insulating film, 31 ... first sidewall spacer , 32 ... Second sidewall spacer, 33a ... Metal layer or metal silicide layer, 34 ... Polycrystalline silicon gate electrode, 35b ... Drain, 36 ... Electric field relaxation layer, 37 ... Gate oxide film, 38 ... P well region , 39 ... Wiring, 310 ... Passivation film, 312 ... Insulating film.

Claims (3)

[Claims] 1. A semiconductor device in which a metal silicide layer or a metal layer is formed on a source and a drain, having an offset layer for offsetting an interface between an end of the metal silicide layer or the metal layer and a pn junction of the source and the drain. A semiconductor device characterized by: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the offset layer is formed of an insulating layer on the side wall of the gate a plurality of times. 3. The offset layer according to claim 1 or 2, wherein the offset layer is formed by ion-implanting impurities of the source and drain into the gate sidewall at an inclined angle, and the metal silicide layer or metal layer is formed. A method of manufacturing a semiconductor device, wherein the same gate sidewall is formed in a self-aligned manner.