JPH09246490A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: To suppress the formation of a resistance layer or the like at the interface between an electrode and a dielectric film made of a metal oxide. An element isolation oxide film 2 is formed on a part of a p-type substrate 1, and an n ⁺ diffusion layer 3 (3a, 3b) is formed so as to be sandwiched between two element isolation oxide films 2. n ⁺ diffusion layer 3a
And 3b, a gate electrode 5 covered with a gate insulating film 4 is formed on the substrate 1. An interlayer insulating film 6a is formed on the gate insulating film 4 and the substrate 1. Bit line 7 connected to n ⁺ diffusion layer 3a is formed on interlayer insulating film 6a. Interlayer insulating film 6a and bit line 7
An interlayer insulating film 6b is formed on top. n ⁺ diffusion layer 3b
On the n ⁺ polycrystalline silicon 8 and the TiN film 9 on the Ru film.
The film 10 is formed. SrRu covering the Ru film 10
An O ₃ film 11 is formed, a SrTiO ₃ film 12 is formed on the O ₃ film 11, and a Ni film 13 is formed on a part of the SrTiO ₃ film 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a capacitor having a laminated structure of electrodes / metal oxides / electrodes and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor memory devices has been further increased and the area of one cell has been reduced year by year. As the cell area is reduced, the area allocated to the capacitor is naturally reduced, but the stored charge capacity of the capacitor required for one cell cannot be reduced so much in view of sensitivity and soft error.

In order to secure storage capacity, in recent years, attention has been paid to the use of a metal oxide having a high dielectric constant, which has not been heretofore, as the dielectric film. However, the metal oxide
Since the film formation temperature of 400 to 700 ° C. is required in the oxidizing atmosphere during film formation, the lower electrode material needs to be stable and not oxidized even under these circumstances.
Also, since a fine electrode pattern must be formed, the lower electrode material must be easily processed.
From the above points, attention is paid to a noble metal, particularly Ru or an oxide of Ru, as a material for the lower electrode.

FIG. 10 is a sectional view of a memory cell portion of a DRAM using a conventional Ru film as a lower electrode. 1 is a p-type silicon substrate, 2 is an element isolation oxide film, 3 (3a,
3b) is an n ⁺ diffusion layer, 4 is a gate insulating film, 5 is a gate electrode (word line), 6 (6a, 6b) is an interlayer insulating film, 7 is a bit line, 8 is n ⁺ polycrystalline silicon, and 9 is a diffusion layer. A TiN film which is a prevention film, 10 is a Ru film which is a lower electrode, 28 is a (Ba, Sr) TiO ₃ film which is a dielectric film, and 29 is a WN _x film which is an upper electrode.

However, in the above structure, the Ru film 1
The (Ba, Sr) TiO ₃ film 28 is formed on the oxide film 10 by the heat treatment process.
There is a problem that an oxide layer is formed at the interface with the iO ₃ film 28 or a problem that the morphology of the interface is deteriorated due to the structural change. In addition, (Ba, Sr) TiO
_{Since the 3} film 28 is a polycrystal, the (Ba, Sr) TiO ₃ film in contact with the Ru film 10 has a mismatch of lattice constants, and an interface layer with many lattice defects and interstitial atoms is formed, resulting in a large storage capacity. There is also the problem of deterioration.

In order to solve the above problem, a method of using a RuO ₂ film for the lower electrode instead of the Ru film can be considered.
However, RuO ₂ is a material that is extremely easily reduced and lacks thermal stability. On the other hand, the diffusion prevention film formed in contact with the RuO ₂ film (lower electrode) is a material that is easily oxidized.
There is a problem that the uO ₂ film is reduced by itself and the diffusion prevention film is oxidized to form a resistance layer. Also, the problem of lattice mismatch is not solved.

Another method is to use a conductive metal oxide film, for example, a SrRuO ₃ film as an electrode as a material having excellent thermal stability, but it is difficult to perform fine processing and is not suitable as a lower electrode.

[0008]

As described above, heat treatment at 400 ° C. to 700 ° C. in an oxidizing atmosphere is required to form a metal oxide as a dielectric film of a capacitor,
At the time of this heat treatment, a resistance layer or an interface layer having poor crystallinity is formed at the interface between the dielectric film and the electrode, so that there is a problem that the storage capacity is reduced.

An object of the present invention is to prevent the formation of a resistance layer or an interface layer having poor crystallinity at the interface between a metal oxide and an electrode, and to increase the storage capacity of a capacitor, and to manufacture the same. Is to provide a method.

[0010]

[Means for Solving the Problems]

(Structure) The semiconductor device and its manufacturing method of the present invention are structured as follows.

(1) A semiconductor device according to the present invention is a capacitor having a laminated structure of electrodes / metal oxides / electrodes formed on a semiconductor substrate, wherein at least one of the interfaces between the electrodes and the metal oxide is A conductive transition layer containing at least one of the constituent elements of the electrode and at least one of the constituent elements of the metal oxide is provided.

(2) The method of manufacturing a semiconductor device according to the present invention comprises:
A step of forming a first electrode on a semiconductor substrate; and a conductive material made of a material containing at least one of the constituent elements of the first electrode and at least one of the constituent elements of a metal oxide on the first electrode. Forming a transition layer, forming the metal oxide on the transition layer, and forming a second electrode on the metal oxide.

(3) At least one of the electrodes is Ru,
A compound containing a noble metal of Rh, Pd, Ag, Re, Os, Ir, Pt, Au or an oxide thereof, wherein the metal oxide is represented by the chemical formula αβO ₃ , and α is Ba, S
contains at least one of r, Pb, La, Li, K, and β
Is at least one of Zr, Sn, Ti, Ta, Nb, and the transition layer is represented by the chemical formula γ _x δ _x O _7-y ,
γ is Ba, Sr, Pb, La, Li, Zr, Sn, T
at least one of i, Ta, and Nb, δ is the noble metal that constitutes the electrode, and x is 1 or 2,
y is an integer from 0 to 4.

(4) In particular, the electrode is a Ru film, an Ir film,
It is a Re film or other precious metals.

(5) In particular, the transition layer is SrRuO.
ABO ₃ type compounds such as ₃ film and SrIrO ₃ film, or A ₂ B ₂ O _7-x type compounds such as Pb ₂ Re ₂ O _7-x .

(6) In particular, the metal oxide is (Ba, S
r) TiO ₃ film, SrTiO ₃ film, Pb (Zr, Ti)
O ₃ film, (Pb, La) (Zr, Ti) O ₃ film, Ba
(Ti, Sn) O ₃ film or the like.

(Operation) The dielectric film of the capacitor is set to (Ba,
In the case where the Sr) TiO ₃ film and the lower electrode are Ru films, (Ca, Sr) RuO ₃ and (Ba, S) are used as the transition layers including the metal oxide and the constituent elements of both layers of the electrode and having excellent thermal stability.
r) Conductive metal oxides containing Ru such as RuO ₃ and Sr ₂ Ru ₂ O ₄ are considered. Here, the action of SrRuO ₃ will be described as an example.

FIG. 11 is a diagram showing changes in weight of the SrRuO ₃ film in an oxidizing atmosphere and in vacuum. If SrRu
When O ₃ has a structural change such as release of constituent elements or bonding with multiple elements, the weight changes. SrRuO ₃ is stable in these atmospheres up to 1200 K, and no decrease in weight due to release of constituent elements or increase in weight due to reaction with oxygen molecules is observed. In Ru in a high-heat oxygen atmosphere, the surface is oxidized to become RuO ₂ and the surface morphology deteriorates. However, since SrRuO ₃ is thermally stable even in an oxidizing atmosphere, the surface morphology does not deteriorate.

FIG. 12 shows the relationship between the resistivity of SrRuO ₃ and the measurement temperature. The resistivity of the SrRuO ₃ film at room temperature is 350 μΩ · cm, and that of Ru is 15 μΩ · c.
It has a resistivity 20 times or more higher than that of m, but it can be seen that it has sufficiently low resistance as an electrode.

Further, the crystal lattice of SrRuO ₃ is (Ba _x
Sr _1-x ) TiO ₃ has the same perovskite structure with lattice constants of a = 0.556 nm and b = 0.555n.
m and c = 0.786 nm. In the state where the (100) plane is deviated by 45 °, the unit cell of SrRuO ₃ has (Ba
_It can be seen that the two lattices of the ( _x Sr _1-x ) TiO ₃ film overlap and have extremely close lattice constants. Therefore SrR
The (Ba _x Sr _1-x ) TiO ₃ film formed on the uO ₃ film has good crystallinity from the vicinity of its interface. FIG. 13 shows the crystallinity measured by the Rutherford publication scattering method.
It can be seen that good crystallinity is exhibited on the SrRuO ₃ film.

FIG. 14 shows the frequency dependence of the dielectric constant of the (Ba, Sr) TiO ₃ film formed on the SrRuO ₃ film. In FIG. 14, ● indicates the dielectric constant, and ○ indicates the dielectric loss characteristic tan δ. When the resistance layer is formed at the interface between the metal oxide and the electrode, it has frequency dependence and the dielectric constant decreases as the frequency increases. But SrRu
The (Ba, Sr) TiO ₃ film formed on the O ₃ film generally has a high dielectric constant, and the fall of the dielectric constant is 10% or less at 10 Hz to 10 ⁵ Hz, and the dielectric constant decreases with the increase of frequency. Also few. Therefore, the SrRuO ₃ film and (Ba, S
r) It can be said that the resistance layer is not formed at the interface with the TiO ₃ film.

As shown above, (Ba,
When forming a Sr) TiO ₃ film, SrR is used as a transition layer.
Since uO ₃ is inserted into the interface, it is thermally stable and does not form an interface resistance layer or an interface layer due to lattice mismatch, so that a high storage capacity can be achieved.

Further, in the dielectric film (metal oxide), oxygen vacancies tend to increase with time, which causes a decrease in dielectric constant and an increase in leak current. At this time, if there is a transition layer made of an oxide near the interface between the upper electrode and the lower electrode, oxygen diffuses from the oxide and oxygen vacancies can be compensated, so that the change over time can be reduced. A higher performance capacitor can be formed.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a sectional view of a memory cell portion of a DRAM according to a first embodiment of the present invention. An element isolation oxide film 2 is formed on a part of the p-type silicon substrate 1. A gate electrode (word line) 5 is formed on the substrate 1 via a gate insulating film 4. In the element formation region surrounded by the element isolation oxide film 2, n ⁺ diffusion layers 3 (3a, 3b) are formed on both sides with the gate electrode 5 interposed therebetween. A first interlayer insulating film 6a is formed on the substrate 1 and the gate electrode 5. An n ⁺ diffusion layer 3b is formed on the first interlayer insulating film 6a.
A bit line 7 connected to is formed. A second interlayer insulating film 6b is formed on the first interlayer insulating film 6a and the bit line 7.

The interlayer insulating film 6 (6a, 6a, on the n ⁺ diffusion layer 3a)
In the contact hole 6b), n ⁺ polycrystalline silicon 8 is formed at a height lower than the uppermost portion of the interlayer insulating film 6, and a TiN film 9 serving as a diffusion preventing film is formed thereon.
Then, a Ru film 10 serving as a lower electrode of the capacitor is formed on a part of the TiN film 9 and the interlayer insulating film 6b. A SrRuO ₃ film 11 serving as a transition layer covering the Ru film 10
Are formed. Then, on the SrRuO ₃ film 11 and the interlayer insulating film 6b, SrTiO 3 which becomes a dielectric film of a capacitor is formed.
_{The three} films 12 are formed, and the Ni film 13 which will be the upper electrode of the capacitor is formed on a part of this.

2 and 3 are process sectional views according to the present embodiment.

First, as shown in FIG. 2A, an element isolation oxide film 2 is formed in a region other than an element formation region on a p-type silicon substrate 1, and then a gate insulating film 4 of a transistor and a gate electrode (word line) are formed. ) 5, n ⁺ diffusion layer 3 (3a, 3b)
Is formed, and the first interlayer insulating film gap 6a is laminated on the entire surface.
Then, a contact hole is opened in the first interlayer insulating film 6a on the n ⁺ diffusion layer 3b, a bit line 7 connected to the n ⁺ diffusion layer 3b is formed on the interlayer insulating film 6a, and the second interlayer insulating film 6a is formed on the entire surface. The insulating film 6b is laminated. Next, a contact hole is opened in the interlayer insulating film 6 on the n ⁺ diffusion layer 3a, an n ⁺ polycrystalline silicon film 8 is deposited on the entire surface, the n ⁺ polycrystalline silicon 8 on the interlayer insulating film 6 is removed, and a contact is made. Embed in the hole.
At this time, the upper part of the n ⁺ polycrystalline silicon film 8 is formed to be slightly lower than the upper part of the second interlayer insulating film 6b.

Next, as shown in FIG. 2B, a TiN film 9 as a diffusion preventing film is deposited on the entire surface by a sputtering method using Ar gas, and the TiN film 9 on the second interlayer insulating film 6b is deposited. Is removed and the TiN film 9 is embedded in the contact hole.

Next, as shown in FIG.
The Ru film (lower electrode) 10 is deposited on the entire surface by a sputtering method using r gas, and is appropriately processed so that it is left only around the contact hole.

Next, as shown in FIG. 3D, the SrTiO ₃ film 1 is formed by a sputtering method using Ar gas containing oxygen gas.
4 is deposited to a film thickness of 5 nm.

Next, as shown in FIG. 3E, the Ru film 10 is heat-treated at 550 to 800 ° C. in an oxygen atmosphere.
The SrRuO ₃ film (transition layer) 11 is formed only on the surface of. Further, subsequently, a SrTiO ₃ film (dielectric film) 12 is deposited by a sputtering method using Ar gas containing oxygen gas, and heat treatment is performed at 500 to 800 ° C. in an atmosphere containing oxygen.

As shown in FIG. 3F, a Ni film (upper electrode) 13 is deposited on the entire surface by a sputtering method using Ar gas, and is appropriately processed.

In this embodiment, by providing the SrRuO ₃ film (transition layer) 11 at the interface between the Ru film (lower electrode) 10 and the SrTiO ₃ film (dielectric film) 12,
Since no resistance layer or lattice mismatch layer is formed at the interface between the Ru film 10 and the SrTiO ₃ film 12, a capacitor having a high dielectric constant can be formed.

(Second Embodiment) FIG. 4 is a sectional view of a memory cell portion of a DRAM according to a second embodiment of the present invention.
The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. This embodiment differs from the first embodiment in that the diffusion prevention film is the WN _x film 15, the lower electrode is the Ir film 16, the transition layer is the SrIrO ₃ film 17, and the dielectric film is (Ba , Sr) TiO ₃ film 18 and the upper electrode is a WN _x film 19.

5 and 6 show the DRA according to this embodiment.
It is a process sectional view of M.

First, since FIG. 5A is the same as the manufacturing process of FIG. 2A, description thereof will be omitted.

[0037] Next, as shown in FIG. 5 (b), depositing a WN _x film 15 on the entire surface by a sputtering method using Ar gas, the contact hole by removing the WN _x film 15 on the interlayer insulating film 6b Embed in

Next, as shown in FIG.
The Ir film 16 is deposited on the entire surface by a sputtering method in a r and is appropriately processed so as to remain on the WN _x film 15 and a part of the interlayer insulating film 6.

After that, as shown in FIG.
After thinly depositing Sr oxide by the MOCVD method using the organometallic compound of 550 to 550 in an atmosphere containing oxygen.
Only the surface of the Ir film 16 is heat-treated at 800 ° C. to form SrIr.
The O ₃ film 17 is formed. After that, by the MOCVD method using an organometallic compound of Ba, Sr, and Ti, (Ba,
The Sr) TiO ₃ film 18 is deposited and heat-treated at 550 to 700 ° C. in an atmosphere containing oxygen.

Then, as shown in FIG. 6E, a WN _x film 19 to be an upper electrode is further deposited on the (Ba, Sr) TiO ₃ film 18 and processed appropriately.

The present embodiment differs from the first embodiment in the method of forming the transition layer. In the first embodiment, S in Ar
It takes time because the deposition of the rTiO ₃ film is interrupted midway, moved to another processing chamber, and subjected to heat treatment to form the SrRuO ₃ film (transition layer). On the other hand, in this embodiment, Sr oxide is deposited and heat-treated to form SrIrO ₃ (transition layer), and heat-treated in the same growth chamber to form (Ba, Sr) T.
Since the iO ₃ film (dielectric film) 18 is formed, it does not take time.

(Third Embodiment) FIG. 7 is a sectional view of a DRAM of a memory cell portion according to a third embodiment of the present invention.
The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment differs from the other embodiments in that the dielectric film is sandwiched between two transition layers. The diffusion prevention film is made of the TaN film 20, and the lower electrode is the Re film 21.
And the transition layer sandwiched between the lower electrode and the dielectric film is Pb.
₂ Re ₂ O _7-x film 22, and the PbZrO ₃ film 23 is formed on the portion of the interlayer insulating film 6b where the transition layer is not formed.
And the dielectric film is a Pb (Zr, Ti) O ₃ film 24.
Made of Pb ₂ Re ₂ O which is a transition layer on the dielectric film.
_{The 7-x} film 25 and the Pb ₂ Re ₂ O _7-x film 26 are formed, and P
The Re film 27 of the upper electrode is formed on the b ₂ Re ₂ O _7-x film 25.

8 and 9 are process sectional views according to the present embodiment.

Since FIG. 8A is the same as the manufacturing process of FIG. 2A, its description is omitted.

Next, as shown in FIG. 8B, a TaN film 20 is deposited on the entire surface by a sputtering method in Ar, and the TaN film (diffusion prevention film) 20 on the interlayer insulating film 6b is removed. Embedded in the contact hole.

Subsequently, as shown in FIG. 8C, a Re film (lower electrode) 21 is deposited on the entire surface by MOCVD using an organometallic compound of Re as a raw material, and is appropriately processed.

Then, as shown in FIG. 9D, Pb,
A PbZrO ₃ film 23 is deposited to a thickness of 5 nm by MOCVD using each organometallic compound of Zr as a raw material.

Next, as shown in (e) of FIG.
After heat treatment at 800 ° C, Pb ₂ R is formed only on the surface of the Re film 21.
An e ₂ O _7-x film (transition layer) 22 is formed. Where Pb
The ZrO ₃ film 23 may be formed only at the interface with the Re film 21 or may be formed over the entire film thickness. In this case, a small amount of Zr may remain on the surface portion of the Pb ₂ Re ₂ O _7-x film 22 to be formed, but there is no problem.

Subsequently, Pb of the dielectric film is formed by the MOCVD method.
A (Zr, Ti) O ₃ film 24 is deposited. Furthermore, Pb (Z
A PbZrO ₃ film 26 is deposited on the entire upper surface of the r, Ti) O ₃ film 24 by the MOCVD method using an organic metal compound as a raw material.

Thereafter, as shown in FIG. 9F, a Re film 27 is deposited in the same manner as the Re film 21 of the lower electrode.
The Re film 27 is processed as the upper electrode, and then heat-treated at 550 to 800 ° C. in an atmosphere containing oxygen, and even at the upper electrode interface, Pb ₂ Re ₂ O
_{A 7-x} film (transition layer) 25 is formed.

The present embodiment is different from the other embodiments in that a transition layer is provided at the interface between the high dielectric film and the upper and lower electrodes. Even if the transition layer is provided only on the interface with the lower electrode, a sufficiently good interface can be formed, but by inserting the transition layer also with the upper electrode, the dielectric constant is higher and the resistance to deterioration is high. Capacitors can be formed.

The present invention also has the following modifications.

The capacitor structure and its manufacturing method of the present embodiment can be applied to semiconductor integrated circuits other than DRAM.

According to the present invention, a transition layer is formed by laminating a layer made of a metal oxide or an element constituting the metal oxide on an electrode material and applying a heat treatment in an inert gas (or vacuum atmosphere, oxygen atmosphere). It can be formed, or the transition layer may be laminated directly on the electrode.

Although n ⁺ polycrystalline silicon 8 is formed on the n ⁺ diffusion layer 3, the n ⁺ polycrystalline silicon 8 is replaced on the p ⁺ diffusion layer or on the n ⁺ diffusion layer having the diffusion barrier layer. Alternatively, p ⁺ polycrystalline silicon may be used.

As a lower electrode, a Ru film, an Ir film, and a Re film
Although the film is used, the present invention can be similarly applied by using other noble metals. The transition layer is SrRu.
O ₃ film, ABO ₃ type compound of SrIrO ₃ film, and P
Although the A ₂ B ₂ O _7-x type compound of b ₂ Re ₂ O _7-x was used, other combinations and compounds of other types can be similarly applied.

(Ba, Sr) TiO ₃ as a high dielectric film
A film, a SrTiO ₃ film, and Pb (Zr, Ti) O ₃ were used, but a (Pb, La) (Zr, Ti) O ₃ film, Ba
A ferroelectric material such as a (Ti, Sn) O ₃ film can be used to form the same, and the invention can be applied to a nonvolatile memory such as a FRAM as well as a DRAM.

As the upper electrode, a WN _x film, Ni
Although the film, the Ru film, and the Re film are used, the present invention can be implemented with other films.

When processing the upper electrode, the high dielectric film may be processed at the same time.

In the present invention, WN _x is used as the diffusion prevention film.
Although a film, a TiN film, and a TaN film were used, other metal nitride films,
A metal silicide film such as a WSi _x film or a TiSi ₂ film, a salicide film, or a nitride film of a metal silicide such as a WSi _x N _y film or a TiSi _x N _y film can be similarly formed. Further, the diffusion prevention film may be formed not only in the contact hole but around the contact hole.

In addition, various modifications can be made without departing from the scope of the present invention.

[0062]

According to the semiconductor device of the present invention, when a capacitor is formed, a transition layer which is thermally stable and has good lattice matching is formed between a dielectric made of a metal oxide and an electrode. As a result, the resistance layer is not formed by oxidation and the characteristic deterioration due to the deterioration of the morphology of the interface does not occur, so that the capacitor having a high storage capacity can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view of a DRAM according to a first embodiment.

2A to 2C are process cross-sectional views of the DRAM of FIG.

3A and 3B are process cross-sectional views of the DRAM of FIG.

FIG. 4 is a sectional view of a DRAM according to a second embodiment.

5A to 5C are process cross-sectional views of the DRAM of FIG.

6A and 6B are process cross-sectional views of the DRAM of FIG.

FIG. 7 is a sectional view of a DRAM according to a third embodiment.

FIG. 8 is a process cross-sectional view (1) of the DRAM of FIG.

9A and 9B are process cross-sectional views of the DRAM of FIG.

FIG. 10 is a sectional view of a conventional DRAM.

FIG. 11 is a diagram showing the weight of the SrRuO ₃ film depending on the temperature.

FIG. 12 is a diagram showing the resistivity of the SrRuO ₃ film depending on the temperature.

FIG. 13: SrRuO ₃ on (Ba, Sr) TiO ₃ film
The figure which shows the measurement result by the Rutherford backscattering method of a film.

FIG. 14: (Ba, Sr) TiO ₃ on SrRuO ₃ film
The figure which shows the dielectric constant by the frequency of a film | membrane.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p type silicon substrate 2 ... element isolation oxide film 3 ... n ⁺ diffusion layer 4 ... gate insulating film 5 ... gate electrode 6 ... interlayer insulating film 7 ... bit line 8 ... n ⁺ polycrystalline silicon 9 ... TiN film (diffusion prevention) Film ... 10 Ru film (lower electrode) 11 ... SrRuO ₃ film (transition layer) 12 ... SrTiO ₃ film (dielectric film) 13 ... Ni film (upper electrode) 14 ... SrTiO ₃ film 15 ... WN _x film (diffusion prevention) Film ... 16 ... Ir film (lower electrode) 17 ... SrIrO ₃ film (transition layer) 18 ... (Ba, Sr) TiO ₃ film (dielectric film) 19 ... WN _x film (upper electrode) 20 ... TaN film (diffusion prevention) Film ... 21 ... Re film (lower electrode) 22 ... Pb ₂ Re ₂ O _7-x film (transition layer) 23 ... PbZrO ₃ film 24 ... Pb (Zr, Ti) O ₃ film (dielectric film) 25 ... Pb ₂ Re ₂ O _7-x film (transition layer) 26 ... PbZrO ₃ film 27 ... Re film ( Upper electrode)

Claims (3)

[Claims] 1. A semiconductor device having a capacitor having a laminated structure of electrodes / metal oxides / electrodes formed on a semiconductor substrate, wherein a structure of the electrodes is provided on at least one of the interfaces between the electrodes and the metal oxides. A semiconductor device comprising a conductive transition layer containing at least one of the elements and at least one of the constituent elements of the metal oxide. 2. At least one of the electrodes is Ru, Rh,
A noble metal of Pd, Ag, Re, Os, Ir, Pt, Au or a compound containing an oxide thereof, wherein the metal oxide is represented by the chemical formula αβO ₃ , and α is Ba, Sr, P
contains at least one of b, La, Li and K, and β is Z
containing at least one of r, Sn, Ti, Ta, Nb,
The transition layer is represented by the chemical formula γ _x δ _x O _7-y , where γ is Ba, Sr, Pb, La, Li, Zr, Sn, Ti, T.
at least one of a and Nb, δ is the noble metal forming the electrode, x is 1 or 2, and y is 0.
2. The semiconductor device according to claim 1, wherein the semiconductor device is an integer from 1 to 4. 3. A step of forming a first electrode on a semiconductor substrate; and a material containing at least one constituent element of the electrode and at least one constituent element of a metal oxide on the first electrode. A step of forming a conductive transition layer of the following, a step of forming the metal oxide on the transition layer, and a step of forming a second electrode on the metal oxide. Device manufacturing method.