JPH09199630A - Multilayer wiring board - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] In a multilayer wiring board having a power supply wiring for electrolytic plating on the surface of an input / output terminal, such as an aluminum nitride package, a signal wiring by a power supply wiring in an open / branched state is provided. Minimize the reduction of the signal pass band. SOLUTION: A multilayer substrate 1 in which a plurality of insulating layers are integrated
First and second input / output terminals each having an electroplating layer on the surface are provided on both main surfaces of No. 1. In the multilayer substrate 11, there is provided a signal wiring 22 including an internal conductor layer formed on the internal insulating layer 11b, which electrically connects the first and second input / output terminals. Signal wiring 22
Means that the inner conductor layer is routed from one end portion corresponding to the first input / output terminal to a region outside the other end portion corresponding to itself and the second input / output terminal and then the other end portion. Signal lines 22c and 22d connected to the. Power supply wirings 23c and 23d for these signal lines 22c and 22d
Are drawn out from the middle of the signal line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board used as a semiconductor package or the like.

[0002]

2. Description of the Related Art A high-performance, highly-integrated LSI package has excellent heat dissipation, can handle high-speed signals, and can achieve a high wiring density, and can have a large number of input / output terminals and narrow terminals. Characteristics such as pitching are required. A ceramic package is known as a package that satisfies such required characteristics, and among them, an aluminum nitride package is expected as a highly heat-dissipating package that can be miniaturized. That is, as the performance and integration of semiconductor elements (chips) increase, the amount of heat generated from semiconductor elements tends to increase, and the number of input / output signals per element also tends to increase. In such a situation, the package using aluminum nitride, which is a highly heat-conductive material, can make its package size smaller by taking advantage of its excellent heat dissipation. This is because the use of aluminum nitride requires a smaller package size to satisfy the specifications of thermal resistance, as compared with the case of using a conventional ceramic material.

By reducing the package size, the package mounting area at the time of board mounting can be reduced, so that high-density mounting on the board becomes possible and the signal delay caused by shortening the internal signal wiring length is reduced. It is possible to expect a reduction in the number of packages that can be obtained from one lot of the same area, and it is possible to reduce the manufacturing cost of the packages.

By the way, in an aluminum nitride package, signal wiring is usually routed by using an internal conductor layer formed by simultaneous firing with an aluminum nitride multilayer substrate, and at least one of both main surfaces of the aluminum nitride multilayer substrate has the above-mentioned structure. An input / output terminal electrically connected to the inner conductor layer,
That is, a structure having an internal input / output terminal and an external input / output terminal is generally used. The internal input / output terminal serves as, for example, a connection terminal (electrode) with a semiconductor element, and is connected to the semiconductor element by wire bonding or bump electrode. Moreover, a pin or a solder is provided on the external input / output terminal. External terminals such as bumps are formed.

The input / output terminals in the aluminum nitride package as described above are mainly formed by co-firing with the aluminum nitride multilayer substrate similarly to the internal conductor layers, and are made of a refractory metal such as W or Mo. Therefore, since wire bonding or soldering cannot be performed as it is and corrosion may occur, the surface is usually plated with Ni or Au. Here, since electroless plating of aluminum nitride has not been put to practical use, Ni / Au plating or the like is usually performed on the input / output terminals by an electrolytic plating method that requires wiring for power feeding.

The above-mentioned power supply wiring for electrolytic plating is formed in the aluminum nitride multilayer substrate in the same manner as the internal wiring layer, and one end of the wiring is electrically connected to the internal wiring layer. The other end is pulled out to the outside of the final package shape. Therefore,
When the aluminum nitride multilayer substrate is cut into a package shape after the plating is completed, the outer peripheral side end portion of the power supply wiring exists on the side surface portion of the package in an open state. That is, the open branch is hung in the signal wiring. Thus, if the open branch hangs on the signal wiring in the package, there is a problem that the signal pass band of the signal wiring is reduced. this is,
This is a serious problem in the current situation where the operation speed of semiconductor elements is increased, that is, the operation frequency is increased.

[0007]

As described above, the aluminum nitride package is expected as a package that simultaneously satisfies the requirements of high heat dissipation, small size and light weight, high wiring density, low cost, etc. Since it is necessary to form a plating layer of Ni, Au, etc. on the input / output terminal surface by electrolytic plating, the power supply wiring hangs as an open branch on the signal wiring, and the signal pass band of the signal wiring decreases. It has the problem of being lost.

For this reason, in a multilayer wiring board having a power supply wiring for electrolytic plating on the surface of an input / output terminal, such as an aluminum nitride package,
Since it is unavoidable that the power supply wiring in the open-branch state hangs on the signal wiring, it is an object to suppress the reduction of the signal pass band of the signal wiring due to the power supply wiring as much as possible.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a multilayer wiring board capable of suppressing the deterioration of the signal pass band of the signal wiring due to the power feeding wiring as much as possible. I am trying.

[0010]

A multi-layer wiring board of the present invention is provided on at least one of both main surfaces of a multi-layer board in which a plurality of insulating layers are integrated, and an electroplating layer on the surface. The first and second input / output terminals having the first and second input / output terminals and the internal conductor layer formed on the internal insulating layer of the multilayer substrate, and the first input / output terminal and the second input / output terminal using the internal conductor layer. A signal wire for electrically connecting the output terminal and a power supply for electrically plating the signal wire and electrolytically plating at least one of the first input / output terminal and the second input / output terminal. A wiring for wiring, the signal wiring includes the first inner conductor layer,
From one end corresponding to the input / output terminal to a region outside the one end and the other end corresponding to the second input / output terminal and then connected to the other end. The power supply wiring for the signal line is drawn out from the middle of the signal line.

Here, in the internal conductor layer 2 formed on the internal insulating layer 1b of the conventional multilayer wiring board 1 as shown in FIG. 5, a first input line such as the first signal line A ₁ is used. When one end S _E1 corresponding to the output terminal 3 and the other end S _E2 located on the outer peripheral side of the multilayer wiring board 1 corresponding to the second input / output terminal 4 are connected, , Signal line length L _s
Is long, and the length L _b of the power supply wiring B ₁ is short. on the other hand,
Like the second signal line A ₂ , one end S _E1 ′ corresponding to the first input / output terminal 3 and the other located inside the multilayer wiring board 1 corresponding to the second input / output terminal 4. When the end portion S _E2 ′ of is connected, the signal line length L _s ′ becomes short,
On the contrary, the length L _b ′ of the power supply wiring B ₂ becomes long.

When there is no power supply wiring, the shorter the signal wiring, the better the signal passing characteristic of the signal wiring.
On the other hand, when there is an open-branch power supply wiring, it is preferable that the signal passage characteristic of the signal wiring has a short open branch length, and if the open branch becomes long, the signal passage characteristic deteriorates sharply. Comparing the effects of the signal wiring and the power supply wiring in the open-branch state on the signal passing characteristics, it can be seen that when the length of the power supply wiring in the open-branch state is longer than that in the case of lengthening the signal wiring. The effect is overwhelmingly large. Therefore, the signal pass band of the signal wiring in the multilayer wiring board is almost unaffected by the length of the signal wiring, and is determined by the length of the power supply wiring in the open branch state.

Therefore, in the multilayer wiring board of the present invention, when the length of the power supply wiring B ₂ becomes long, as in the case of the second signal line A ₂ in FIG. 5, such signal line (A ₂ ) as well as connected to one end of the (S _E1 'itself and the other end portion from) (S _E2') the other end after routing the region outside the (S _E2 '), with respect to the signal line The power supply wiring (B ₂ ) is pulled out from the middle. Therefore, although the signal line length that has almost no effect on the signal passing characteristic becomes long, it is possible to shorten the power supply wiring in the open-branch state that greatly affects the signal passing characteristic. This makes it possible to suppress a decrease in the signal pass band of the signal wiring.

[0014]

Embodiments of the present invention will be described below.

FIG. 1, FIG. 2 and FIG. 3 are views showing the structure of an embodiment in which the multilayer wiring board of the present invention is applied to a semiconductor package. FIG. 1 is an exploded perspective view showing the structure.
2 is a sectional view thereof, and FIG. 3 is an exploded plan view showing a ceramics layer portion on which an internal conductor layer is formed.

The semiconductor package shown in these figures is
A ceramics multilayer substrate 11 in which ceramics layers 11a, 11b, and 11c, which are insulating layers, are multilayer-integrated; inner layer wirings 12 provided in the ceramics multilayer substrate 11;
A first input / output terminal 13 electrically connected to the inner layer wiring 12 and provided on one main surface of the ceramic multilayer substrate 11 and a second input / output provided on the other main surface of the ceramic multilayer substrate 11. It is mainly composed of a ceramic multilayer wiring board 15 having terminals 14. The upper surface of the ceramic multilayer substrate 15 is a mounting surface of the semiconductor element 16.

The constituent material of the ceramic multilayer substrate 11 is not particularly limited, and various ceramic materials such as oxide ceramics such as aluminum oxide to non-oxide ceramics such as aluminum nitride and silicon nitride can be applied. However, it is particularly effective when using a ceramic material such as aluminum nitride for which electroless plating has not been put to practical use.

The inner layer wiring 12 is the ceramic multilayer substrate 1
It is composed of a filled conductor layer 17 filled in the through holes provided in each of the ceramic layers 11a to 11c and a printed conductor layer (internal conductor layer) 18 formed on the internal ceramic layer 11b. . The inner layer wiring 12 is formed in accordance with a desired signal wiring pattern and power feeding wiring pattern, and is electrically connected to the pad portions 19 and 20 formed on the front surface side of the ceramic multilayer substrate 11.

The above-mentioned filled conductor layer 17 and printed conductor layer 18
The pad portions 19 and 20 are both formed by co-firing with the ceramic multilayer substrate 11.
That is, first, through holes are formed in a ceramic green sheet corresponding to each of the ceramic layers 11a to 11c, and a conductive paste mainly containing a high melting point metal such as W or Mo is filled in the through holes, and at the same time, the printed conductor layer 1 is formed.
A conductor paste is printed on the ceramic green sheet according to the shapes of the pad 8 and the pad portions 19 and 20. After a plurality of such ceramic green sheets are laminated and pressure-bonded, the green sheet pressure-bonded body is degreased and fired, and the ceramic base material and the conductor are simultaneously sintered.

First and second input / output terminals 13, 14
Is formed by forming an electrolytic plating layer 21 such as a Ni plating layer or an Au plating layer by an electrolytic plating method on the pad portions 19 and 20 formed on the front surface side of the ceramic multilayer substrate 11. The first input / output terminal 13 functions as an electrical connection terminal with the semiconductor element 16, that is, an internal input / output terminal, while the second input / output terminal 14 has pins, bumps, or the like formed thereon. Functions as an external input / output terminal.

The above-mentioned inner layer wiring 12 is for supplying power for forming the electrolytic plating layer 21 on the portions functioning as the signal wiring 22 (signal lines 22a, 22b ...) And the pad portions 19, 20 by the electrolytic plating method. Wiring 23 (23a,
23b ...). The power supply wirings 23a, 23b ...
22b ... Are electrically connected to the outer peripheral side end portions of the ceramic multilayer substrate 11 in an open state, that is, an open branch state. Further, each signal line 22a, 22b ... And each power supply wiring 23
Each of a, 23b ... Is mainly routed by the printed conductor layer 18 formed on the internal ceramics layer 11b.

Here, among the signal wirings 22 described above, like the first and second signal wirings 22a and 22b, the power supply wiring 23a, to which the signal wiring length L _s of the printed conductor layer 18 is connected, longer than the length L _b of 23b (L _s>
L _b ), and the length L _{b of the} power supply wirings 23a and 23b
Is sufficiently short, the signal line 22a,
The signal pass characteristic of 22b, that is, the signal pass band is not significantly reduced. Therefore, as shown,
From the one end corresponding to the first input / output terminal 13 to the other end located on the outer peripheral side of the ceramic multilayer substrate 11 corresponding to the second input / output terminal 14, the signal line 22a by the printed conductor layer 18 is formed. , 22b are linearly formed. In addition, the power supply wirings 23a and 23b by the printed conductor layer 18
Is also linearly formed from the other end located on the outer peripheral side to the outer peripheral part of the ceramic multilayer substrate 11.

On the other hand, like the third signal line 22c shown enlarged in FIG. 4A, from one end S _E1 corresponding to the first input / output terminal 13 to the second input / output terminal 14. When it is assumed that the shortest distance L ₁ to the other end S _E2 located on the outer peripheral side of the corresponding ceramic multilayer substrate 11 forms the power supply wiring directly from the end S _E2 located on the outer peripheral side. _Is shorter than the shortest distance L ₂ from the end portion S _E2 located on the outer peripheral side to the outer peripheral portion of the ceramic multilayer substrate 11 (L ₁ <L ₂ ), the signal line and the power feeding wiring are If it is routed in the same manner as the second signal lines 22a and 22b, the power supply wiring in the open branch state becomes long.

Table 1 shows the first input / output terminal 1 of the signal line 22.
3, the distance (signal line length) L _s from one end corresponding to 3 to the other end corresponding to the second input / output terminal 14, and the length L of the power supply wiring 23 in the open branch state.
An example of the influence of _b on the frequency (cutoff frequency) at which the signal passing through the signal line 22 is attenuated by 3 dB is shown.

[0025]

[Table 1] Sample No. 1 and Sample No. 2 in Table 1, Sample No. 3 and Sample No. 4
As is clear from the comparison with the above, when the power supply wiring length L _b is the same, the cutoff frequency does not decrease so much even if the signal line length L _s is increased. On the other hand, as is clear from the comparison between Sample No. 2 and Sample No. 4, the cutoff frequency is significantly lowered when the power supply wiring length L _b is increased. In other words, even if the signal line length L _s is lengthened, if the feeding wire length L _b can be shortened, it is possible to prevent the cutoff frequency from decreasing. As described above, it is understood that the signal passing characteristic is almost determined by the length of the power supply wiring line L _b , and the influence of the signal line length L _s hardly appears.

As described above, in the semiconductor package which requires the power supply wiring 23 for electrolytic plating, the power supply wiring having a long signal passage characteristic is determined by the hanging signal line. This tendency is when the flip chip connection method for connecting the semiconductor chip and the package via the bump is applied, or when the external input / output terminals are arranged in a plane (lattice) matrix like PGA or BGA. Appears more prominently. In particular, the flip-chip connection and the BGA package are intended to improve the signal characteristics in the package, so that the reduction of the signal pass band due to the power supply wiring becomes a serious problem.

Therefore, as shown in an enlarged view in FIG. 4B, the printed conductor layer 18 in the signal line 22c is connected to one end S
It is formed so as to be connected to the other end S _E2 after than the other end portion S _E2 positioned on the outer peripheral side of itself and the ceramic multilayer substrate 11 from _E1 was routed outside the region. In addition, the power supply wiring 23c by the printed conductor layer 18 is
The signal line 22c is led out from the middle so that the distance from the signal line 22c to the outer peripheral portion of the ceramic multilayer substrate 11 becomes the shortest.

That is, the distance of the signal line 22c (actual distance from one end S _E1 to the other end S _E2 : signal line length) L _s is longer than the length L _b of the power supply wiring 23c ( L
_s > L _b ), the signal line length L _s that hardly affects the signal passing characteristics is lengthened, and conversely, the length L of the power supply wiring 23c in the open branch state that greatly affects the signal passing characteristics is increased. _b is shortened. This suppresses the reduction of the signal pass band of the signal wiring.

Also, like the fourth signal line 22d, the first signal line 22d
When one end portion corresponding to the input / output terminal 13 is located outside the other end portion corresponding to the second input / output terminal 14, the power supply wiring is directly directed from the end portion to the outer peripheral portion. When formed, the length of the power supply wiring becomes particularly long, so that the printed conductor layer 18 in the signal line 22d is connected to one end portion (the end portion located on the outer side / the end portion located outside) similarly to the third signal line 22c.
(Corresponding to the first input / output terminal 13) and is formed so as to be connected to the other end after being routed to a region outside itself, and from the middle of the signal line 22d to the power supply wiring 23d.
It is effective to bring out. Such a signal line 22d
The arrangement is such that the size of the semiconductor chip mounted in the package is increased and the number of inputs / outputs is increased, and the second input / output terminal (external input / output terminal) 14 is formed in the central part of the package due to the miniaturization of the package. It was created by the increased need.

Although only part of the signal wiring 22 is shown in FIGS. 1 to 3, the third and fourth signal lines 22c and 22 are shown.
In addition to d, the above-mentioned condition, that is, the shortest distance L ₁ from one end corresponding to the first input / output terminal 13 of the signal line to the other end corresponding to the second input / output terminal 14 is For the signal line shorter than the shortest distance L ₂ from the end portion located on the outer peripheral side to the outer peripheral portion of the ceramic multilayer substrate 11 (L ₁ <L ₂ ), the signal line and the power supply wiring have the routing shape as described above. As a result, the signal passing characteristic can be improved. In this case, it is desirable to set the power supply wiring to L _s > L _b for all the signal lines having the relationship of L ₁ <L ₂ described above, but this relationship is 5% of that of the signal lines having L ₁ <L _2. When applied to the above, the effect as a whole appears.

In the semiconductor package of the above-described embodiment, Ni is formed on the pad portions 19 and 20 formed on the surface side of the ceramic multilayer substrate 11 by using the power supply wiring 23.
An electrolytic plating layer 21 such as a plating layer or an Au plating layer is formed by an electrolytic plating method, and after the ceramic multilayer wiring board 15 is processed into a final shape, external terminals such as pins and bumps on the second input / output terminals 14 are formed. Formation, bonding and mounting of the semiconductor element 16, electrical connection between the electrode of the semiconductor element 16 and the first input / output terminal 13 (when mounting in the case of flip chip, mounting), the semiconductor element 16 by a ceramic cap or the like.
It is used as a PGA package, a BGA package, or the like after undergoing airtight sealing.

In such a semiconductor package,
Since the length L _b of the power supply wiring 23 is sufficiently short in the entire package, the signal pass band of the in-package signal wiring 22 can be satisfactorily guaranteed up to a high frequency region. Therefore, even when a semiconductor element having a high operating frequency is mounted, good operating characteristics can be obtained, and malfunctions can be stably prevented. In particular, in the package to which the flip chip connection is applied or the BGA package, the original effect of improving the signal characteristic in the package can be satisfactorily obtained.

Further, by using aluminum nitride ceramics for the ceramic multilayer substrate 11, while sufficiently satisfying the thermal reliability for the semiconductor element in which the amount of heat generation tends to increase, the package is downsized, the wiring density is increased,
It is possible to achieve cost reduction and the like. Then, it becomes possible to obtain a semiconductor package that satisfies these characteristics and has improved high-frequency signal transmission characteristics.

In the above embodiment, an example in which the multilayer wiring board of the present invention is applied to a ceramic multilayer wiring board for a semiconductor package has been described, but the present invention is not limited to these, and a multilayer circuit board for semiconductor mounting, MCM
It can be used as various multilayer circuit boards such as a multilayer circuit board for use. It is also possible to apply to a multilayer wiring board using an insulating material other than a ceramic material.

[0035]

As described above, according to the multilayer wiring board of the present invention, it is possible to suppress the deterioration of the signal pass band of the signal wiring due to the power supply wiring in the open branch state as much as possible. Therefore, for example, even when a semiconductor element or the like having a high operating frequency is mounted and mounted, it is possible to stably obtain good operating characteristics.

[Brief description of drawings]

FIG. 1 is an exploded perspective view showing a main part configuration of an embodiment in which a multilayer wiring board of the present invention is applied to a semiconductor package.

FIG. 2 is a cross-sectional view of the semiconductor package shown in FIG.

FIG. 3 is an exploded plan view showing a ceramics layer portion on which a printed conductor layer of the semiconductor package shown in FIG. 1 is formed.

FIG. 4 is an enlarged view showing a characteristic signal wiring and a power feeding wiring in the present invention.

FIG. 5 is a cross-sectional view showing a configuration of a conventional multilayer wiring board.

[Explanation of symbols]

 11 ... Ceramic multilayer substrate 11a, 11b, 11c ... Ceramic layer 12 ... Inner layer wiring 13 ... First input / output terminal 14 ... Second input / output terminal 15 ... Ceramic multilayer substrate 18 ... Printed conductor layer (Inner conductor layer) 21 ... Plating layer 22 ... Signal wiring 23 ... Power supply wiring

Claims (4)

[Claims] 1. A multi-layer substrate in which a plurality of insulating layers are integrated, and first and second input / output terminals provided on at least one of both main surfaces of the multi-layer substrate and having an electrolytic plating layer on the surface thereof. The first conductor includes an inner conductor layer formed on an inner insulating layer of the multilayer substrate, and uses the inner conductor layer.
A signal wire electrically connecting the input / output terminal and the second input / output terminal, and at least one of the first input / output terminal and the second input / output terminal electrically connected to the signal wire. In a multilayer wiring board comprising a power supply wiring for electroplating on one side, the signal wiring has one end from one end where the inner conductor layer corresponds to the first input / output terminal. And a signal line connected to the other end after being routed to a region outside the other end corresponding to the second input / output terminal, and the power supply wiring for the signal line is A multilayer wiring board, which is drawn out from the middle of the signal line. 2. The multilayer wiring board according to claim 1, wherein the shortest distance from the one end of the signal line to the other end is L ₁ , and the shortest distance is located outside the end of the signal line. When the shortest distance from the end portion to the outer peripheral portion of the multilayer substrate is L ₂ , L ₁ <L ₂ , and the distance from the one end portion to the other end portion is L _s , the signal multilayer wiring board characterized by having a signal line which is L _s> L _b when the length of the power supply wire drawn out from the line was L _b. 3. The multilayer wiring board according to claim ₂ , wherein among the signal lines satisfying L ₁ <L ₂ , at least 5% of signal lines correspond to L _s > L _b. And multilayer wiring board. 4. The multilayer wiring board according to claim 1, wherein the multilayer board is an aluminum nitride ceramic multilayer board.