JPH07193229A - Semiconductor device manufacturing process design method - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a process design method capable of compensating for fluctuations in electrical characteristics of a device that may occur due to process fluctuations by adjusting subsequent process conditions. In a process design for manufacturing an insulating gate type field effect transistor, step 4 of forming a gate electrode and then measuring the gate shape, and a threshold value obtained by a subsequent process condition. Step 2 of amplifying voltage fluctuations, Step 1 of obtaining a function that gives a process condition for obtaining a desired threshold voltage from the gate shape, and Step 1 of determining a subsequent process condition using the function. It has 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a designing method in a semiconductor manufacturing process, and more particularly, to compensating for fluctuations in electrical characteristics of a device which may be caused by fluctuations in the above-mentioned process by adjusting subsequent process conditions. And a semiconductor device manufacturing process designing method.

[0002]

2. Description of the Related Art In general, an integrated circuit using an insulator gate type field effect transistor (MOSFET) generally reduces the gate length of the MOSFET so that the drivability and responsiveness of the MOSFET can be improved. It is known to be effective in improving the performance of the above.

However, if the gate length of the above MOSFET is too short, a phenomenon called a short channel effect in which the threshold value is lowered occurs. Therefore, it is necessary to shorten the gate length in a range where the short channel effect is not remarkable. On the other hand, the gate length of the above MOSFET is also miniaturized due to the miniaturization of semiconductor elements due to recent semiconductor technological innovation. Therefore, the error in the gate length that occurs during the production of the semiconductor device becomes relatively large, the variation in the threshold voltage due to the short channel effect increases, and the yield decreases.

Therefore, in the conventional method of designing a semiconductor process, in order to obtain a stable semiconductor element, the semiconductor element is designed by such a method that the electrical characteristics such as the threshold value of the semiconductor element do not change with respect to the variation of process conditions. It had been.

[0005]

However, in the conventional method, along with the accelerated miniaturization in the progress of semiconductor devices, the variation of the electrical characteristics due to the variation of the specific process is unavoidable, and the above-mentioned electrical characteristics are somewhat reduced. It will cause a gap. On the other hand, as described above, the conventional process design method is designed so that the electrical characteristics of the semiconductor element do not change with process variations.

Therefore, it is very difficult to obtain the desired electrical characteristics by adjusting the subsequent process conditions from the electrical characteristics that are once deviated, and in some cases it becomes impossible to adjust. This has brought about a serious situation that the yield of the semiconductor element is lowered, the reliability is lowered, and further the accelerated miniaturization of the semiconductor element cannot be coped with in the future.

The present invention has been made in view of the above circumstances, and an object of the present invention is to adjust the subsequent process condition to the electrical characteristics by changing the electrical characteristics caused by the variation of the specific process. It is to provide a process design method capable of correcting characteristics.

[0008]

In order to achieve the above-mentioned object, the present invention provides a process for designing an insulating gate type field effect transistor, wherein a gate electrode is formed and then the gate is formed. Measuring the shape, amplifying the variation of the threshold voltage obtained by the subsequent process condition, and obtaining a function giving the process condition for obtaining the desired threshold voltage from the gate shape. And using the function to determine subsequent process conditions.

A peak having a concentration of ions to be implanted into the semiconductor substrate is located inside the semiconductor substrate, and the ions and ions having a polarity opposite to that of the ions are implanted so that the peak can be corrected with higher sensitivity. It is preferable to use steps. P-type impurities such as boron and indium are preferable as the ions. Further, as the ion having the opposite polarity to the above-mentioned ion, N-type impurities can be cited, and antimony and arsenic are preferable from the viewpoint that the diffusion rate in the heat treatment is slow and they are not easily affected by damage. Further, as the subsequent process, the annealing time and the annealing temperature are preferable from the viewpoint of process control.

[0010]

According to the above means, the electrical characteristics of the device are designed to be largely changed by the change of the subsequent process conditions. Therefore, it is easy to adjust the anneal time or the like which is the subsequent process condition. The electrical characteristics of the element can be corrected.

Further, after the completion of a certain process, the variation of the process is measured, and the subsequent process condition for obtaining a desired electrical characteristic with respect to the process variation is determined. Specifically, for example, after the gate electrode is formed, its length is measured and the anneal time for obtaining a desired threshold voltage for the gate length is determined.

From the above, it is possible to realize a significant improvement in yield by adjusting the fluctuation of the electrical characteristics of the element due to the above process conditions in a later step.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In this embodiment, an NMOSFET process design method will be described in particular along the NMOSFET manufacturing process. Further, as a subsequent process, an example of annealing time will be described.

Embodiment 1 FIG. 1 shows a flow chart of each step in a process design method which is an example of the present invention. Hereinafter, each step will be described corresponding to the reference numeral of the step in the drawing.

First, step 1 in FIG. 1 will be described.

Step 1 is a step of deriving an annealing time as a function of the gate electrode by simulation or the like.

First, in the course of the manufacturing process, a processing gate
Estimate the range in which the length varies. Next, for each gate length within the above range, an anneal time for obtaining a desired threshold voltage is derived in advance by a process device simulator, actual measurement, or the like.

Here, the function derived by the process device simulator is shown in FIG. Figure 3
Designate the gate length of the NMOSFET to be 0.5 [μm]
When the threshold value is 0.55 [Volts], the annealing time required to obtain this value is shown as a function of the processing gate length. In FIG. 3, for example, when the gate length of the NMOSFET is 0.5 [μm], in order to obtain the threshold value of 0.55 [Volts], an annealing time of 60 minutes is required.
Indicates that time is needed.

In the present embodiment, the process device simulator was used as a method for deriving the anneal time. However, if a device in which the gate length is actually changed is prototyped and the function is obtained, it is more effective. Highly accurate correction can be performed.

This is the end of the description of step 1.

Next, the step before step 2 in FIG. 1 (no reference numeral)
Will be described. This step is a well-known step of forming wells, element isolation, and the like. Where the NMOS
It is desirable that the well concentration for forming the FET is determined according to a normal integrated circuit design standard such as inter-well breakdown voltage and latch-up resistance. The well concentration was set to 3 × 10 ¹⁶ [cm ^-3 ] in this embodiment.

This is the end of the description of the step before Step 2.

Next, step 2 in FIG. 1 will be described.

Step 2 is a step of implanting P-type ions such as boron into the channel region in order to make it easier to correct the threshold voltage of the wafer that has been subjected to the preceding steps by the annealing time.

FIG. 2 shows the boron concentration distribution in the channel region in the depth direction. As shown in FIG. 2, the peak position of the boron concentration immediately after the ion implantation is deepened and the surface concentration is designed to be low, so that the boron near the substrate surface is adjusted by adjusting the annealing time. Since the degree of freedom in changing the concentration can be improved, it becomes possible to increase the width in which the threshold voltage can be corrected.

Although boron is used as the impurity of the channel region in the above example, indium (In), which is the same P-type impurity as boron, may be used.

This is the end of the description of step 2.

Next, step 6 in FIG. 1 will be described.

Step 6 is a well-known step of forming a gate electrode, and a gate oxide film is formed on the surface of the wafer which has undergone the above-mentioned step 2. Next, polysilicon is deposited and the polysilicon is doped to form a gate electrode.

This is the end of the description of step 6.

Next, step 4 in FIG. 1 will be described.

Step 4 is a step of measuring the length of the gate electrode in the wafer.

First, a gate electrode is formed on the wafer having undergone the above-mentioned step 6 by using directional edging. Next, using a size scanning microscope (size SEM), etc.,
By measuring the average length of the gate electrode, the length of the gate electrode is obtained.

This is the end of the description of step 4.

Next, step 5 in FIG. 1 will be described.

Step 5 is a step of determining the anneal time from the gate electrode length using the derived function.

The anneal time can be calculated by using the gate electrode length measured in the step 4 and the function derived in the step 1. In the next step, the annealing step is carried out according to the annealing time calculated in this step.

The annealing process was performed in a nitrogen atmosphere.

This is the end of the description of step 5.

Although the description of each step is completed above, the NMOSFET is described in the above embodiment, but the same method can be applied to the PMOSFET or the CMOSFET. Further, although the threshold voltage is corrected in the nitrogen atmosphere in the above embodiment, the atmosphere may be oxidizing.

Example 2 In Example 2, in the step of implanting boron ions in Step 2 in Example 1, the step 3 for effectively expanding the correction range of the threshold voltage in Example 1 was adopted. It was replaced. The description of the steps described in the first embodiment will be omitted, and here, particularly, step 3 will be described.

In general, impurity diffusion is modulated by damage, which is damage to the crystal structure of the substrate material due to ion implantation. Further, the ion implantation into the channel region is low.
Since it is performed with a small amount, the influence of damage due to the ion implantation is small.

However, the ion implantation into the source / drain region is performed with a high dose amount in order to improve the driving force of the device. Therefore, in the case of the short channel MOSFET, the impurity diffusion in the channel region may be significantly affected. Due to the damage, the boron diffusion is accelerated, and rapid diffusion occurs at the initial stage of diffusion, so that the range of the threshold voltage that can be corrected is narrowed by changing the annealing time. That is, the range of the processing gate length that can be relieved by changing the annealing time is narrowed.

Therefore, in order to widen the range of the threshold value that can be corrected by the annealing time, diffusion by antimony of the conductivity type opposite to boron is used. The antimony diffusion has a small diffusion rate in heat treatment, is less susceptible to the effects of damage due to ion implantation, and has a polarity opposite to that of boron. Therefore, for example, as shown in FIG. 4, boron (P type) is used. By combining with antimony (N type) diffusion,
It can be made wider than the correction range of the threshold voltage of only boron. That is, in FIG. 4, antimony has a low diffusion rate and is less affected by damage in ion implantation.
Moreover, since the antimony distribution has a peak near the substrate surface, the electrical difference between the boron (P-type) concentration and the antimony (N-type) concentration near the substrate surface is the correction range due to the change in annealing time. It turns out that. Therefore, by adding antimony, the range of the threshold voltage that can be corrected by the annealing time can be expanded.

Although antimony is used in this embodiment, arsenic can also be used because it is not easily affected by damage.

[0047]

As described above, according to the present invention, even if there is a process variation, the process variation amount is measured,
By controlling the subsequent process accordingly, it is possible to easily correct the variation in the electrical characteristics and obtain the stable electrical characteristics. As described above, the quality of the integrated circuit can be improved, and the yield can be significantly improved.

[Brief description of drawings]

FIG. 1 is a process flow diagram of an embodiment according to the present invention.

FIG. 2 is a boron concentration distribution diagram in the depth direction in the channel region according to the present invention.

FIG. 3 is a diagram giving the annealing time according to the present invention as a function of the processed gate length.

FIG. 4 is a concentration distribution diagram of boron and antimony in the depth direction in the channel region of the second embodiment according to the present invention.

[Explanation of symbols]

1. A step of deriving an annealing time as a function of a gate electrode by simulation or the like. 2. A step of facilitating the correction of the threshold voltage by the annealing time in the step of implanting boron or the like. 3 A step of widening the correction range of the threshold voltage in the step of implanting boron or the like. 4 Step of measuring the length of the gate electrode in the wafer. 5 A step of determining the anneal time from the gate electrode length measured in step 4, using the function derived from step 1. (6) A step of forming a gate oxide film, depositing polysilicon to be a gate electrode, and doping the polysilicon.

Claims (3)

[Claims] 1. A process design for manufacturing an insulating gate type field effect transistor, comprising the steps of forming a gate electrode and then measuring the gate shape, and a threshold obtained by the subsequent process conditions. Amplifying the fluctuation of the value voltage, obtaining a function that gives a process condition for obtaining a desired threshold voltage from the gate shape, and determining a subsequent process condition using the function. Method for designing semiconductor device manufacturing process having. 2. The step of amplifying the fluctuation of the threshold voltage is a step of arranging a peak of a concentration of ions to be implanted in the semiconductor substrate inside the semiconductor substrate. A method for designing a semiconductor device manufacturing process as described. 3. In the step of locating a peak having a concentration of ions to be implanted into the semiconductor substrate inside the semiconductor substrate, the ions and ions having a polarity opposite to the ions are implanted. The semiconductor device manufacturing process design method according to claim 2.