JPH07183304A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH07183304A JPH07183304A JP5323489A JP32348993A JPH07183304A JP H07183304 A JPH07183304 A JP H07183304A JP 5323489 A JP5323489 A JP 5323489A JP 32348993 A JP32348993 A JP 32348993A JP H07183304 A JPH07183304 A JP H07183304A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor chip
- pads
- pad
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
- H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
- H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/856—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 工程が少なくしかもメッキ金属であれば任意
の金属からなるパッドを使用することが可能な半導体装
置の製造方法を提供する。
【構成】 複数のパッドを有する半導体チップと複数の
パッドを有する回路基板とをそれらのパッドが互いに対
向するように所望の間隔をあけて位置合わせすると共に
接着剤などを用いて前記半導体チップの中央部と前記回
路基板を接着固定する工程と、互いに接着固定された前
記半導体チップ及び前記回路基板をメッキ液の中に入
れ、電気メッキにより前記半導体チップのパッドと前記
回路基板のパッドとの間に金属を析出してそれらのパッ
ド間を電気的、機械的に接合する金属バンプを形成する
工程とを具備したことを特徴とする。
(57) [Summary] [Object] To provide a method for manufacturing a semiconductor device, which has a small number of steps and can use a pad made of any metal as long as it is a plated metal. A semiconductor chip having a plurality of pads and a circuit board having a plurality of pads are aligned with a desired gap so that the pads face each other, and an adhesive or the like is used to center the semiconductor chip. Section and the circuit board are bonded and fixed, and the semiconductor chip and the circuit board that are bonded and fixed to each other are placed in a plating solution, and electroplated between the pad of the semiconductor chip and the pad of the circuit board. And a step of depositing metal to form metal bumps for electrically and mechanically joining the pads.
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に所要の配線を有する回路基板のパットにバ
ンプを介して半導体チップをフェースダウンで実装する
半導体装置の製造方法に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a semiconductor chip is mounted face down on a pad of a circuit board having required wiring via bumps.
【0002】[0002]
【従来の技術】電子機器の高速・高密度に対応する技術
として、ベアチップを用いる方法が最近多く開発されて
いる。これらの方法は、具体的にはワイヤーボンディン
グ法、TAB法、フリップチップ法などがある。2. Description of the Related Art Recently, many methods using bare chips have been developed as a technology to cope with high speed and high density of electronic devices. Specific examples of these methods include a wire bonding method, a TAB method, and a flip chip method.
【0003】前記ワイヤーボンディング法は、半導体チ
ップをフェースアップに置き、チップのパッドと回路基
板上のパッドとを金などのワイヤーによって接続する方
法である。しかしながら、前記ワイヤーボンディング法
では50μmのように非常に小さいピッチのパッド間を
接続することは現状では困難であり、高密度化に不向き
である。The wire bonding method is a method in which a semiconductor chip is placed face up and pads of the chip and pads on a circuit board are connected by wires such as gold. However, with the wire bonding method, it is currently difficult to connect between pads having a very small pitch of 50 μm, and it is not suitable for high density.
【0004】前記TAB法は、ポリイミドフィルム上に
銅箔で配線を作り、半導体チップのパッドと銅箔のリー
ドとをバンプを介して接続する方法である。しかしなが
ら、前記TAB法は高価なポリイミドフィルムを使用す
ること、微細接続に対して前記フィルムが熱収縮するた
めに高い寸法精度が得られないという問題を有してい
た。The TAB method is a method in which wiring is made of a copper foil on a polyimide film and pads of a semiconductor chip and leads of the copper foil are connected via bumps. However, the TAB method has problems that an expensive polyimide film is used and that the film is thermally shrunk with respect to a fine connection, so that high dimensional accuracy cannot be obtained.
【0005】これに対し、前記フリップチップ法は半導
体チップのパッドに金属バンプを蒸着法,ディップ法,
メッキ法などで形成し、回路基板表面のパッドと位置合
わせして接続する方法である。このようなフリップチッ
プ法による半導体装置の製造方法を図6を参照して以下
に説明する。半導体チップ31の窒化シリコンなどのパ
ッシベーション膜32で一部が覆われたアルミニウムパ
ッド33上にCu,Ni,Cr,Tiやこれらの複合膜
などの金属膜を蒸着法などにより形成した後、パターニ
ングしてバリアメタル34を形成する。つづいて、前記
バリアメタル34上に半田などの金属バンプ35を蒸着
法、メッキ法などにより形成する。次いで、半導体チッ
プ31のバンプ35に回路基板36のパッド37を位置
合わせし、前記バンプ35と前記回路基板のパッド37
を加圧加熱することにより接合して半導体装置を製造す
る。On the other hand, in the flip chip method, metal bumps are deposited on the pads of the semiconductor chip by the vapor deposition method, the dip method,
It is a method of forming by a plating method, etc., and aligning and connecting with a pad on the surface of the circuit board. A method of manufacturing a semiconductor device by such a flip chip method will be described below with reference to FIG. A metal film such as Cu, Ni, Cr, Ti or a composite film of these is formed on the aluminum pad 33, which is partially covered with the passivation film 32 such as silicon nitride of the semiconductor chip 31, by a vapor deposition method or the like, and then patterned. To form the barrier metal 34. Subsequently, metal bumps 35 such as solder are formed on the barrier metal 34 by vapor deposition, plating or the like. Next, the pads 37 of the circuit board 36 are aligned with the bumps 35 of the semiconductor chip 31, and the bumps 35 and the pads 37 of the circuit board are aligned.
Are heated and joined to manufacture a semiconductor device.
【0006】前記フリップチップ法は、ワイヤーボンデ
ィング法,TAB法などと比べて半導体チップの全面を
利用して接続を行えること、バンプによって接続を行う
ため非常に微細なピッチの接合もできることなどによ
り、高密度実装が可能になり電子機器の小型化がはかれ
る。また、半導体チップと回路基板が金属バンプで直接
接続されているため、ワイヤやテープのような余分な配
線が不要になり、信号伝達遅延が低減できるので電子機
器の高速化を図ることができる。Compared with the wire bonding method, the TAB method, etc., the flip chip method is capable of utilizing the entire surface of the semiconductor chip for connection, and because the connection is made by bumps, it is possible to perform bonding at a very fine pitch. High-density mounting is possible and electronic devices can be downsized. In addition, since the semiconductor chip and the circuit board are directly connected by the metal bumps, extra wiring such as wires and tapes is not required, and the signal transmission delay can be reduced, so that the speed of the electronic device can be increased.
【0007】しかしながら、上述した従来のフリップチ
ップ法は以下のような欠点を有していた。 (1)半導体チップ上にバリアメタルを形成する必要が
あり、工程が増える。However, the above-mentioned conventional flip-chip method has the following drawbacks. (1) It is necessary to form a barrier metal on the semiconductor chip, which increases the number of steps.
【0008】(2)バンプ形成や、接合工程において熱
処理が必要であり信頼性に問題がある。 (3)接続に用いる金属はSn,Pb,In,Bi,A
u、Ag、Sbやこれらの化合物であり柔らかい金属に
限定される。(2) There is a problem in reliability because heat treatment is required in the bump forming and joining steps. (3) Metals used for connection are Sn, Pb, In, Bi, A
u, Ag, Sb and their compounds are limited to soft metals.
【0009】[0009]
【発明が解決しようとする課題】上述したように、従来
のフリップチップ法には工程が多く、接続に用いる金属
も限定されており、簡便でかつ応用範囲の広い半導体装
置は得られていない。本発明は、上記事情を考慮してな
されたもので、工程が少なくしかもメッキ金属であれば
任意の金属からなるパッドを使用することが可能な半導
体装置の製造方法を提供しようとするものである。As described above, the conventional flip-chip method has many steps and the metal used for connection is limited, so that a simple and versatile semiconductor device has not been obtained. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method of manufacturing a semiconductor device which has a small number of steps and can use a pad made of any metal as long as it is a plated metal. .
【0010】[0010]
【課題を解決するための手段】本発明は、複数のパッド
を有する半導体チップと複数のパッドを有する回路基板
とをそれらのパッドが互いに対向するように所望の間隔
をあけて位置合わせすると共に接着剤などを用いて例え
ば前記半導体チップの中央部と前記回路基板を接着固定
する工程と、互いに接着固定された前記半導体チップ及
び前記回路基板をメッキ液の中に入れ、電気メッキによ
り前記半導体チップのパッドと前記回路基板のパッドと
の間に金属を析出してそれらのパッド間を電気的、さら
には機械的に接合する金属バンプを形成する工程とを具
備したことを特徴とする半導体装置の製造方法である。SUMMARY OF THE INVENTION According to the present invention, a semiconductor chip having a plurality of pads and a circuit board having a plurality of pads are aligned and bonded at desired intervals such that the pads face each other. For example, a step of adhering and fixing the central portion of the semiconductor chip and the circuit board using an agent and the like, and placing the semiconductor chip and the circuit board that are adhered and fixed to each other in a plating solution, and electroplating the semiconductor chip A step of depositing a metal between the pad and the pad of the circuit board to form a metal bump that electrically and mechanically joins the pad to each other. Is the way.
【0011】前記半導体チップのパッドは、例えばアル
ミニウムまたはその合金等から形成される。前記回路基
板のパッドは、例えば銅またはその合金等により形成さ
れる。The pads of the semiconductor chip are formed of, for example, aluminum or its alloy. The pads of the circuit board are formed of, for example, copper or an alloy thereof.
【0012】前記接着剤としては、例えばエポキシ系接
着剤、アクリル系接着剤等を用いることができる。前記
メッキ金属としては、例えば銅,ニッケル,アルミニウ
ム,金,銀,錫,鉛,鉄,チタン,クロム,ビスマス,
インジウム、アンチモンやこれらの合金を用いることが
できる。As the adhesive, for example, an epoxy adhesive, an acrylic adhesive or the like can be used. Examples of the plating metal include copper, nickel, aluminum, gold, silver, tin, lead, iron, titanium, chromium, bismuth,
Indium, antimony and alloys of these can be used.
【0013】前記電気メッキにより前記半導体チップの
パッドと前記回路基板のパッドとの間に金属を析出する
手段としては、例えば前記回路基板に全てのパッドと接
続する共通配線を形成し、この共通配線を通して前記各
パッドに電圧を印加することにより前記回路基板のパッ
ドに金属を析出し、前記半導体チップのパッドと電気
的、機械的接合する金属バンプを形成方法を採用するこ
とができる。ただし、前記メッキ工程後は前記共通配線
をエッチング等により除去して前記パッドを互いに電気
的に分離する。その他の手段としては、前記パッドに近
似した形状の導体部を複数有する共通電極を互いに接着
剤で接着固定された前記半導体チップのパッドと前記回
路基板のパッドの間に前記導体部が前記パッドに対向す
るように配置し、前記共通電極に通電して前記導体部の
表裏面から金属を析出して前記半導体チップのパッドと
前記回路基板のパッドとを電気的、機械的接合する金属
バンプを形成方法を採用することができる。この場合、
前記バンプの形成後に前記各導体部を共通電極から電気
的に分離させる。As means for depositing metal between the pads of the semiconductor chip and the pads of the circuit board by the electroplating, for example, a common wiring connecting all pads is formed on the circuit board, and the common wiring is formed. It is possible to employ a method of forming a metal bump that deposits a metal on the pad of the circuit board by applying a voltage to each pad through the pad and electrically and mechanically bonds to the pad of the semiconductor chip. However, after the plating step, the common wiring is removed by etching or the like to electrically separate the pads from each other. As another means, the conductor part is provided between the pad of the semiconductor chip and the pad of the circuit board in which a common electrode having a plurality of conductor parts having a shape similar to the pad is fixed to each other with an adhesive. Metal bumps that are arranged so as to face each other are formed by electrically energizing the common electrode to deposit metal from the front and back surfaces of the conductor portion to electrically and mechanically bond the pad of the semiconductor chip and the pad of the circuit board. The method can be adopted. in this case,
After forming the bumps, the conductors are electrically separated from the common electrode.
【0014】[0014]
【作用】本発明によれば、複数のパッドを有する半導体
チップと複数のパッドを有する回路基板とをそれらのパ
ッドが互いに対向するように所望の間隔をあけて位置合
わせすると共に接着剤などを用いて前記半導体チップの
中央部と前記回路基板を接着固定し、前記半導体チップ
及び前記回路基板をメッキ液の中に入れ、電気メッキを
行うことにより前記半導体チップのパッドと前記回路基
板のパッドとの間に金属を析出してそれらのパッド間を
電気的、機械的接合する金属バンプを形成できる。つま
り、バンプ形成工程と前記半導体チップと回路基板のパ
ッド間の接合工程とを同時に行なうことができる。その
結果、従来のようにバリアメタルを前記半導体チップの
パッドとバンプの間に配置することが不要になり、しか
も金属バンプを溶融する目的で加熱処理する工程も省略
できる。ただし、前記バンプの性質に応じてバリアメタ
ルを用いて金属の拡散を防止することも許容する。ま
た、半導体チップと回路基板を予め樹脂で接続させてお
くためバンプのみで接続する場合に比べてそれらの接続
強度を向上することができる。したがって、プロセスの
簡略化を図ることができると共に信頼性の高い半導体装
置を製造できる。According to the present invention, a semiconductor chip having a plurality of pads and a circuit board having a plurality of pads are aligned at desired intervals so that the pads face each other, and an adhesive or the like is used. Adhesively fix the central portion of the semiconductor chip and the circuit board together, place the semiconductor chip and the circuit board in a plating solution, and perform electroplating to form a pad of the semiconductor chip and a pad of the circuit board. A metal bump can be formed by depositing a metal in between to electrically and mechanically bond the pads. That is, the bump forming step and the bonding step between the semiconductor chip and the pad of the circuit board can be simultaneously performed. As a result, it becomes unnecessary to dispose the barrier metal between the pad and the bump of the semiconductor chip as in the conventional case, and the heat treatment step for melting the metal bump can be omitted. However, it is also permissible to prevent the diffusion of metal by using a barrier metal depending on the nature of the bump. Further, since the semiconductor chip and the circuit board are connected in advance with resin, the connection strength between them can be improved as compared with the case of connecting only with the bumps. Therefore, the process can be simplified and a highly reliable semiconductor device can be manufactured.
【0015】また、前記電気メッキ工程において半導体
チップの例えばアルミニウムからなるパッド表面や回路
基板の例えば銅からなるパッド表面の酸化膜を除去でき
るため、半導体チップや回路基板のパッドと金属バンプ
を低抵抗接続することができる。In the electroplating step, the oxide film on the surface of the pad of the semiconductor chip made of aluminum or the surface of the pad of the circuit board made of copper, for example, can be removed. Can be connected.
【0016】さらに、前記半導体チップのパッドと前記
回路基板のパッドとを電気メッキにより形成した金属バ
ンプにより接合したとき印加する電圧が変化する場合に
は、その接合が完了したことを検知することができる。Further, when the applied voltage changes when the pads of the semiconductor chip and the pads of the circuit board are joined by metal bumps formed by electroplating, it can be detected that the joining is completed. it can.
【0017】さらに、電気メッキ法によって成長させる
金属バンプは、錫,鉛,ビスマス,インジウム,金,
銀,アンチモンなどの比較的柔らかい金属のみならず、
銅,ニッケル,アルミニウム,鉄,チタン,クロムなど
の硬い金属でも可能であるため、半導体装置の用途や性
能に応じてバンプ材料の選択できる利点を有する。その
他、前記回路基板のパッドを選択的に電気メッキの陰極
とすれば、前記回路基板と半導体チップの必要なパッド
部分のみの接続を図ることも可能である。Further, the metal bumps grown by the electroplating method include tin, lead, bismuth, indium, gold,
Not only relatively soft metals such as silver and antimony,
Since a hard metal such as copper, nickel, aluminum, iron, titanium, and chromium can be used, there is an advantage that the bump material can be selected according to the application and performance of the semiconductor device. In addition, if the pads of the circuit board are selectively used as cathodes for electroplating, it is possible to connect only the necessary pad portions of the circuit board and the semiconductor chip.
【0018】[0018]
【実施例】以下、本発明の実施例を図面を参照して説明
する。まず、所望の素子が多数形成された厚さ500μ
mの6インチ半導体ウェハをダイシングして図1に示す
100μm角、ピッチが150μmのアルミニウムパッ
ド1を有する10mm角の半導体チップ2を作製した。
なお、前記半導体チップ2の表面には前記パッド1以外
を覆う窒化シリコンからなるパッシベーション膜3が形
成されている。つづいて、前記半導体チップ2のパッド
1以外の中央の7mm角の部分に厚さ50μmのエポキ
シ系の接着剤層4を塗布した。Embodiments of the present invention will be described below with reference to the drawings. First, the thickness of the desired element is 500μ
A 6-inch semiconductor wafer of m was diced to form a 10 mm square semiconductor chip 2 having an aluminum pad 1 having a 100 μm square and a pitch of 150 μm shown in FIG.
A passivation film 3 made of silicon nitride is formed on the surface of the semiconductor chip 2 so as to cover parts other than the pad 1. Subsequently, an epoxy adhesive layer 4 having a thickness of 50 μm was applied to the central 7 mm square portion of the semiconductor chip 2 other than the pad 1.
【0019】次いで、図2に示すように共通配線5によ
り互いに接続された銅からなるパッド6を有し、前記パ
ッド6以外の表面にソルダーレジスト膜7が被覆された
回路基板8を用意し、前記半導体チップ2のアルミニウ
ムパッド1と前記回路基板8のパッド6とを、例えばハ
ーフミラーを用いる位置合わせ装置などによって位置合
わせし、前記半導体チップ2中央部の接着剤層4により
前記回路基板8と前記半導体チップ2を接触させた後、
前記接着剤層4を硬化させることによって前記半導体チ
ップ2と回路基板6を一体化した。Next, as shown in FIG. 2, a circuit board 8 having copper pads 6 connected to each other by a common wiring 5 and having a surface other than the pads 6 covered with a solder resist film 7 is prepared. The aluminum pad 1 of the semiconductor chip 2 and the pad 6 of the circuit board 8 are aligned by, for example, a positioning device using a half mirror, and the adhesive layer 4 in the central portion of the semiconductor chip 2 causes the circuit board 8 and After contacting the semiconductor chip 2,
The semiconductor chip 2 and the circuit board 6 were integrated by curing the adhesive layer 4.
【0020】次いで、図3に示すように硫酸銅250g
/l、硫酸50g/lからなる温度25℃のメッキ液1
1が収容されたメッキ槽12内に前記半導体チップ2が
一体化された回路基板8を浸漬し、前記回路基板8の共
通配線5を陰極とし、かつ高純度銅を陽極13とし、電
流密度5A/dm2 印加して緩やかに攪拌しながら電気
銅メッキ処理を施した。なお、図4中の14は直流電
源、15は前記直流電源14に直列に接続された電流
計、16は前記電源14に対して並列に接続された電圧
計である。このような電気銅メッキ処理により前記回路
基板8のパッド6から銅が析出して図4に示すように厚
さが50μmのメッキ膜(銅バンプ)9が形成された時
点で前記半導体チップ2のアルミニウムパッド1と接続
された。この時、印加する電圧,電流を電圧計16、電
流計15でモニターし、電圧変化を検知することにより
前記半導体チップ2と前記回路基板8との接続完了を確
認することができた。Next, as shown in FIG. 3, 250 g of copper sulfate
/ L, sulfuric acid 50g / l plating solution at a temperature of 25 ℃ 1
1. A circuit board 8 integrated with the semiconductor chip 2 is immersed in a plating tank 12 in which 1 is accommodated, a common wiring 5 of the circuit board 8 is used as a cathode, and high-purity copper is used as an anode 13, and a current density is 5 A. / Dm 2 was applied and electrolytic copper plating was performed with gentle stirring. In FIG. 4, 14 is a DC power supply, 15 is an ammeter connected in series to the DC power supply 14, and 16 is a voltmeter connected in parallel to the power supply 14. When copper is deposited from the pads 6 of the circuit board 8 by the electrolytic copper plating process to form a plating film (copper bump) 9 having a thickness of 50 μm as shown in FIG. 4, the semiconductor chip 2 of the semiconductor chip 2 is formed. It was connected to the aluminum pad 1. At this time, the applied voltage and current were monitored by the voltmeter 16 and the ammeter 15, and the completion of the connection between the semiconductor chip 2 and the circuit board 8 could be confirmed by detecting the voltage change.
【0021】次いで、前記メッキ槽12から前記半導体
チップ2が一体化され、かつ銅バンプ9が形成された回
路基板8を取り出し、純水により洗浄し、窒素ブローに
より乾燥させた後、回路基板8の共通配線の所望個所を
切断し手所定の機能を有する配線10として前記パッド
6を電気的に分離することにより半導体装置を製造した
(図5図示)。Next, the circuit board 8 on which the semiconductor chip 2 is integrated and the copper bumps 9 are formed is taken out from the plating tank 12, washed with pure water, dried by nitrogen blowing, and then the circuit board 8 is removed. A semiconductor device was manufactured by cutting a desired portion of the common wiring and electrically separating the pad 6 as a wiring 10 having a predetermined function (see FIG. 5).
【0022】バンプ数200を有する10mm角の半導
体チップを印刷配線板のような樹脂製回路基板上に前述
した方法によって接合した。このサンプルを−65℃
(30min)→25℃(5min)→150℃(30
min)→25℃(5min)を5000サイクル行っ
たところ、接続箇所には破断は認められなかった。前記
回路基板と半導体チップの間が樹脂系の接着剤が充填さ
れているため、金属バンプのみによる接合よりも信頼性
が向上した。また、金属バンプの強度は70g/個で問
題はなく、バンプ間でショートは全く起こらなかった。A 10 mm square semiconductor chip having 200 bumps was bonded onto a resin circuit board such as a printed wiring board by the method described above. This sample is -65 ℃
(30 min) → 25 ° C (5 min) → 150 ° C (30
min) → 25 ° C. (5 min) for 5000 cycles, but no fracture was observed at the connection points. Since the resin adhesive is filled between the circuit board and the semiconductor chip, the reliability is improved as compared with the bonding using only the metal bumps. The strength of the metal bumps was 70 g / piece, and there was no problem, and no short circuit occurred between the bumps.
【0023】なお、前記実施例では接続される金属バン
プとして銅を用いたが、これに限定されるものではな
く、例えばニッケル,アルミニウム,金,銀,鉄,錫,
鉛,インジウム,ビスマス,チタン,クロム,アンチモ
ンやこれらの合金でもよい。Although copper is used as the metal bump to be connected in the above embodiment, the present invention is not limited to this. For example, nickel, aluminum, gold, silver, iron, tin,
Lead, indium, bismuth, titanium, chromium, antimony or alloys thereof may be used.
【0024】前記実施例では、回路基板のパッドに電気
メッキにより金属バンプを形成したが、前記接着剤層の
接着領域および前記パッドを除く回路基板表面にレジス
ト膜を形成した後、前記電気メッキを行って前記回路基
板のパッドにその面積に近似した形状の金属バンプを形
成してもよい。前記実施例では、印刷配線板のような樹
脂製回路基板を用いたが、基材がシリコン系,アルミナ
系の窒化アルミニウム系などであってもよい。In the above-described embodiment, the metal bumps are formed on the pads of the circuit board by electroplating. However, after forming the resist film on the bonding area of the adhesive layer and the surface of the circuit board excluding the pads, the electroplating is performed. A metal bump having a shape similar to the area may be formed on the pad of the circuit board. Although a resin circuit board such as a printed wiring board is used in the above embodiments, the base material may be a silicon-based or alumina-based aluminum nitride-based material.
【0025】[0025]
【発明の効果】以上詳述したように本発明によれば、半
導体チップと回路基板の接続が金属バンプの形成と同時
に行うことができ、バリアメタルなどの金属も不必要で
従来のフリップチップ法に比べて工程を減少でき、さら
に従来法に比べバンプとして様々な金属を用いることが
でき、応用範囲が広い半導体装置の製造方法を提供する
ことができる。As described in detail above, according to the present invention, the semiconductor chip and the circuit board can be connected at the same time when the metal bumps are formed, and a metal such as a barrier metal is not necessary, and the conventional flip chip method is used. It is possible to provide a method of manufacturing a semiconductor device which can reduce the number of steps as compared with the conventional method and can use various metals as bumps as compared with the conventional method, and has a wide range of applications.
【図1】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.
【図2】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.
【図3】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.
【図4】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.
【図5】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the invention.
【図6】従来法により製造された半導体装置を示す断面
図。FIG. 6 is a cross-sectional view showing a semiconductor device manufactured by a conventional method.
1…アルミニウムパッド、2…半導体チップ、4…接着
剤層、5…共通配線、6…銅パッド、8…回路基板、9
…銅バンプ、10…配線、11…メッキ液、12…メッ
キ槽、13…銅からなる陽極、14…直流電源。DESCRIPTION OF SYMBOLS 1 ... Aluminum pad, 2 ... Semiconductor chip, 4 ... Adhesive layer, 5 ... Common wiring, 6 ... Copper pad, 8 ... Circuit board, 9
... copper bumps, 10 ... wiring, 11 ... plating solution, 12 ... plating bath, 13 ... copper anode, 14 ... DC power supply.
Claims (1)
数のパッドを有する回路基板とをそれらのパッドが互い
に対向するように位置合わせして前記半導体チップと前
記回路基板を固定する工程と、 互いに固定された前記半導体チップ及び前記回路基板を
メッキ液の中に入れ、電気メッキにより前記半導体チッ
プのパッドと前記回路基板のパッドとの間に金属を析出
してそれらのパッド間を電気的に接合する金属バンプを
形成する工程とを具備したことを特徴とする半導体装置
の製造方法。1. A step of fixing a semiconductor chip and a circuit board by aligning a semiconductor chip having a plurality of pads and a circuit board having a plurality of pads so that the pads face each other, and fixing the semiconductor chip and the circuit board together. The semiconductor chip and the circuit board thus prepared are placed in a plating solution, and a metal is deposited between the pad of the semiconductor chip and the pad of the circuit board by electroplating to electrically bond the pads. And a step of forming metal bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32348993A JP3297177B2 (en) | 1993-12-22 | 1993-12-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32348993A JP3297177B2 (en) | 1993-12-22 | 1993-12-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07183304A true JPH07183304A (en) | 1995-07-21 |
| JP3297177B2 JP3297177B2 (en) | 2002-07-02 |
Family
ID=18155266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32348993A Expired - Fee Related JP3297177B2 (en) | 1993-12-22 | 1993-12-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3297177B2 (en) |
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