JPH0629335A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH0629335A JPH0629335A JP4201821A JP20182192A JPH0629335A JP H0629335 A JPH0629335 A JP H0629335A JP 4201821 A JP4201821 A JP 4201821A JP 20182192 A JP20182192 A JP 20182192A JP H0629335 A JPH0629335 A JP H0629335A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- semiconductor device
- lead
- free phenol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/865—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 リードの多ピン化、ファインピッチ化に対応
したはんだ付け性に優れた樹脂封止型半導体装置を提供
する。
【構成】 リードフレームのダイパッド部又はインナー
リード3に固着された半導体素子表面の電極4とインナ
ーリード間が電気的に接続された半導体素子1及びリー
ドフレーム3の一部を、(a)エポキシ樹脂、(b)フ
リーフェノール含有量が0.1wt%以下のフェノール
系樹脂硬化剤、(c)含窒素系化合物等の硬化促進剤及
び(d)無機質充填剤を必須成分とする樹脂組成物6で
封止した樹脂封止型半導体装置において、上記リードフ
レームはプリント基板に電気的に接続される少なくとも
先端部分がパラジウムを主剤又は最外層とするめっき被
膜で覆われており、かつ、上記樹脂組成物は150〜1
90℃、30〜180秒の封止工程で発生するフリーフ
ェノールの発生量が30ppm以下であることとしたも
のである。
(57) [Abstract] [Purpose] To provide a resin-encapsulated semiconductor device having excellent solderability, which is compatible with a large number of lead pins and a fine pitch. A part of the semiconductor element 1 and the lead frame 3 in which the electrodes 4 on the surface of the semiconductor element fixed to the die pad portion of the lead frame or the inner lead 3 and the inner lead are electrically connected to each other are (a) epoxy resin A resin composition 6 containing (b) a phenolic resin curing agent having a free phenol content of 0.1 wt% or less, (c) a curing accelerator such as a nitrogen-containing compound, and (d) an inorganic filler. In the sealed resin-sealed semiconductor device, the lead frame has at least a tip end portion electrically connected to a printed circuit board, which is covered with a plating film containing palladium as a main component or an outermost layer, and the resin composition. Is 150-1
The amount of free phenol generated in the sealing step at 90 ° C. for 30 to 180 seconds is 30 ppm or less.
Description
【0001】[0001]
【産業上の利用分野】本発明は、樹脂封止型半導体装置
に係り、特に、リードの多ピン化、ファインピッチ化に
対応したはんだ付け性に優れた樹脂封止型半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more particularly to a resin-encapsulated semiconductor device which has excellent solderability and is compatible with a large number of leads and a fine pitch.
【0002】[0002]
【従来の技術】半導体素子を外部環境から保護し、プリ
ント基板への実装を容易にするためのパッケージ技術と
して、従来から樹脂封止技術が広く用いられている。し
かし、半導体素子はこれまで3年に4倍のピッチで高集
積度化が進み、それに伴って素子サイズの大型化が進ん
でいる。また、素子の高集積、高性能、多機能化に伴い
ピン数の増大も急激に進んでいる。2. Description of the Related Art Conventionally, resin encapsulation technology has been widely used as a packaging technology for protecting semiconductor elements from the external environment and facilitating mounting on a printed circuit board. However, the degree of integration of semiconductor elements has been increasing at a quadruple pitch in the past three years, and the element size has been increasing accordingly. In addition, the number of pins is rapidly increasing with the high integration, high performance, and multi-functionalization of devices.
【0003】一方、各種エレクトロニクス機器の小型軽
量化、高性能化などのニーズから、各種半導体装置には
実装の高密度化が強く望まれ、半導体部品のパッケージ
は小型薄型化の趨勢にある。また、パッケージの形状も
ピンをプリント基板のスルーホールに差し込んで実装す
るDIP( Dual Inline Plastic Package )、ZIP
( Zigzag Inline Plastic Package )、SIP( Singl
e Inline Plastic Package )といったいわゆるピン挿入
型から、最近はSOP( Small Outline PlasticPackag
e )、SOJ( Small Outline J-lead Plastic Package
) 、QFP( Quad Flat Plastic Package )のような
両面実装が可能で、しかもサイズが小さな表面実装型の
パッケージの需要が急増している。このような半導体部
品のプリント基板への実装は通常はんだ付けによって行
われている。On the other hand, from the needs of miniaturization, weight reduction, and high performance of various electronic equipments, it is strongly desired that various semiconductor devices have high packaging density, and the package of semiconductor parts is in the trend of miniaturization and thinning. In addition, the package shape is DIP (Dual Inline Plastic Package) which mounts the pin by inserting it into the through hole of the printed circuit board, ZIP.
(Zigzag Inline Plastic Package), SIP (Singl
From the so-called pin insertion type such as e Inline Plastic Package) to SOP (Small Outline Plastic Package)
e), SOJ (Small Outline J-lead Plastic Package
), A double-sided mounting such as QFP (Quad Flat Plastic Package) is possible, and the demand for a small surface mounting type package is rapidly increasing. Mounting of such semiconductor components on a printed circuit board is usually performed by soldering.
【0004】[0004]
【発明が解決しようとする課題】しかし、素子の高集
積、高機能化とともに多ピン化が進む一方でパッケージ
に小型化が求められる結果、リードの微細化、ファイン
ピッチ化が進み、こうした部品をプリント基板に実装
(はんだ付け)するうえでいろいろな技術的課題が発生
するようになった。すなわち、リード間隔の極端に狭い
部品をプリント基板に実装する場合隣接するリード間で
はんだのブリッジングが起こり、リードが短絡(ショー
ト)する問題が発生し易くなった。これは次の理由によ
る。従来、樹脂封止型半導体はプリント基板へのはんだ
付けを容易にするため、素子の樹脂封止が完了するとア
ウターリードにはんだめっきを施していた。ところが、
はんだめっきを施したリードフレームは、はんだとの濡
れが良好なため、これをプリント基板にはんだ付けしよ
うとすると基板の回路部に予め塗布しておいたはんだを
リードフレームが吸い上げ、また、予めリードフレーム
にめっきしたはんだが溶融して流動するため、リードフ
レームには局部的にはんだが異常に多い箇所が発生し、
その部分でリードがショートするためであった。However, as the number of pins increases with higher integration and higher functionality of devices, miniaturization of packages is required, resulting in finer leads and finer pitch. Various technical problems have come to occur when mounting (soldering) on a printed circuit board. That is, when a component having an extremely narrow lead interval is mounted on a printed circuit board, solder bridging occurs between adjacent leads, which easily causes a problem of short-circuiting the leads. This is for the following reason. Conventionally, in order to facilitate the soldering of a resin-sealed semiconductor to a printed circuit board, the outer lead is solder-plated when the resin sealing of the element is completed. However,
The solder-plated lead frame has good wetting with the solder, so when you try to solder it onto the printed circuit board, the lead frame absorbs the solder that has been applied to the circuit part of the board in advance, Since the solder plated on the frame melts and flows, there are some areas of the lead frame where the amount of solder is abnormally high.
This was because the lead short-circuited at that part.
【0005】こうした問題に対処するため、最近はリー
ドフレームの表面に薄いパラジウムめっきを施したリー
ドフレームを用いて半導体を樹脂封止する試みがなされ
ている。これは、パラジウムめっきを施こしたリードフ
レームは、はんだとの濡れ性は極めて良好であるが、は
んだ付けの際パラジウム自体が溶融しないためにはんだ
の付き過ぎによるリードフレームの異常な太りが起こり
にくく、リードが狭ピッチ化しても隣接するリード間の
はんだのブリッジングによるリードの短絡(ショート)
が発生しにくいためである。In order to deal with such a problem, attempts have recently been made to seal a semiconductor with a resin by using a lead frame whose surface is thinly plated with palladium. This is because the lead frame plated with palladium has extremely good wettability with solder, but since palladium itself does not melt during soldering, abnormal thickening of the lead frame due to excessive soldering is unlikely to occur. , Even if the lead pitch is narrowed, the lead is short-circuited due to solder bridging between adjacent leads.
Is less likely to occur.
【0006】ところが、このようなパラジウムめっきを
施したリードフレームを用いた樹脂封止型半導体装置は
リードのはんだ濡れ性の経時変化が著しく、加熱、加湿
処理工程を経るに従ってはんだ濡れ性が低下し、その解
決がパラジウムめっきを施したリードフレームを樹脂封
止型半導体に適用するうえで重要な技術課題になってい
た。本発明は、このような状況に鑑みなされたものであ
り、特に、リードの多ピン化、ファインピッチ化に対応
したはんだ付け性に優れた樹脂封止型半導体装置を提供
することを課題とするものである。However, in the resin-encapsulated semiconductor device using such a lead frame plated with palladium, the solder wettability of the lead is remarkably changed with time, and the solder wettability is lowered as the heating and humidification treatment steps are performed. However, the solution has become an important technical issue in applying the lead frame plated with palladium to the resin-sealed semiconductor. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a resin-encapsulated semiconductor device having excellent solderability corresponding to a multi-pin lead and a fine pitch. It is a thing.
【0007】[0007]
【課題を解決するための手段】上記課題を解決するた
め、パラジウムめっきを施したリードフレームのはんだ
濡れ性が経時変化を起こす理由について詳細な解析を行
った。その結果、はんだ濡れ性が低下する理由は樹脂封
止を行う際、封止材料から発生するフリーフェノールが
リードフレームの表面に付着し、それがパラジウムの触
媒作用によって変質し、それがはんだ濡れ性を低下させ
ることが明らかになった。従って、パラジウムめっきを
施したリードフレームのはんだ濡れ性の経時変化を抑制
するためには封止工程で封止材料から発生するフリーフ
ェノールを低減することが必要なことが明らかになっ
た。本発明はこのような状況を鑑み成し遂げられたもの
であり、その要点は以下の通りである。[Means for Solving the Problems] In order to solve the above problems, a detailed analysis was conducted on the reason why the solder wettability of a lead frame plated with palladium changes with time. As a result, the reason why solder wettability decreases is that during resin encapsulation, free phenol generated from the encapsulating material adheres to the surface of the lead frame, which is altered by the catalytic action of palladium, which causes solder wettability. It has become clear that Therefore, it has been clarified that it is necessary to reduce the amount of free phenol generated from the encapsulating material in the encapsulation step in order to suppress the change in solder wettability of the lead frame plated with palladium over time. The present invention has been accomplished in view of such circumstances, and the main points are as follows.
【0008】すなわち、リードフレームのダイパッド部
又はインナーリードに固着された半導体素子表面の電極
とインナーリード間が電気的に接続された半導体素子及
びリードフレームの一部を、(a)エポキシ樹脂、
(b)フェノール系樹脂硬化剤、(c)硬化促進剤及び
(d)無機質充填剤を必須成分とする樹脂組成物で封止
した樹脂封止型半導体装置において、上記リードフレー
ムはプリント基板に電気的に接続される少なくとも先端
部分がパラジウムを主剤又は最外層とするめっき被膜で
覆われており、かつ、上記樹脂組成物は150〜190
℃、30〜180秒の封止工程で発生するフリーフェノ
ールの発生量が30ppm以下であることとしたもので
ある。上記において、リードフレームは銅又は銅系合金
であるのがよく、また、樹脂組成物は、(b)樹脂硬化
剤が分子内にフェノール性水酸基を2個以上含み、か
つ、フリーフェノール含有量が0.1wt%以下のフェ
ノール系樹脂であり、(c)硬化促進剤が含窒素系化合
物であるものを用いるのがよい。That is, a part of the lead frame and the semiconductor element in which the electrodes on the surface of the semiconductor element fixed to the die pad portion or the inner lead of the lead frame and the inner lead are electrically connected are (a) epoxy resin,
In a resin-encapsulated semiconductor device encapsulated with a resin composition containing (b) a phenolic resin curing agent, (c) a curing accelerator, and (d) an inorganic filler as essential components, the lead frame is electrically connected to a printed circuit board. At least the tip end portion to be electrically connected is covered with a plating film containing palladium as a main component or an outermost layer, and the resin composition is 150 to 190.
The amount of free phenol generated in the sealing step at 30 ° C. for 30 to 180 seconds is 30 ppm or less. In the above, the lead frame is preferably copper or a copper-based alloy, and the resin composition is such that (b) the resin curing agent contains two or more phenolic hydroxyl groups in the molecule, and the free phenol content is It is preferable to use a phenolic resin of 0.1 wt% or less and a curing accelerator (c) which is a nitrogen-containing compound.
【0009】[0009]
【作用】現在エポキシ樹脂系半導体封止材料の硬化剤と
して用いられるフェノール系樹脂は、フェノールとホル
マリンとの付加縮合反応によって合成される。そのため
樹脂中には未反応のフェノールが残存する。それ故、フ
リーフェノールの発生源は硬化剤のフェノール系樹脂と
考えられる。従って、フリーフェノールの発生量を低減
するためにはフェノール系樹脂中に含まれる未反応のフ
ェノール量を減らすことが先ず重要である。しかし、未
反応のフェノール量を極端に少なくすることには技術的
にも経済的にも限界がある。一方、封止材料は封止工程
で樹脂成分の熱分解が起こり、フリーフェノールはこの
ような樹脂成分の熱分解によっても発生する。従って、
フリーフェノールの発生量を低減するためにはこのよう
な樹脂成分の熱分解を抑制することも重要である。The phenolic resin currently used as a curing agent for epoxy resin-based semiconductor encapsulation materials is synthesized by the addition condensation reaction of phenol and formalin. Therefore, unreacted phenol remains in the resin. Therefore, the source of free phenol is considered to be the phenolic resin of the curing agent. Therefore, in order to reduce the amount of free phenol generated, it is first important to reduce the amount of unreacted phenol contained in the phenolic resin. However, it is technically and economically limited to extremely reduce the amount of unreacted phenol. On the other hand, the encapsulating material undergoes thermal decomposition of the resin component in the encapsulation process, and free phenol is also generated by such thermal decomposition of the resin component. Therefore,
In order to reduce the amount of free phenol generated, it is important to suppress the thermal decomposition of such resin components.
【0010】本発明では、硬化促進剤として含窒素系化
合物を用いることにより、フェノール系樹脂中に含まれ
るフリーフェノールの系外への放出を抑制できると同時
に、封止工程で起こる樹脂成分の熱分解も抑制するもの
である。本発明に用いることのできる含窒素系化合物と
しては、イミダゾール、1−メチルイミダゾール、2−
エチル−4−メチルイミダゾール、1−シアノエチル−
2−エチル−4−メチルイミダゾール、1−シアノエチ
ル−2−ウンデシルイミダゾール、1−シアノエチル−
2−フェニルイミダゾール、N−ベンジルジメチルアミ
ン、2,4,6−トリス(ジメチルアミノメチル)フェ
ノール、テトラメチルブチルグアニジン、ピリジン、N
−メチルピペラジン、ピペリジン、1,8−ジアザビシ
クロ(5,4,0)−7−ウンデセンあるいはこれらの
誘導体及び各化合物の有機酸塩、有機ボロン塩などを上
げることができる。In the present invention, by using a nitrogen-containing compound as a curing accelerator, the release of free phenol contained in the phenolic resin to the outside of the system can be suppressed, and at the same time, the heat of the resin component generated in the sealing step can be suppressed. It also suppresses decomposition. Examples of the nitrogen-containing compound that can be used in the present invention include imidazole, 1-methylimidazole, 2-
Ethyl-4-methylimidazole, 1-cyanoethyl-
2-ethyl-4-methylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyanoethyl-
2-phenylimidazole, N-benzyldimethylamine, 2,4,6-tris (dimethylaminomethyl) phenol, tetramethylbutylguanidine, pyridine, N
-Methylpiperazine, piperidine, 1,8-diazabicyclo (5,4,0) -7-undecene or their derivatives, and organic acid salts and organic boron salts of each compound can be used.
【0011】本発明の封止材料に用いるエポキシ樹脂は
特にその構造を限定するものではないが、o−クレゾー
ルノボラック型エポキシ樹脂、ビスフェノールAを原料
にした2官能あるいは多官能型エポキシ樹脂、ナフタレ
ン又はビフェニル骨格を有する2官能あるいは多官能型
エポキシ樹脂等を用いることができる。フェノール系硬
化剤としては、フェノールノボラック樹脂のほか、o−
クレゾールノボラック樹脂、ポリ−p−ビニルフェノー
ル、フェノールとアラルキルエーテルとの縮合物などの
フェノール系樹脂を用いることができる。無機充填剤と
しては溶融シリカ、結晶性シリカ、アルミナなどを用い
ることができる。また、上記以外にも必要に応じてカッ
プリング剤、離型剤、着色剤、難燃化剤、可とう化剤な
どを配合することもできる。The epoxy resin used for the encapsulating material of the present invention is not particularly limited in its structure, but is an o-cresol novolac type epoxy resin, a bifunctional or polyfunctional epoxy resin using bisphenol A as a raw material, naphthalene or A bifunctional or polyfunctional epoxy resin having a biphenyl skeleton can be used. As the phenol-based curing agent, in addition to phenol novolac resin, o-
Phenolic resins such as cresol novolac resin, poly-p-vinylphenol, and a condensation product of phenol and aralkyl ether can be used. As the inorganic filler, fused silica, crystalline silica, alumina or the like can be used. In addition to the above, a coupling agent, a release agent, a colorant, a flame retardant, a softening agent and the like can be added as required.
【0012】これらの各素材は二軸ロールや押出し機を
用いて混練し封止材料にすることができる。また、こう
して得られた封止材料はトランスファープレスを用いて
従来と全く同様の方法で半導体の樹脂封止を行なうこと
ができる。本発明の樹脂封止型半導体装置に用いるリー
ドフレームは銅又は銅系合金が望ましい。例えば鉄系の
リードフレームは表面にパラジウムめっきを施すとリー
ドフレームの耐食性が著しく低下し実用的でない。銅系
リードフレームにパラジウムめっきを施す場合、各層間
の密着力を向上するためたとえば下地にニッケルめっき
などを行っても良い。最外層のパラジウムめっきの厚さ
は特に限定されるものではないが、少なくとも0.1μ
m以上の厚さを有することが望ましい。Each of these materials can be kneaded into a sealing material using a twin-screw roll or an extruder. The thus obtained sealing material can be used for resin sealing of a semiconductor by using a transfer press in the same manner as the conventional method. The lead frame used for the resin-encapsulated semiconductor device of the present invention is preferably copper or a copper-based alloy. For example, iron-based lead frames are not practical when the surface is plated with palladium, because the corrosion resistance of the lead frames is significantly reduced. When palladium plating is applied to the copper-based lead frame, for example, nickel plating may be applied to the base in order to improve the adhesion between the layers. The thickness of the palladium plating of the outermost layer is not particularly limited, but is at least 0.1 μm.
It is desirable to have a thickness of m or more.
【0013】次に、モールド封止工程で発生するフェノ
ール量とリードフレームのはんだ濡れ不良率との関係
を、図6〜図8に示す。図6〜図8において、フェノー
ル発生量は封止工程を180℃で90秒加熱で行った際
に発生するフェノール量(ppm)であり、図6は二次
キュアすなわち180℃で5時間加熱後のはんだ濡れ不
良率(%)を示すグラフであり、図7はベーク後すなわ
ち150℃で168時間後のはんだ濡れ不良率(%)を
示すグラフであり、また、図8は100℃、100%相
対湿度下で16時間加湿後のはんだ濡れ不良率(%)を
示すグラフである。これらの図からもわかるように、封
止工程でのフェノール発生量が30ppm以下の場合は
いずれの処理後もはんだ濡れ不良率は0%であり、この
ような封止材料で封止した半導体装置が優れていること
が明らかである。なお、a〜eは実施例の樹脂a〜eに
相当する材料を示す。Next, FIG. 6 to FIG. 8 show the relationship between the amount of phenol generated in the mold sealing step and the solder wetting defect rate of the lead frame. 6 to 8, the amount of phenol generated is the amount of phenol (ppm) generated when the sealing step is performed by heating at 180 ° C. for 90 seconds, and FIG. 6 shows the secondary cure, that is, after heating at 180 ° C. for 5 hours. Is a graph showing the solder wetting failure rate (%) of FIG. 7, FIG. 7 is a graph showing the solder wetting failure rate (%) after baking, that is, after 168 hours at 150 ° C., and FIG. 8 is 100 ° C., 100%. It is a graph which shows a solder wetting failure rate (%) after humidification for 16 hours under relative humidity. As can be seen from these figures, when the amount of phenol generated in the sealing step is 30 ppm or less, the solder wetting defect rate is 0% after any of the treatments, and the semiconductor device sealed with such a sealing material is Is clearly superior. Note that a to e indicate materials corresponding to the resins a to e in the examples.
【0014】[0014]
【実施例】以下、本発明を実施例により具体的に説明す
るが、本発明はこれらに限定されない。 実施例1 まず、本発明に用いる封止材料の例を説明する。 樹脂例a エポキシ樹脂として、o−クレゾールノボラック型エポ
キシ樹脂を85重量部及び臭素化ビスフェノールA型エ
ポキシ樹脂を15重量部、硬化剤としてフリーフェノー
ル含有量が0.5wt%のフェノールノボラック樹脂を
52重量部、硬化促進剤として1,8−ジアザビシクロ
(5,4,0)−7−ウンデセンを1.5重量部、可撓
化剤として両末端にアミノ基を有する分子量が約80,
000のポリジメチルシロキサン8重量部、充填剤とし
て溶融シリカを350重量部、カップリング剤としてエ
ポキシシランを2重量部、離形剤としてモンタン酸エス
テルを1重量部、難燃化助剤として三酸化アンチモンを
10重量部、着色剤としてカーボンブラックを1重量部
を計量した。次いで、これらの各素材を約80℃に加熱
した二軸ロールを用いて約15分間混練し目的とする封
止材料を作製した。EXAMPLES The present invention will be specifically described below with reference to examples, but the present invention is not limited thereto. Example 1 First, an example of a sealing material used in the present invention will be described. Resin Example a As an epoxy resin, 85 parts by weight of an o-cresol novolac type epoxy resin and 15 parts by weight of a brominated bisphenol A type epoxy resin, and 52 parts by weight of a phenol novolac resin having a free phenol content of 0.5 wt% as a curing agent. Part, 1.5 parts by weight of 1,8-diazabicyclo (5,4,0) -7-undecene as a curing accelerator, and a molecular weight of about 80 having amino groups at both ends as a flexibilizer,
000 polydimethylsiloxane 8 parts by weight, 350 parts by weight of fused silica as a filler, 2 parts by weight of epoxysilane as a coupling agent, 1 part by weight of montanic acid ester as a release agent, and trioxide as a flame retardant aid. 10 parts by weight of antimony and 1 part by weight of carbon black as a colorant were weighed. Then, each of these materials was kneaded for about 15 minutes using a biaxial roll heated to about 80 ° C. to produce a target sealing material.
【0015】樹脂例b エポキシ樹脂としてテトラメチルビフェノール型エポキ
シ樹脂を85重量部用いたほかは上記樹脂例aと同様に
して封止材料を作製した。Resin Example b A sealing material was prepared in the same manner as in Resin Example a except that 85 parts by weight of tetramethylbiphenol type epoxy resin was used as the epoxy resin.
【0016】樹脂例c 硬化剤としてフリーフェノール含有量が0.35wt%
のフェノールアラルキル樹脂を95重量部用いたほかは
上記樹脂例aと同様にして封止材料を作製した。Resin Example c Free phenol content of 0.35 wt% as a curing agent
A sealing material was prepared in the same manner as in the above resin example a except that 95 parts by weight of the phenol aralkyl resin in Example 1 was used.
【0017】樹脂例d(比較例) 硬化剤としてフリーフェノール含有量が1.5wt%の
フェノールノボラック樹脂を用いたほかは上記樹脂例a
と同様にして封止材料を作製した。Resin Example d (Comparative Example) Resin Example a above except that a phenol novolac resin having a free phenol content of 1.5 wt% was used as a curing agent.
A sealing material was prepared in the same manner as in.
【0018】樹脂例e(比較例) 硬化促進剤としてテトラフェニルホスフィンを1.5重
量部用いたほかは上記樹脂例aと同様にして封止材料を
作製した。Resin Example e (Comparative Example) A sealing material was prepared in the same manner as in Resin Example a except that 1.5 parts by weight of tetraphenylphosphine was used as a curing accelerator.
【0019】次に、本発明を適用した半導体装置の構造
を図面を用いて説明する。図1は半導体素子1をフィル
ム状の両面接着剤2を介してリード3に固着した後、素
子上の電極4とインナーリード3を金ワイヤ5で電気的
に接続した後、素子及びインナーリードを封止材料6で
封止したSOJの例である。アウターリードにはパラジ
ウムめっき7が施してある。図2は、リードフレームの
ダイパッド部8に半導体素子1を銀ペースト9で固着
し、素子上の電極4とインナーリード3を金ワイヤ5で
電気的に接続した後、素子及びインナーリードを封止材
料6で封止したTSOP( Thin Small Outline Plasti
c Package ) の例である。アウターリードには上記同様
にパラジウムめっきが施してある。Next, the structure of the semiconductor device to which the present invention is applied will be described with reference to the drawings. FIG. 1 shows that after the semiconductor element 1 is fixed to the leads 3 via the film-shaped double-sided adhesive 2, the electrodes 4 on the elements and the inner leads 3 are electrically connected by the gold wires 5, and then the elements and the inner leads are connected. It is an example of SOJ sealed with the sealing material 6. Palladium plating 7 is applied to the outer leads. In FIG. 2, the semiconductor element 1 is fixed to the die pad portion 8 of the lead frame with the silver paste 9, and the electrode 4 on the element and the inner lead 3 are electrically connected with the gold wire 5, and then the element and the inner lead are sealed. TSOP (Thin Small Outline Plasti) sealed with Material 6
c Package). The outer leads are plated with palladium as described above.
【0020】図3は半導体素子(1と1′)を固着した
リード同士(3と3′)を接合して半導体素子を二段重
ねにし、これを封止材料6で樹脂封止した外観上はSO
J(Small Outline Plastic Package ) の例である。ア
ウターリードには上記同様にパラジウムめっきが施して
ある。上記によって作製した5種類の樹脂例a〜eの封
止材料について、180℃で90秒加熱した場合に発生
するフリーフェノール量をガスクロマトグラフィーを用
いて測定した。また、図1に示す半導体装置を上記の樹
脂例a〜eの封止材料で樹脂封止し、封止直後、後硬化
後、さらに加熱、加湿処理を行った後のリードフレーム
のはんだ濡れ性を評価した。なお、はんだ濡れ性の良否
は、リードフレームのはんだ濡れ不良(はんだのはじ
き)部分が表面積の5%以内の場合を良とし、5%以上
の場合を否とした。評価結果をまとめて表1に示す。FIG. 3 shows the appearance in which the leads (3 and 3 ') to which the semiconductor elements (1 and 1') are fixed are joined to form a two-tier semiconductor element, which is resin-sealed with a sealing material 6. Is SO
This is an example of J (Small Outline Plastic Package). The outer leads are plated with palladium as described above. The amount of free phenol generated when the encapsulating materials of the five resin examples a to e produced as described above were heated at 180 ° C. for 90 seconds was measured using gas chromatography. Further, the semiconductor device shown in FIG. 1 is resin-sealed with the sealing materials of the above resin examples a to e, and the solder wettability of the lead frame immediately after sealing, after post-curing, and after further heating and humidification treatment. Was evaluated. The solder wettability was judged to be good when the poor solder wettability (solder repelling) portion of the lead frame was within 5% of the surface area, and when it was 5% or more. The evaluation results are summarized in Table 1.
【0021】[0021]
【表1】 表1から明らかなように、本発明の封止材料は封止工程
で発生するフリーフェノール量が少ない。また、樹脂封
止半導体装置は後硬化後、さらにその後の長時間の加
熱、加湿処理工程を経てもはんだ濡れ性の低下が起こら
ないことがわかる。[Table 1] As is clear from Table 1, the sealing material of the present invention has a small amount of free phenol generated in the sealing step. Further, it can be seen that the resin-encapsulated semiconductor device does not deteriorate in solder wettability even after the post-curing and subsequent heating and humidification treatment steps for a long time.
【0022】図4は本発明のパラジウムめっきをほどこ
したリードフレームを用いた半導体装置をプリント基板
にはんだ付けした場合、図5は従来のはんだめっきを施
したリードフレームを用いた半導体装置をプリント基板
にはんだ付けした場合のリードフレームに対するはんだ
の付き具合を比較した結果である。従来のはんだめっき
を施したリードフレームを用いた半導体装置(図5)は
プリント基板に予め付けておいたはんだが吸い上げられ
リードフレーム周辺のはんだの付着が多く、リードフレ
ームが太って見えるのに対し、本発明のパラジウムめっ
きを施こしたリードフレームを用いた半導体装置(図
4)ははんだの付き過ぎによるリードの太りはほとんど
認められない。FIG. 4 shows a case where a semiconductor device using a lead frame plated with palladium of the present invention is soldered to a printed circuit board, and FIG. 5 shows a semiconductor device using a conventional lead frame subjected to solder plating. It is a result of comparing the degree of solder attachment to the lead frame when soldering is performed on the. In the conventional semiconductor device using a lead frame plated with solder (Fig. 5), the solder pre-attached to the printed circuit board is sucked up and the solder around the lead frame adheres a lot, so the lead frame looks thick. In the semiconductor device (FIG. 4) using the palladium-plated lead frame of the present invention, lead thickening due to excessive soldering is hardly recognized.
【0023】[0023]
【発明の効果】このように、本発明のパラジウムめっき
を施したリードフレームは、はんだ濡れ性の経時変化が
少なく、また、基板実装時のはんだ付け性が良好であ
り、リードの狭ピッチ化が進む多ピン素子用に好適なこ
とがわかる。As described above, the lead frame plated with palladium of the present invention has little change in solder wettability with time, has good solderability at the time of mounting on a substrate, and has a narrow lead pitch. It can be seen that it is suitable for advanced multi-pin devices.
【図1】本発明の半導体装置の一例を示す概略断面図。FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor device of the present invention.
【図2】本発明の半導体装置の他の例を示す概略断面
図。FIG. 2 is a schematic cross-sectional view showing another example of the semiconductor device of the present invention.
【図3】本発明の半導体装置のもう一つの例を示す概略
断面図。FIG. 3 is a schematic cross-sectional view showing another example of the semiconductor device of the present invention.
【図4】本発明のリードフレームを基板にはんだ付けし
た場合の部分拡大図。FIG. 4 is a partially enlarged view of the lead frame of the present invention soldered to a substrate.
【図5】従来のリードフレームを基板にはんだ付けした
場合の部分拡大図。FIG. 5 is a partially enlarged view of a conventional lead frame soldered to a substrate.
【図6】フェノール発生量とはんだ濡れ不良率の関係を
示すグラフ。FIG. 6 is a graph showing the relationship between the amount of phenol generated and the solder wetting failure rate.
【図7】フェノール発生量とはんだ濡れ不良率の関係を
示すグラフ。FIG. 7 is a graph showing the relationship between the amount of phenol generated and the solder wetting failure rate.
【図8】フェノール発生量とはんだ濡れ不良率の関係を
示すグラフ。FIG. 8 is a graph showing the relationship between the amount of phenol generated and the solder wetting failure rate.
1,1′:半導体素子、2:両面接着剤、3,3′:リ
ード、4:電極、5:金ワイヤ、6:封止材料、7:パ
ラジウムめっき、8:ダイパッド部、9:銀ペースト、
10:はんだ、11:プリント基板1, 1 ': semiconductor element, 2: double-sided adhesive, 3, 3': lead, 4: electrode, 5: gold wire, 6: sealing material, 7: palladium plating, 8: die pad part, 9: silver paste ,
10: Solder, 11: Printed circuit board
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/50 N 9272−4M G 9272−4M // H05K 1/18 H 9154−4E (72)発明者 江口 州志 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 宝蔵寺 裕之 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 石井 利昭 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H01L 23/50 N 9272-4M G 9272-4M // H05K 1/18 H 9154-4E (72) Inventor Satoshi Eguchi 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory Ltd. (72) Inventor Hiroyuki Hozoji 4026 Kuji Town Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory Ltd. (72) Inventor Ishii Toshiaki 4026 Kuji Town, Hitachi City, Ibaraki Prefecture
Claims (3)
ナーリードに固着された半導体素子表面の電極とインナ
ーリード間が電気的に接続された半導体素子及びリード
フレームの一部を、(a)エポキシ樹脂、(b)フェノ
ール系樹脂硬化剤、(c)硬化促進剤及び(d)無機質
充填剤を必須成分とする樹脂組成物で封止した樹脂封止
型半導体装置において、上記リードフレームはプリント
基板に電気的に接続される少なくとも先端部分がパラジ
ウムを主剤又は最外層とするめっき被膜で覆われてお
り、かつ、上記樹脂組成物は150〜190℃、30〜
180秒の封止工程で発生するフリーフェノールの発生
量が30ppm以下であることを特徴とする樹脂封止型
半導体装置。1. A semiconductor element in which an electrode on a surface of a semiconductor element fixed to a die pad portion or an inner lead of a lead frame and an inner lead are electrically connected to each other and a part of the lead frame are provided with (a) an epoxy resin, In a resin-sealed semiconductor device sealed with a resin composition containing b) a phenolic resin curing agent, (c) a curing accelerator, and (d) an inorganic filler as essential components, the lead frame is electrically connected to a printed circuit board. Is coated with a plating film containing palladium as a main component or an outermost layer, and the resin composition has a temperature of 150 to 190 ° C.
A resin-encapsulated semiconductor device, wherein the amount of free phenol generated in a 180-second sealing step is 30 ppm or less.
あることを特徴とする請求項1記載の樹脂封止型半導体
装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the lead frame is made of copper or a copper-based alloy.
樹脂硬化剤が分子内にフェノール性水酸基を2個以上含
み、かつ、フリーフェノール含有量が0.1wt%以下
のフェノール系樹脂であり、(c)硬化促進剤が含窒素
系化合物であることを特徴とする請求項1又は2記載の
樹脂封止型半導体装置。3. The resin composition according to claim 1, wherein (b) the phenolic resin curing agent contains two or more phenolic hydroxyl groups in the molecule, and the free phenol content is 0.1 wt% or less. The resin-encapsulated semiconductor device according to claim 1 or 2, wherein the curing accelerator (c) is a nitrogen-containing compound.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4201821A JP2673764B2 (en) | 1992-07-07 | 1992-07-07 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4201821A JP2673764B2 (en) | 1992-07-07 | 1992-07-07 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0629335A true JPH0629335A (en) | 1994-02-04 |
| JP2673764B2 JP2673764B2 (en) | 1997-11-05 |
Family
ID=16447463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4201821A Expired - Fee Related JP2673764B2 (en) | 1992-07-07 | 1992-07-07 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2673764B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834831A (en) * | 1994-08-16 | 1998-11-10 | Fujitsu Limited | Semiconductor device with improved heat dissipation efficiency |
| US6005286A (en) * | 1997-10-06 | 1999-12-21 | Micron Technology, Inc. | Increasing the gap between a lead frame and a semiconductor die |
| US10125252B2 (en) | 2013-05-31 | 2018-11-13 | Toray Industries, Inc. | Ethylene-vinyl alcohol copolymer microparticles, dispersion liquid and resin composition containing same, and method of producing said microparticles |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02175747A (en) * | 1988-12-28 | 1990-07-09 | Nippon Steel Chem Co Ltd | Epoxy resin composition for sealing |
| JPH02298056A (en) * | 1989-02-22 | 1990-12-10 | Texas Instr Inc <Ti> | Reliablepackage of intebrated circuit |
-
1992
- 1992-07-07 JP JP4201821A patent/JP2673764B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02175747A (en) * | 1988-12-28 | 1990-07-09 | Nippon Steel Chem Co Ltd | Epoxy resin composition for sealing |
| JPH02298056A (en) * | 1989-02-22 | 1990-12-10 | Texas Instr Inc <Ti> | Reliablepackage of intebrated circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834831A (en) * | 1994-08-16 | 1998-11-10 | Fujitsu Limited | Semiconductor device with improved heat dissipation efficiency |
| US6005286A (en) * | 1997-10-06 | 1999-12-21 | Micron Technology, Inc. | Increasing the gap between a lead frame and a semiconductor die |
| US6133068A (en) * | 1997-10-06 | 2000-10-17 | Micron Technology, Inc. | Increasing the gap between a lead frame and a semiconductor die |
| US10125252B2 (en) | 2013-05-31 | 2018-11-13 | Toray Industries, Inc. | Ethylene-vinyl alcohol copolymer microparticles, dispersion liquid and resin composition containing same, and method of producing said microparticles |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2673764B2 (en) | 1997-11-05 |
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