JPH06104756A - Device for increasing signal resolution - Google Patents

Abstract

PURPOSE: To improve the resolution of number of revolution signals. CONSTITUTION: The period length of a signal from a number of revolution sensor 105 is measured by means of first and third counters 120 and 130 which are cascade-connected with each other, in accordance with the clock frequency of an oscillator 115. The third counter 130 has the count value corresponding to the periodic length of the sensor signal. When the value is loaded into a second counter 140 and the count value of the counter 140 becomes zero as the clock frequency is subtracted from the value, a drive signal is generated from the output of the counter 140 and inputted to an engine controller 100. Since the generating interval of the drive signal is set at a prescribed fraction of the period of the sensor signals, the resolution of the sensor 105 can be enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for increasing the resolution of signals, and more particularly to an apparatus for increasing the angular resolution of signals, especially rotational speed sensor signals.

[0002]

2. Description of the Related Art An apparatus of this type is, for example, DE-OS29.
Known from 18498. In this publication, a pulse multiple (multiplication) circuit for dividing an interval between two pulses into an arbitrary number of pulses is described.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to provide a device which makes it possible to increase the angular resolution of the speed signal. In that case, this signal must have very good dynamic characteristics.

[0004]

In order to solve the above-mentioned problems, according to the present invention, in a device for improving the resolution of a signal, in particular, a rotation speed sensor signal, the cycle length of the signal is obtained by a multistage counting means. Therefore, a configuration is adopted in which a means for generating a pulse whose interval is a fraction of the cycle length obtained by the multi-stage counting means is provided.

[0005]

According to the device of the present invention, it is possible to improve the resolution of signals. Preferred embodiments of the invention are described in the dependent claims.

[0006]

The present invention will be described in detail below with reference to the embodiments shown in the drawings.

A device for increasing the angular resolution of the signal is preferably used when processing the signal of the speed sensor.
In that case, the problem of detecting the axis position with high accuracy frequently occurs. For that purpose, a wheel with a certain number of markings is arranged on the shaft. The sensor detects this marking, which is then converted in a processing circuit (evaluation circuit) into a series of rectangular pulses. 2 (a) and 4 (a) show part of a pulse train of this kind having two such pulses.
Such a device is known, for example, from DE-OS 2918498.

To obtain the most accurate signal possible, the markings must be very closely spaced. Due to the manufacturing precision of the wheel and the markings, and also due to the geometrical shape of the wheel, the angular spacing cannot necessarily be chosen to be any size. Therefore, other means are needed to increase the resolution.

Particularly when controlling an internal combustion engine, a highly accurate drive pulse must be output at a predetermined angular position of the crankshaft and / or the camshaft. The drive pulse determines, for example, an ignition time point in a gasoline internal combustion engine and a fuel feed start time or a fuel end time in a diesel internal combustion engine. Particularly in a diesel internal combustion engine, it is important to determine this drive pulse with high accuracy.

Particularly in diesel internal combustion engines, a so-called time interpolation method is currently used to improve the resolution. A method of this kind is, for example, DE-OS 40041.
Known from 107. The method is preferably processed using software algorithms internal to the microcomputer. This calculation creates a considerable computer burden.

A method for realizing corresponding control with high precision angular resolution by the apparatus of the present invention will be described. In that case, according to the invention, the period between two pulses is divided into a settable number of periods.

FIG. 1 schematically shows the device of the invention as a block diagram. The individual elements can be realized as discrete elements or as a computer.

The engine control unit 100 includes a multiple circuit 11
It is connected to the rotation speed sensor 105 via 0. The multiplier circuit 110 is further supplied with the high frequency output signal of the frequency oscillator. This signal of the frequency oscillator 115 reaches the input 122 of the first counter 120 and the input 142 of the programmable counter 140. This programmable counter 140 is also called the second counter. The first counter 120 is connected via its output 127 to the input 132 of the third counter 130. The third counter 130 is connected via its output 137 to the programming input 143 of the programmable counter 140. The rotation speed sensor 105 provides signals to the reset input 125 of the first counter 120, the reset input 135 of the third counter 130 and the reset input 144 of the programmable counter 140. The output signal 147 of the programmable counter 140 is the engine controller 100.
Is input to.

This device operates as follows. The engine control unit generates drive pulses to be supplied to various actuators of the internal combustion engine according to the pulses supplied from the rotation speed sensor. Normally, the point in time when the drive pulse is generated and, in some cases, the period thereof is determined by counting the pulses of the rotation speed sensor. A multiple circuit 110 is provided to improve the accuracy of the drive pulse. This circuit divides the interval between two pulses of the speed sensor into a settable number of intervals. This means that, for example, in the case of a rotation speed sensor that generates 64 pulses, the multiplier circuit has 512
Means to generate a pulse.

The multiplier circuit operates as follows. The rotational speed sensor 1 is connected to the first counter via its input 125.
When the reset pulse is input from 05, the first counter is reset to zero. The counter value of the first counter is incremented by 1 for each pulse of the frequency oscillator 115. Therefore, the counter value of the first counter is incremented by 1 at predetermined time intervals. The counter value of the first counter periodically circulates from 0 to (2 n-1). When the first counter overflows, the counter value of the third counter 130 is incremented by 1.

When the third counter 130 is pulsed from the speed sensor 105 via its input 135,
The counter value obtained is loaded into the counter 140 via its output 137 and the input 145 of the programmable counter 140. This value is stored in programmable counter 140. Programmable counter 140
When a reset pulse is provided at its input 144 through its input 144, the counter 140 is set to its programmed value. At the same time, the third counter 130 is reset to zero. For each output signal of the frequency oscillator 115, the counter value of the programmable counter 140 is decremented by 1.
That is, the counter value of programmable counter 140 is decremented by 1 at predetermined time intervals. When this counter value reaches the value 0, a pulse is output to the engine control unit 100 via its output 147 and is set to the previously stored value.

With this method, the interval between two pulses of the speed sensor can be divided into 2 n periods.

The basic idea for increasing the angular resolution is to measure the cycle length of the input signal of the multiplier circuit 110 corresponding to the output signal of the rotation speed sensor 105 as follows. That is, the frequency oscillator 11 for one cycle of the signal corresponding to the interval between the two pulses of the rotation speed sensor 105.
The number of pulses of the high frequency output signal of 5 is counted by the cascaded counters 120-130.

The programmable counter 140 clocked at a clock frequency that is a power of 2 times higher than the third counter 130 has a third counter at the end of the period length measurement.
, By a coefficient corresponding to the counter value of the counter 130, thereby producing a signal at the output with a resolution that is 2n times greater than the input signal.

What is important is that the predetermined time interval for increasing the counter value of the first counter is much shorter than the cycle length (pulse interval) of the rotation speed signal. This means that the frequency of the frequency oscillator 115 is equal to the rotation speed sensor 105.
It means that it must be much higher than the signal frequency of. At the maximum permissible rotational speed, the frequency of the frequency oscillator should be greater than the frequency of the rotational speed sensor by about 2n times.

To further explain the function, refer to FIG. In FIG. 2A, the output signal of the rotation speed sensor 105 is shown, and here only one cycle length is shown. FIG. 2B shows the output signal of the frequency oscillator 115. Only four pulses are listed. The other pulses are omitted for simplicity, but continue at the same intervals as shown. The first is shown in FIG.
The counter value of the counter 120 of FIG.
2E, the counter value of the programmable counter 140 is shown in FIG. 2E. FIG. 2F shows the output signal of the multiplier circuit 110, which is the same as the input signal of the engine control device 110. FIG. 2 (g) shows the signal when the division is optimal.

The first counter cyclically cycles from a counter value of 0 to 2 to the nth power -1. In this example, n has the value 3. Each time the first counter 120 overflows, the counter value of the third counter 130 starts from 0 and increases by 1. When the next pulse of signal is generated by the speed sensor 105, the programmable counter 140 is loaded with the counter value of the third counter 130. In the present example this is a value of 8. This counter cycles cyclically from a counter value of 8 to 1. This counter generates a pulse each time it overflows. This pulse is shown in FIG. 2 (f). Figure 2
The number of pulses for each signal period in (a) is 2 n.

In this method, the multiplier circuit only evaluates the period length before the period to be divided. The programmable counter 140 is loaded with the counter value obtained in the third counter 130 in the preceding cycle. As a result, the dynamic characteristics are remarkably improved when the frequency of the output signal of the rotation speed sensor is changed, as compared with a so-called phase locked loop (PLL).

According to this method, the output signal of the rotation speed sensor is divided into a predetermined number of pulses having a substantially uniform cycle length. FIG. 2 (g) shows values in the case of optimal even division. As is clear from the figure, the pulse output from the multiplier circuit is slightly deviated from this optimum value.

This deviation is due to the fact that the first counter usually has not yet reached the maximum counter value when the rpm sensor pulse is generated. Thereby, FIG.
As shown in (a), the programmable counter 140 has not yet been reset to zero when the pulse occurs,
This causes the interval between the last pulse and the first pulse to be longer than the interval between other pulses.

This inaccuracy is significantly reduced by the device shown in FIG. In addition to the configuration shown in FIG. 1, the device shown in FIG. 3 is further provided with a second programmable counter 300. This counter is connected via its input 302 to the output 147 of the programmable counter 140. Counter 300 also provides a signal to programmable counter 140 via its output 308. The output signal of the rotation speed sensor 105 is applied to the counter 300 via its input 306. Counter 300
Is loaded with the counter value of the first counter 120 via input 304.

This device operates as follows. Each time the output of programmable counter 140 is pulsed, the counter value of second programmable counter 300 is decremented by one. When the pulse of the rotation speed sensor 105 is generated, the counter value of the first counter 120 is loaded in the counter 300. While the counter value of the second programmable counter is> 0, the programmable counter 140 is switched to count counter values up to 0 instead of up to 1. That is, only one extra pulse is counted. In this way, each of the first (n2 + 1) output pulses of programmable counter 140 is extended by one clock pulse of the frequency oscillator. In that case, n2 is the counter value of the counter 120 loaded into the programmable counter 300.

When the second programmable counter 300 reaches the value 0, the programmable counter 140 switches to the normal sequence. The position error of the individual pulses is thus reduced. The maximum possible error is only a quarter of the value for the device shown in FIG.

Alternatively, instead of switching the counting sequence, individual clock pulses of programmable counter 140 can be erased. With this configuration, error correction is performed during the first (n2 + 1) pulses of the programmable counter 140 output signal. Alternatively, the error correction can be performed at any pulse within the cycle.

The counter value is also shown in FIG. Figure 4
(A), 4 (b), 4 (c), 4 (d) and 4 (g)
2 (a), 2 (b), 2 (c), 2 (d) and 2
It corresponds to (g). In FIG. 4 (h), the counter value of the second programmable counter 300 is shown. FIG. 4 (i) shows the output 30 of the second programmable counter.
8 signals are shown. The content of the first counter 120 is read into the second programmable counter 300 each time a pulse of the speed sensor 105 is generated. This value is 3 in this embodiment. Each time the first counter overflows, the contents of the second programmable counter 300 is decremented by one. Programmable counter 30
When 0 reaches a counter value less than 0, it outputs a signal to the first programmable counter 140 as shown in FIG. 4 (i). During the absence of this signal (which means that the contents of the second programmable counter 300 is greater than or equal to 0)
Programmable counter 140 counts from a programmed value to zero.

If a signal is present (which means that the content of the second programmable counter 300 is less than 0), the first programmable counter 14
0 counts from the programmed value to 1.

Alternatively, a second programmable counter may be provided to cancel the frequency oscillator pulse at input 142 in the first step.

Further, it is possible to perform correction at any pulse within the cycle of the rotation speed sensor 105.

When the first programmable counter 140 reaches a counter value of 0 to 1, this counter outputs a pulse to the engine controller. This pulse is shown in FIG. 4 (f). Comparing with the optimal values of FIG. 4 (g), it is clear that the deviation is much smaller for this example.

[0035]

As is apparent from the above description, according to the present invention, it is possible to obtain the device capable of increasing the resolution of the rotation speed signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the device of the present invention.

FIG. 2 is a timing chart showing a count value of each counting means.

FIG. 3 is a block diagram showing the configuration of another improved embodiment.

FIG. 4 is a timing chart showing the contents of a counter in the improved embodiment.

[Explanation of symbols]

 100 Engine Control Unit 105 Rotation Speed Sensor 110 Multiple Circuit 115 High Frequency Oscillator 120 First Counter 130 Third Counter 140 Programmable Counter 300 Programmable Counter

Claims (6)

[Claims] 1. A device for increasing the resolution of a signal, particularly a rotation speed sensor signal, wherein the cycle length of the signal is obtained by a multi-stage counting means (120-130) and the interval is obtained by a multi-stage counting means An apparatus for improving the resolution of a signal, characterized in that means for generating a pulse that is a fraction of a power is provided. 2. The means for generating a pulse is at least one.
Two programmable counting means (140, 300)
The apparatus of claim 1, wherein the apparatus comprises: 3. The contents of the first counting means (120) and the contents of the second counting means (140) are changed at a predetermined time interval, and when a signal is generated, a third count is given to the second counting means (140).
The contents of the counting means (130) of the
Counting means (120) and third counting means (13
0) is reset and the first counting means (120) reaches a predetermined value,
Device according to claim 1 or 2, characterized in that the content of the third counting means (130) is changed and the second counting means (140) generates a pulse when it reaches a predetermined value (0). . 4. Device according to claim 3, characterized in that the second counting means (140) is reset to the previously loaded value after outputting the pulse. 5. The device according to claim 1, wherein the predetermined time interval is substantially shorter than the period length of the signal. 6. When a pulse is generated, the content of the first counting means (120) is loaded into the fourth counting means (300), and when the content of the first counting means (120) reaches a predetermined value. , The content of the fourth counting means (300) is changed, and while the fourth counting means (300) has not yet reached the predetermined value, the second counting means (140) outputs a predetermined value. The device according to any one of claims 1 to 5, characterized in that