JPH0463545B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for application to a semiconductor integrated circuit having a resistor part and a capacitor part, that is, a time constant element, such as a filter circuit.

At present, semiconductor integrated circuit devices incorporating a CR time constant circuit having a resistive portion and a capacitive portion, such as a filter circuit, have not yet become widely used. This is because the time constant cannot be set with high precision in conventional manufacturing methods.

However, when resistors and capacitors do not require such high precision, integrated circuits that include these resistors and capacitors as part of circuit elements have been provided.

An example is shown in FIG. 1, in which a common semiconductor substrate 1 is provided with an NPN transistor 2, a capacitive element 3, and resistive elements 4 and 5. The semiconductor substrate 1 is formed by epitaxially growing an N-type semiconductor layer 7 on a P-type substrate 6 . A P-type isolation region 8 is formed in the semiconductor layer 7 in the form of a lattice, for example, across the semiconductor layer 7.
is formed, thereby separating the portions where each of the elements 2 to 5 are formed. Further, 9, 10 and 11 are transistor 2 and resistor elements 4 and 5, respectively.
This is the embedded area. 12 is an insulating layer formed on the surface of the base 1, such as SiO ₂ . transistor 2
For example, an N-type semiconductor layer portion 13 surrounded by an isolation region 8 is used as a collector region, and a P-type base region 14 and an N-type emitter region are respectively formed by diffusion on this collector region. 15.

Resistance element 4 is constituted by a resistance layer 16 formed at the same time as the base region 14 is diffused. The other resistor element 5 is made of low resistivity polycrystalline silicon on an insulating layer 12 formed on the surface of the base 1 between regions 17 and 18 formed at the same time as the diffusion of the base region 14 as terminal regions at both ends of the resistor. A resistive layer 19 consisting of the following is deposited and constructed. Further, the capacitive element 3 is, for example, an emitter region 15 of the transistor 2.
The region 20 formed during the diffusion is used as one electrode, and the thin oxide film 21 formed on the region 20 during the diffusion is used as a dielectric layer, and an electrode metal layer 22 such as Al is deposited on this. A capacitance C is formed between this region 20 and the region 20 that opposes this with the dielectric layer 21 in between. This electrode metal layer 22 is ohmicly connected to one end of the resistance layer 16. 23
is the other electrode of the resistor element 4, 24 is the terminal electrode of the region 20 of the capacitor 3, 25, 26 and 27 are the collector, base and emitter electrodes of the transistor 2, respectively, and the other end of the emitter electrode 27 is the terminal electrode of the region 20 of the capacitor 3. 5
The terminal area 18 is ohmicly connected to the terminal area 18 of the terminal area 18. Note that if the resistance element 4 or the capacitor element 3 is intended to have higher precision, the resistance layer 16 may be formed by, for example, boron ion implantation in a process different from the above-described diffusion process of the base region 14. The dielectric layer 21 of the capacitive element 3 is formed under reduced pressure, which is different from the oxide film formed by the above-mentioned diffusion process.
It is formed by CVD method (low pressure chemical vapor deposition method) or oxidation treatment.

However, in either case, these resistors and capacitors are generally manufactured independently in separate processes and operations, so their resistance and capacitance values vary independently. If the time constant is determined based on both of them because they have no relationship, it is extremely difficult to set the time constant accurately and with good reproducibility.

On the other hand, since each value of resistance and capacitance can be set to a value with relatively no variation in sheet resistance and dielectric constant, it is rather likely that geometric factors are the cause of variation in these resistance and capacitance values. It's summery. For example, regarding the resistance value R, this is given by R=ρ _s ·l/W (1). Here ρ _s is the sheet resistance, W and l
are the width and length of the resistance layer 16, and fluctuation is a problem for these W and l as well. That is, the formation of the resistive layer 16 involves forming an insulating layer such as SiO ₂ on the surface of the substrate 1, which serves as a mask layer for diffusion or ion implantation, and forming an opening in this for selective doping by diffusion of impurities or ion implantation. This opening is usually made by photoetching, and the photoresist is exposed to light, developed and
Relatively large variations occur due to errors in etching of the SiO ₂ mask layer, etc. This also applies to the capacitance C.

In the present invention, such drawbacks can be effectively avoided, the CR time constant can be set with high precision, and a semiconductor integrated circuit with a built-in filter circuit etc. can be obtained. The present invention provides a semiconductor device that can perform the following steps.

An example of a manufacturing method for obtaining a semiconductor device according to the present invention will be explained in detail with reference to FIG. 2 and subsequent figures. In the illustrated example, an integrated circuit having a capacitor and a resistor is obtained, but only the capacitor part and the resistor part are shown in the figure.

In this example as well, as shown in FIG. 2, a semiconductor substrate 33 is formed in which an N-type semiconductor layer 32 is epitaxially grown on a P-type substrate 31, and a lattice pattern is formed across the semiconductor layer 32. A P-type isolation region 34 is formed, thereby separating each circuit element, in this example, portions 32A and 32B which become a capacitor portion and a resistor portion. Reference numeral 35 denotes an N-type buried region provided between the substrate 31 and the semiconductor layer 32 in the portion 32B. For example, although not shown, a high impurity concentration region 36 is selectively formed on the semiconductor layer 32 in the portion 32A, which is formed at the same time as the diffusion of the emitter region of an NPN transistor as another circuit element. For example, a pair of highly doped terminal regions 37 and 38 are provided which are selectively formed simultaneously with the formation of a low resistivity diffusion region for base electrode contact to the base region of an NPN transistor. An insulating layer 39 made of SiO ₂ or the like is deposited on the surface of the base 33 . In the present invention, openings 40 and 41 for forming the capacitive part and the resistive part are simultaneously formed in the portion of the insulating layer 39 where the capacitive part and the resistive part are to be formed. In other words, the high concentration region 3 provided in the portion 32A
Openings 40 and 41 are simultaneously formed on the terminal area 6 and in the portion 32B spanning both the terminal areas 37 and 38, respectively, by, for example, photoetching in the same operation.

In this case, assuming that the width and length of the opening 41 forming the resistance portion are W ₁ and L ₁ , respectively, the configuration is such that W ₁ <<L ₁ . That is, the pattern is formed so that the length (L ₁ ) in the direction along the plane of the paper in FIG. 2 is sufficiently larger than the width (W ₁ ) in the direction perpendicular to the plane of the paper in FIG. 2 .

Next, as shown in FIG. 3, for example, the base 1 is thermally oxidized to form a thin SiO ₂ dielectric layer 42 in both openings 40 and 41, which will eventually become, for example, the first dielectric layer of the capacitive element. Form.

As shown in FIG. 4, a Si ₃ N ₄ dielectric layer 4 that will eventually become, for example, the second dielectric layer of the capacitor
3 on the entire surface.

As shown in FIG. 5, the Si ₃ N ₄ layer 43 is
Leave the part that covers 0 and remove the other part by etching. In this selective etching, a photoresist layer 44 is applied on the dielectric layer 43, exposed and developed to form a predetermined pattern, and the dielectric layer 43 is etched using the photoresist layer 44 as a mask. Next, boron ions as a P-type impurity are implanted into the portion 32B through the opening 41 using the insulating layer 39 as a mask, as shown by the broken line arrow.
A resistive layer 60 is formed spanning between regions 37 and 38. In this case, since the resist layer 44 is formed to cover the opening 40, ions are not implanted into this portion.

As shown in FIG. 6, after the resist layer 44 is peeled off, an insulating layer 45 for passivation, such as a SiO ₂ layer, is deposited over the entire surface by chemical vapor deposition or the like. After that, annealing treatment is performed in a N ₂ atmosphere at, for example, 900°C.

Next, as shown in FIG. 7, an insulating layer 45, a dielectric layer 42 below this, and an insulating layer 3 below this.
9, electrode windows are formed by photoetching or the like. In the illustrated example, electrode windows 46, 47, and 48 for ohmic contact are formed in areas 36, 37, and 38, respectively, and in areas where the opening 40 is not formed on area 36, and on areas 37 and 38, respectively. , and an insulating layer 4 for passivation over the opening 40.
A window 49 is bored only in 5, and these windows 46, 47,
48 to make ohmic contact with each region 36, 37, 38. For example, each electrode 50, 51, 52 is formed of an Al metal layer. In the illustrated example, the electrode 51 is inserted into the SiO ₂ layer 42 through the opening 40.
and Si ₃ N ₄ layer 43 to form a capacitance C between them by extending to face region 36 via a dielectric layer having a two-layer structure consisting of Si 3 N 4 layer 43. That is, the target capacitive element 5 has a capacitance C formed between the electrodes 50 and 51.
3. Furthermore, a semiconductor integrated circuit 55 is obtained in which a target resistance element 54 having a resistance value R is formed by a resistance layer 60 between electrodes 51 and 52.

The dielectric constant and thickness of the dielectric layer in the capacitive element 53 configured in this way, that is, the dielectric layer made of the SiO ₂ layer 42 and the Si ₃ N ₄ layer 44 in the above example, can be kept constant with good reproducibility. Furthermore, if the sheet resistance of the resistance layer 60 of the resistance element 54 is similarly constant with good reproducibility, the geometric dimensions of the dielectric layer and the low antibody layer are determined as described at the beginning. is an important factor in determining the capacitance value and resistance value, but as mentioned above, the errors that occur when forming these openings 40 and 41 at the same time are By allowing this to occur, the CR time constant can be compensated to a predetermined value. That is, considering the case where the openings 40 and 41 are rectangular for convenience of explanation, the width and length of these rectangular openings 40 and 41 are respectively W ₀ , W ₁ and L ₀ , L _{1 .}
When the deviation in _the width direction is ΔW and the deviation in the length direction is ΔL, the capacitance C and resistance R are CεLoWo/d(1+ΔL/Lo+ΔW/Wo)...(2) However, d is the dielectric layer The thickness, ε, is its dielectric constant.

RρsL ₁ /W ₁ (1-|ΔL'|/L ₁ -ΔW/W ₁ ...(3) where ΔL' is the opening 4 that constitutes the resistance section.
1 shows the sum of the displacement in the length direction that occurs during so-called patterning of the opening 41 and the displacement that occurs due to the lengths of the terminal regions 37 and 38 at both ends of the resistive layer 60 provided in the opening 41. In other words, the length L that regulates the resistance R
is the value obtained by subtracting the length of the terminal areas 37 and 38 from the length of the opening 41.
Since the lengths of and 38 are actually set to be sufficiently smaller than the length of the opening 41, they can be expressed as ΔL' including the above-mentioned deviation during patterning. and this terminal area 37 and 38
The amount of deviation caused by this is always larger than the amount of deviation during patterning, and in this case, the length of the opening 41
Since the deviation is caused in the direction of decreasing _L1 , the sign of the deviation amount ΔL' due to the sum of these is always − (minus).

In this case, since the width W ₁ and the length L ₁ of the opening 41 of the resistor part are set as W ₁ <<L ₁ as described above, the resistance R can be expressed by the following equation (3)'. be done.

RρsL ₁ /W ₁ (1−ΔW ₁ /W ₁ ) ……(3)′ Now considering the case where the pattern is Wo≪Lo, CεLoWo/d(1+ΔW/Wo) ……(4). Therefore, if ΔW is infinitesimal, then RCρsL ₁ /W ₁・εLoWo/d・(1−ΔW/W ₁ +ΔW/Wo
) ...(5) becomes. Therefore, in this case, if W ₀ =W ₁ , the dimensional error can be compensated for.

Also, considering the case of a WoLo pattern, CεLoWo/d(1+2ΔW/Wo)...(6). Therefore, RCρsL ₁ /W ₁・εLoWo/d・(1−ΔW/W ₁ +2ΔW/Wo
) ...(7) becomes. Therefore, in this case, the dimensional error can be compensated by setting 2W ₁ =WoLo.

As described above, according to the configuration of the present invention, the capacitor part,
That is, the opening 40 for forming the pattern of the dielectric layer constituting the capacitive element and the opening 41 for forming the pattern of the resistive layer constituting the resistive part, that is, the resistive element, are formed simultaneously. By making geometric errors occur with the same tendency, it is possible to compensate for errors in CR values caused by these errors. In addition, since the filter circuit can be built into a common semiconductor substrate and configured as an integrated circuit, assembly and manufacturing can be simplified and the size can be reduced compared to the case where such a filter circuit is configured as a separate structure.

In addition, the configuration of the device of the present invention and the manufacturing method for obtaining the same are not limited to the above-mentioned example, and various aspects can be adopted.For example, the conductivity type of each part can be set to a conductivity type opposite to that of the illustrated example. , explained in Figure 3.
_After omitting the formation of the SiO ₂ layer 42 and forming the Si ₂ N ₄ layer 43 over the entire surface, implanting boron, for example, as explained in _FIG . 6 and 7, leaving only one opening 40 closed.
The desired semiconductor device can also be obtained by a method similar to that explained in the drawings. In this case, the dielectric layer of the capacitive element 53 is a single layer of Si ₃ N ₄ layer 43.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a portion of an example of a semiconductor device, and FIGS. 2 to 7 are process diagrams of an example of a manufacturing method for obtaining the device of the present invention. 33 is a semiconductor substrate, and 53 and 54 are a capacitive element and a resistive element, respectively.

Claims (1)

[Claims] 1. A first terminal region on a semiconductor substrate and a second terminal region of a pair of conductivity types opposite to that of the resistor forming region of the semiconductor substrate.
an insulating layer is formed on the first terminal area and the second terminal area, and an insulating layer is formed on the first terminal area of the insulating layer and on the second terminal area of the pair. and an opening constituting a capacitive part and an opening constituting a resistive part are simultaneously formed between the second terminal regions of the pair, respectively, and an electrode is formed on the opening constituting the capacitive part via a dielectric layer. is provided to constitute a capacitor section, and the second of the pair is
A semiconductor device in which a resistor layer is provided between terminal regions of the resistor section to configure a resistor section, and an electrode of the capacitor section and one terminal region of the resistor section are electrically connected to configure a time constant circuit. In, if the pattern of the openings forming the capacitive part is rectangular and the long side is sufficiently longer than the short side, the width of the opening pattern forming the resistive part and the width of the opening pattern forming the capacitive part are or, if the pattern of openings constituting the capacitance section is approximately square, the width of the pattern of openings constituting the resistor section is equal to the width of the pattern of openings constituting the capacitance section. A semiconductor device characterized in that it is approximately one-half the size.