JPH04326562A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04326562A JPH04326562A JP9599991A JP9599991A JPH04326562A JP H04326562 A JPH04326562 A JP H04326562A JP 9599991 A JP9599991 A JP 9599991A JP 9599991 A JP9599991 A JP 9599991A JP H04326562 A JPH04326562 A JP H04326562A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuit pattern
- insulating film
- lead
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000005516 engineering process Methods 0.000 claims abstract description 10
- 238000001459 lithography Methods 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 10
- 239000010949 copper Substances 0.000 abstract description 10
- 238000000605 extraction Methods 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000007789 sealing Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置に関し、特に
樹脂封止型の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
【0002】0002
【従来の技術】従来の半導体装置は、図2に示すように
、内部リード12と外部リード13とを有するリードフ
レーム1のアイランド部11に半導体チップ2を搭載し
、半導体チップ2上のパッド21と内部リード12との
間をボンデンイング線7により接続した後、封止用樹脂
をモールドしてパッケージ6を形成するという構成であ
った。2. Description of the Related Art As shown in FIG. 2, a conventional semiconductor device has a semiconductor chip 2 mounted on an island portion 11 of a lead frame 1 having internal leads 12 and external leads 13. The package 6 was formed by connecting the bonding wire 7 and the internal lead 12, and then molding a sealing resin.
【0003】リードフレーム1のパターンは、プレス技
術またはエッチング技術により形成する。また、ボンデ
イング線7の線長は樹脂封止時における変形や切断等の
不具合を避けるため最大3.5mm程度とする必要があ
る。[0003] The pattern of the lead frame 1 is formed by pressing technology or etching technology. Further, the wire length of the bonding wire 7 needs to be approximately 3.5 mm at maximum in order to avoid problems such as deformation and cutting during resin sealing.
【0004】したがって、半導体チップ2が小型であり
、また、端子数、すなわち、ボンデイング用のパッド2
1の数が多い場合には、半導体チップ2の寸法に合わせ
、ボンデイング線7の線長が3.5mmを越えないよう
にリードフレーム1の内部リード12のパターンを設計
する必要がある。このような場合には、内部リード12
は中心に向かって長く形成され、その終端における中心
間距離、すなわち、ピッチが非常に小さく、たとえば、
0.15mm以下となる。また、ボンデンイング線7に
よるボンデンイグに必要な内部リード12の最小幅は約
0.1mmである。Therefore, the semiconductor chip 2 is small, and the number of terminals, that is, the number of bonding pads 2 is small.
If the number of 1's is large, it is necessary to design the pattern of the internal leads 12 of the lead frame 1 in accordance with the dimensions of the semiconductor chip 2 so that the line length of the bonding line 7 does not exceed 3.5 mm. In such a case, the internal lead 12
is formed long toward the center, and the center-to-center distance at its end, that is, the pitch, is very small, for example,
It becomes 0.15 mm or less. Further, the minimum width of the internal lead 12 necessary for bonding using the bonding wire 7 is about 0.1 mm.
【0005】一方、現状のリードフレーム1のパターン
の加工技術では、プレス技術またはエッチング技術のい
ずれの場合でも、内部リード12の側面間距離、すなわ
ち、抜き幅は板厚の70%程度である。これは、たとえ
ば、板厚0.15mmとすれば、0.105mmとなる
。上述のように、ピッチを0.15mmとすれば、この
抜き幅0.105mmを考慮すると、内部リードの終端
幅としてはわずか0.045mmしか確保できない。
この寸法では、ボンデンイグ最小幅の0.1mmより小
さいので、ボンデイングは不可能である。[0005] On the other hand, in the current processing technology for patterning the lead frame 1, whether by pressing technology or etching technology, the distance between the side surfaces of the internal leads 12, that is, the punching width is about 70% of the plate thickness. For example, if the plate thickness is 0.15 mm, this becomes 0.105 mm. As mentioned above, if the pitch is 0.15 mm, taking into consideration this punching width of 0.105 mm, only 0.045 mm can be secured as the terminal width of the internal lead. With this dimension, bonding is impossible because it is smaller than the minimum bonding width of 0.1 mm.
【0006】また、半導体装置の高機能化、高集積度化
等により、消費電力が増大するという動向がある。この
ため、半導体チップの発熱が大きくなり、その放熱設計
を適切に行なう必要があるというものであった。[0006] Furthermore, as semiconductor devices become more sophisticated and highly integrated, there is a trend toward increased power consumption. For this reason, the semiconductor chip generates a large amount of heat, and it is necessary to appropriately design the heat dissipation.
【0007】[0007]
【発明が解決しようとする課題】上述した従来の半導体
装置は、半導体チップが小型で端子数が多い場合には、
内部リードの終端におけるピッチが非常に小さくなるの
で、半導体チップの最小寸法や端子数において制約を受
けるという欠点があった。また、内部リードの終端にお
けるピッチを小さく設計すると、ボンデンイグ最小幅を
確保するため抜き幅を小さくするよう内部リードの板厚
を小さくする必要があり、リードの強度が保持できず加
工時に折損するという欠点があった。さらに、高消費電
力の半導体チップの放熱を効率よく行なうことが困難で
あるという欠点があった。[Problems to be Solved by the Invention] In the conventional semiconductor device described above, when the semiconductor chip is small and has a large number of terminals,
Since the pitch at the end of the internal leads becomes very small, there is a drawback that there are restrictions on the minimum size of the semiconductor chip and the number of terminals. In addition, if the pitch at the end of the internal leads is designed to be small, the thickness of the internal leads must be reduced to reduce the width of the cutout in order to ensure the minimum bonding width, and the strength of the leads cannot be maintained and may break during processing. There were drawbacks. Furthermore, there is a drawback that it is difficult to efficiently dissipate heat from a semiconductor chip that consumes high power.
【0008】[0008]
【課題を解決するための手段】本発明の半導体装置は、
上面に絶縁膜を形成しこの絶縁膜の中央部に半導体チッ
プを搭載する半導体チップ搭載部を設けこの半導体チッ
プ搭載部の周囲部分にリソグラフイ技術により形成した
前記半導体チップとリードフレームの内部リードとの電
気的接続用の回路パターンを有する金属板を備えて構成
されている。[Means for Solving the Problems] A semiconductor device of the present invention includes:
An insulating film is formed on the upper surface, a semiconductor chip mounting part for mounting a semiconductor chip is provided in the center of the insulating film, and the semiconductor chip and internal leads of the lead frame are formed around the semiconductor chip mounting part by lithography technology. The metal plate has a circuit pattern for electrical connection.
【0009】[0009]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments Next, embodiments of the present invention will be described with reference to the drawings.
【0010】図1は本発明の半導体装置の一実施例を示
す(A)は部分破断平面図、(B)は(A)のA−B線
における断面図である。FIG. 1 shows an embodiment of a semiconductor device according to the present invention, in which (A) is a partially cutaway plan view and (B) is a cross-sectional view taken along the line AB in (A).
【0011】本実施例の半導体装置は、図1に示すよう
に、内部リード12と外部リード13とを有するリード
フレーム1のアイランド部11に、銅板3を接着し、銅
板3の上面に数μmの厚さでシリコン酸化膜等の絶縁膜
4を形成し、絶縁膜4上にアルミニュームや金あるいは
銀等の金属を蒸着し、リソグラフイ技術を用いて回路パ
ターン5を形成して、回路パターン5上の中央部に半導
体チップ2を搭載し、半導体チップ2上のパッド21と
回路パターン5との間をボンデンイング線8により接続
して、回路パターン5と内部リード12との間をボンデ
ンイング線7により接続後、封止用樹脂をモールドして
パッケージ6を形成するという構成である。As shown in FIG. 1, in the semiconductor device of this embodiment, a copper plate 3 is bonded to an island portion 11 of a lead frame 1 having an internal lead 12 and an external lead 13, and a distance of several μm is placed on the top surface of the copper plate 3. An insulating film 4 such as a silicon oxide film is formed to a thickness of The semiconductor chip 2 is mounted on the center part on the semiconductor chip 2, and the pads 21 on the semiconductor chip 2 and the circuit pattern 5 are connected by the bonding wire 8, and the bonding is performed between the circuit pattern 5 and the internal leads 12. After connecting through wires 7, a sealing resin is molded to form a package 6.
【0012】本実施例では、内部リード12の終端とし
て絶縁膜4上にリソグラフイ技術を用いて形成した回路
パターン5を用いているので、回路パターン5の側面間
距離、すなわち、抜き幅を極めて小さくすることができ
、一例として、0.01mm程度にすることが可能であ
る。したがって、従来例と同様の0.1mmのボンデン
イグ最小幅を確保しても、回路パターン5のピッチを0
.11mmまで小さくすることが可能である。In this embodiment, since the circuit pattern 5 formed on the insulating film 4 using lithography technology is used as the termination of the internal lead 12, the distance between the sides of the circuit pattern 5, that is, the width of the cutout can be minimized. It can be made small, for example, about 0.01 mm. Therefore, even if the minimum bond width of 0.1 mm is secured as in the conventional example, the pitch of the circuit pattern 5 is reduced to 0.
.. It is possible to make it as small as 11 mm.
【0013】また、熱伝導率の高い銅板3をリードフレ
ーム1のアイランド部11上に接着し、この上に半導体
チップ2を搭載する構成となっているので、半導体チッ
プ2で発生する熱は効率よく外部に放熱されることにな
る。Furthermore, since the copper plate 3 with high thermal conductivity is bonded onto the island portion 11 of the lead frame 1 and the semiconductor chip 2 is mounted on this, the heat generated by the semiconductor chip 2 is efficiently dissipated. Heat is often radiated to the outside.
【0014】たとえば、半導体チップ面積を25平方m
m、リードフレームの厚さを0.15mm、リードフレ
ームの熱伝導率を0.36cal/cm/s/℃、銅板
の面積を225平方mm、銅板の厚さを1mm、銅板の
熱伝導率を0.50cal/cm/s/℃、樹脂の熱伝
導率を0.0016cal/cm/s/℃、パッケージ
の寸法を40×40×4.2mmとし、296ピンクワ
ッドフラットパッケージでは次のように改善される。す
なわち、従来の構造では、熱抵抗が70℃/Wであるの
に対し、本実施例の構造では45℃/Wとなる。For example, if the semiconductor chip area is 25 square meters
m, the thickness of the lead frame is 0.15 mm, the thermal conductivity of the lead frame is 0.36 cal/cm/s/℃, the area of the copper plate is 225 square mm, the thickness of the copper plate is 1 mm, the thermal conductivity of the copper plate is 0.50 cal/cm/s/℃, the thermal conductivity of the resin is 0.0016 cal/cm/s/℃, the package dimensions are 40 x 40 x 4.2 mm, and the 296 pin quad flat package has the following improvements. be done. That is, while the conventional structure has a thermal resistance of 70° C./W, the structure of this embodiment has a thermal resistance of 45° C./W.
【0015】以上、本発明の実施例を説明したが、本発
明は上記実施例に限られることなく種々の変形が可能で
ある。Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be modified in various ways.
【0016】たとえば、アイランド部に回路パターンを
形成した銅板を搭載し回路パターンと内部リードとをボ
ンデイング線で接続する代りに、アイランド部を省略し
銅板上の回路パターンと内部リードとを直接半田等で接
着する方法も本発明の主旨を逸脱しない限り適用できる
ことは勿論である。For example, instead of mounting a copper plate with a circuit pattern formed on the island part and connecting the circuit pattern and internal leads with a bonding wire, the island part is omitted and the circuit pattern on the copper plate and the internal leads are directly connected by soldering, etc. It goes without saying that the method of adhesion can also be applied as long as it does not depart from the gist of the present invention.
【0017】[0017]
【発明の効果】以上説明したように、本発明の半導体装
置は、上面に絶縁膜を形成した金属板を備え、絶縁膜上
の周囲部分にリソグラフイ技術により形成した半導体チ
ップと内部リードとの電気的接続用の回路パターンを有
することにより、半導体チップの最小寸法や端子数にお
ける制約が大幅に緩和でき小型で端子数が多い半導体装
置を提供できるという効果がある。また、内部リードの
終端におけるピッチを小さくしてもリードの強度を保持
して信頼性が高くできるという効果がある。さらに、高
消費電力の半導体チップの放熱を高効率に行なうことが
できるという効果がある。As explained above, the semiconductor device of the present invention includes a metal plate with an insulating film formed on the upper surface, and a semiconductor chip and internal leads formed on the surrounding area of the insulating film by lithography technology. By having a circuit pattern for electrical connection, restrictions on the minimum size of a semiconductor chip and the number of terminals can be significantly relaxed, and a semiconductor device that is small and has a large number of terminals can be provided. Further, even if the pitch at the end of the internal leads is reduced, the strength of the leads can be maintained and reliability can be increased. Furthermore, there is an effect that heat can be dissipated from a semiconductor chip with high power consumption with high efficiency.
【図1】本発明の半導体装置の一実施例を示す部分破断
平面図および断面図である。FIG. 1 is a partially cutaway plan view and a sectional view showing an embodiment of a semiconductor device of the present invention.
【図2】従来の半導体装置の一例を示す部分破断平面図
および断面図である。FIG. 2 is a partially cutaway plan view and a cross-sectional view showing an example of a conventional semiconductor device.
1 リードフレーム 2 半導体チップ 3 銅板 4 絶縁膜 5 回路パターン 6 パッケージ 7,8 ボンデンイング線 11 アイランド部 12 内部リード 13 外部リード 21 パッド 1 Lead frame 2 Semiconductor chip 3 Copper plate 4 Insulating film 5 Circuit pattern 6 Package 7, 8 Bonding wire 11 Island part 12 Internal lead 13 External lead 21 Pad
Claims (1)
央部に半導体チップを搭載する半導体チップ搭載部を設
けこの半導体チップ搭載部の周囲部分にリソグラフイ技
術により形成した前記半導体チップとリードフレームの
内部リードとの電気的接続用の回路パターンを有する金
属板を備えることを特徴とする半導体装置。1. An insulating film is formed on the upper surface, a semiconductor chip mounting part for mounting a semiconductor chip is provided in the center of the insulating film, and the semiconductor chip and leads are formed around the semiconductor chip mounting part by lithography technology. A semiconductor device comprising a metal plate having a circuit pattern for electrical connection with an internal lead of a frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9599991A JPH04326562A (en) | 1991-04-26 | 1991-04-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9599991A JPH04326562A (en) | 1991-04-26 | 1991-04-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04326562A true JPH04326562A (en) | 1992-11-16 |
Family
ID=14152795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9599991A Pending JPH04326562A (en) | 1991-04-26 | 1991-04-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04326562A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009194373A (en) * | 2008-01-15 | 2009-08-27 | Dainippon Printing Co Ltd | Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-encapsulated semiconductor device |
-
1991
- 1991-04-26 JP JP9599991A patent/JPH04326562A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009194373A (en) * | 2008-01-15 | 2009-08-27 | Dainippon Printing Co Ltd | Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-encapsulated semiconductor device |
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