JPH04257974A - Crossing-over evaluating system for logical design evaluation system - Google Patents

Abstract

PURPOSE:To evaluate the validity of dispatch information or the like for crossing-over between a software logic(SW) simulator and a hardware(HW) simulator and the coding error of an instruction to apply timing for crossing- over before evaluating the design of an HW by the SW simulator and the HW simulator. CONSTITUTION:This system connects a first SW logic simulator 1 as an instruction level simulator to an HW logic simulator 3 as an evaluation object and evaluates device logic on the HW logic simulator while exchanging the contents of a memory 11 and the contents of an SW visible register 12 each other, and in place of the HW logic simulator, a second SW logic simulator 2 is provided with a model information receiving means 23 provided at the HW logic simulator, model information transmitting means 26, simulation executing means 25 to execute simulation at an instruction level, and simulation ending means 25.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an evaluation method for a logic design evaluation system, and more particularly to an evaluation method for switching between a software (SW) simulator and a hardware logic (HW) simulator.

0002

[Prior Art] Conventionally, this type of logic design evaluation system combines a SW simulator and a HW simulator, and executes a part of the instructions under test, which is about a few percent of the total number of steps of a test program, on a logic-level HW simulator. By simulating the remaining parts, which account for most of the steps, such as monitor processing, pre-test processing, and post-test processing, at the instruction level rather than the logic level, the SW simulator is several hundred times faster than the HW simulator. Therefore, there is an evaluation method that effectively evaluates the logic design on a HW simulator (for example, "Effective logic verification using an ultrahigh-speed simulator (HAL)" Information Processing Society of Japan 37th (late 1988) National Conference Paper reference).

0003

[Problems to be Solved by the Invention] The conventional logic design evaluation system described above cannot operate unless the logic design is completed, so the transfer process is evaluated at the same time as the logic design evaluation. In order to proceed with the logical design evaluation while isolating whether it is a problem of switching between the SW simulator and the HW simulator, it is not only necessary to consider the scope of trouble analysis to include evaluation tools.
There were some problems that took time to troubleshoot.

0004

[Means for Solving the Problems] The transfer evaluation method of the logic design evaluation system of the present invention connects a first software logic simulator, which is an instruction level simulator, and a hardware logic simulator to be evaluated. In a logic design evaluation system that evaluates device logic on the hardware logic simulator while transmitting and receiving contents of software visible registers to and from each other,
Instead of the hardware logic simulator, the hardware logic simulator has a model information receiving means, a model information sending means, and unlike the hardware logic simulator, a simulation execution means for simulating at an instruction level, and a simulation termination means. Equipped with two software logic simulators.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows the configuration of an evaluation system of a logic design evaluation system according to an embodiment of the present invention, which includes a memory model 11 storing a test program 4, a SW visible register model 12, model information receiving means 13, and a simulation execution unit. Means 14, simulation termination means 15
, a first SW simulator 1 having a model information sending means 16, a memory model 21 in which the test program 4 is stored, an SW visible register model 22, a model information receiving means 23, a simulation execution means 24, a simulation termination means 25, a model A second SW simulator 2 having an information sending means 26 is connected.

FIG. 2 also shows the test program 4 shown in FIG.
Of the first SW simulator 1 and the second SW simulator 2 that have been evaluated, the HW simulator 3 is connected to the first SW simulator 1 instead of the second SW simulator 2. The configuration of the evaluation system is shown.

FIG. 3 shows the first SW simulator 1 and the second SW simulator 1.
The processing flow of the SW simulator 2 is shown. 1st
The SW simulator 1 and the second SW simulator 2 perform an instruction fetch process 301 that retrieves an instruction stored in the memory indicated by an IC, which is one of the SW visible register models.
Subsequently, an instruction decoding process 302 that checks the instruction code of the fetched instruction, an individual instruction process 303 that performs processing according to the instruction code, an IC addition process 304 that adds the instruction word length of the instruction just executed to the IC, and a simulator. An event poller process 305 that performs polling of events including intercommunication and various event processes is repeatedly executed to perform a command-level simulation.

The test program 4 consists of test units 4-1 to 4-n as shown in FIG. Further, the general processing of the test unit is as shown in FIG. A test preprocessing 51 that prepares the test environment, a TEST-START instruction 52 that indicates the start of a test instruction, a test instruction 53 that executes a test, a TEST-END instruction 54 that indicates the end of the test instruction, and a TEST-END instruction 54 that indicates the end of the test instruction so as not to affect the next test. It consists of post-test processing 55 for restoring the test environment.

Next, an evaluation method using the test program 4 in the logic design evaluation system will be explained. The test program 4 loaded into the first SW simulator 1 shown in FIG. 2 is executed while updating the memory model 11 and SW visible register model 12. Following the test pretreatment 51 shown in FIG.
When the T command 52 is executed, the simulation termination means 1
5, the simulation in the first SW simulator 1 is ended, and the current contents of the memory model 11 and the SW visible register model 12 are sent to the HW simulator 3 by the model information sending means 16. HW simulator 3
The model information receiving means 33 of the memory model 31 and the SW visible register model 3 based on this sent information.
After setting the contents in 2, the simulation execution means 34
The test program 4 is continuously executed by the HW simulator 3. As a result, the HW simulator 3 executes the test command 53 shown in FIG. Next, HW simulator 3
When the TEST-END instruction 54 is executed above, the simulation in the HW simulator 3 is ended by the simulation ending means 35, and the contents of the current memory model 31 and SW visible register model 32 are transferred to the first SW simulator by the model information sending means 36. Send to 1. After the model information receiving means 13 of the first SW simulator 1 sets contents in the memory model 11 and the SW visible register model 12 based on the sent information, the simulation execution means 14 sets the contents of the first SW simulator 1. Continue running test program 4. As a result, the test command 53 is executed by the first SW simulator 1. In this way, the logic design is evaluated by executing only the target test instruction 53 and the TEST-END instruction 54 for control on the HW simulator 3 where the logic design is to be evaluated.

Next, the characteristics of the evaluation method of the logical design evaluation system will be explained. In place of the HW simulator 3 to be evaluated, the second SW simulator 2 shown in FIG. Only the TEST-END instruction 54 is executed. As a result, although the first SW simulator 1, which is a design evaluation tool, is evaluated using the test program 4,
TEST- which is an interface with W Simulator 3
The validity of the transfer information for transferring to the HW simulator 3 by the START instruction 52 and the transfer information for transferring from the HW simulator 3 by the TEST-END instruction 54, and the TEST-START, TES coded in the test program 4 to provide the transfer timing.
It becomes possible to evaluate the transfer between the HW simulator 3 and the first SW simulator 1 due to a coding error in the T-END command, etc., before evaluating the HW design.

[0012] The first SW simulator 1 and the second SW simulator 2 perform TEST in the individual instruction processing 303.
By supporting the -START and TEST-END instructions, the programs can be the same.

[0013]

[Effects of the Invention] As explained above, according to the present invention, S
TEST-ST provides the validity of the transfer information for switching between the W simulator and the HW simulator, and the timing of switching to be coded in the test program.
Coding errors in ART and TEST-END instructions can be evaluated before HW design evaluation using SW simulators and HW simulators, and logical design evaluation of equipment can be performed efficiently and effectively in a short period of time using expensive and small number of HW simulators. .

[Brief explanation of the drawing]

FIG. 1 is an evaluation system configuration diagram of a logical design evaluation system of the present invention.

FIG. 2 is a configuration diagram of a logical design evaluation system.

FIG. 3 shows a processing flow of the first and second SW simulators shown in FIGS. 1 and 2. FIG.

FIG. 4 shows the configuration of the test program shown in FIGS. 1 and 2.

FIG. 5 shows a test execution flow of the test programs shown in FIGS. 1, 2, and 4.

[Explanation of symbols]

1 First SW simulator 11, 21, 31 Memory model 12, 22, 3
2 SW visible register model 13, 23, 3
3 Model information receiving means 14, 24, 34
Simulation execution means 15, 25, 35
Simulation termination means 16, 26, 36 Model information sending means 2 Second SW simulator 3 HW simulator 4 Test program

Claims (1)

[Claims] 1. A first software logic simulator, which is an instruction level simulator, and a hardware logic simulator to be evaluated are connected, and the contents of the memory and the contents of the software visible register are transmitted and received on the hardware logic simulator. In the logic design evaluation system for evaluating the device logic of a second comprising a simulation executing means for simulating and a simulation terminating means;
A transfer evaluation method for a logic design evaluation system characterized by comprising a software logic simulator.