JPH0425181A - Thin film transistor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a thin film transistor memory to be simplified in manufacturing process and lessened in cost by a method wherein N-type impurities are diffused into a channel region of a semiconductor layer of the memory thin film transistor. CONSTITUTION:Both gate insulating films 12 of a memory thin film transistor T10 and a drive thin film transistor T20 are formed of an insulating layer whose surface layer is possessed of a charge storing function, and a semiconductor layer 13 is formed of the same I-type semiconductor, N-type impurities are diffused into the channel region of the semiconductor layer 13 of the drive thin film transistor T20 which is required to be very small in hysteresis of VG-ID characteristics to enable the drive thin film transistor T20 to be possessed of VG-ID characteristics very small in hysteresis. By this setup, a thin film transistor memory can be simplified in manufacturing process and lessened in cost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor memory and a method for manufacturing the same.

[Conventional technology]

Recently, as memories such as E2FROM, memory transistors and drive transistors (transistors forming the drive circuit of a memory array consisting of a large number of memory transistors, or connected to each memory transistor to selectively drive each memory transistor) have been developed. A thin film transistor memory has been developed in which a thin film transistor is used as a transistor.

FIG. 5 shows a conventional thin film transistor memory.

This thin film transistor memory has a memory thin film transistor (hereinafter referred to as a memory transistor) T+ and a driving thin film transistor (hereinafter referred to as a drive transistor) T2 formed on a substrate 1 made of glass or the like.
The memory transistor T1 includes a gate electrode G1 formed on a substrate 1, and a breakdown voltage maintaining insulating film 2a made of silicon nitride (S]N) that does not have a charge storage function, with a composition ratio of silicon atoms Si. A gate insulating film 2 having a two-layer film structure in which a memory insulating film 2b made of silicon nitride having a charge storage function is laminated, a semiconductor layer 3, an ohmic contact layer 4, and source and drain electrodes S. D
, and are laminated together. Further, the drive transistor T2 is placed on the gate electrode G2 formed on the substrate 1.
A gate insulating film 5 made of silicon nitride that does not have a charge storage function, a semiconductor layer 6, an ohmic contact layer 7, and source and drain electrodes S2. D2 is laminated. Note that the semiconductor layers 3.6 of the memory transistor T1 and the drive transistor T2 are both i-type semiconductors,
For example, it is made of i-type amorphous silicon or polysilicon (fSi), and both transistors T
,.

The ohmic contact layers 4 and 7 of T2 are both n-type semiconductors, for example, n-type semiconductors doped with n-type impurities such as phosphorus (P).
Amorphous silicon or polysilicon (n
”-8j).

Although not shown, the gate electrodes Gl+G2 of the memory transistor T1 and the drive transistor T2 are connected to a gate line formed integrally therewith, and the source electrode S1 and drain electrode D1 of the memory transistor T1 and the drive transistor The source electrode S2 and drain electrode D2 of T2 are connected to a source line and a drain line, respectively, which are integrally formed with these electrodes.

FIG. 6 shows the manufacturing method of the thin film transistor memory in the order of steps, and the memory transistor T and drive transistor T2 of this thin film transistor memory are manufactured by the following steps.

First, as shown in FIG. 6(a), a metal film such as chromium (Cr) is deposited on a substrate 1 made of glass or the like, and this metal film is patterned to form gate electrodes of the memory transistor T and the drive transistor T2. After forming G, G2 and a gate line (not shown) at the same time, on the substrate 1,
A gate insulating film 5 for a driving transistor that does not have a charge storage function, a semiconductor layer 6, an ohmic contact layer 7,
Source and drain electrodes S2+D of drive transistor T2
A metal film 8 for source and drain electrodes made of chromium or the like is sequentially deposited.

Next, as shown in FIG. 6(b), a laminated film of the gate insulating film 5 for the drive transistor, the semiconductor layer 6, the ohmic contact layer 7, and the metal film 8 for source and drain electrodes is formed by photolithography. Patterning is performed in the element shape of the drive transistor T2, and the gate electrode G of the memory transistor T1 is exposed.

Next, as shown in FIG. 6(C), on the substrate 1, an insulating film 2a for maintaining voltage resistance and a memory insulating film 2b having a charge storage function are sequentially deposited. A gate insulating film 2 for a memory transistor is formed, and a semiconductor layer 3 and an ohmic contact layer 4 are further formed thereon.
Then, a metal film 9 for source and drain electrodes, such as chromium, which will become the source and drain electrodes S, D, of the memory thin film transistor T1, is sequentially deposited.

Next, as shown in FIG. 6(d), a laminated film of the gate insulating film 2 for the memory transistor, the semiconductor layer 3, the ohmic contact layer 4, and the metal film 9 for source and drain electrodes is formed by photolithography. memory transistor T
1, and the laminated films 2, 3, 4.9 above the drive transistor 212 portion are removed.

Next, as shown in FIG. 6(e), the metal films 8 and 9 for source and drain electrodes of the memory transistor T1 portion and the drive transistor 212 portion and the ohmic contact layers 4 and 7 thereunder are patterned by photolithography. The source and drain electrodes s+ and St of the memory transistor T1, the source and drain lines (not shown), and the source and drain electrodes S2 of the drive transistor T2.
D2 and source and drain lines (not shown) are formed at the same time to complete the memory transistor T1 and drive transistor T2.

Note that in this manufacturing method, first, the stacked films (gate insulating film 5, semiconductor layer 6, ohmic contact layer 7, and metal film 9 for source and drain electrodes) constituting the drive transistor T2 are fabricated.
) is deposited and patterned into the device shape, and then a laminated film (gate insulating film 2, semiconductor layer 3, ohmic contact layer 4, and source) forming the memory transistor T is deposited and patterned into the device shape.

The metal film 8) for the drain electrode is deposited and patterned into the device shape.
The deposition and patterning of the laminated film constituting the drive transistor T2 and the laminated film constituting the drive transistor T2 may be performed in the reverse order. Further, the gate insulating film 2 of the memory transistor T1 may be a single layer film in which only the memory insulating film 2b is formed to a thickness that provides a sufficient dielectric strength.

[Problem to be solved by the invention]

However, in the conventional thin Ml-transistor memory, the gate insulating film 2 of the memory transistor T1 is an insulating film having a charge storage function (a two-layer film of an insulating film 2a for maintaining voltage resistance and an insulating film 2b having a memory property), or a film having a memory property Since the gate insulating film 5 of the drive transistor T2 is formed of an insulating film that does not have a charge storage function, the memory transistor T and the drive transistor T2 are In order to form the memory transistor T1, the gate insulating film 2, the semiconductor layer 3, the ohmic contact layer 4, and the metal film 8 for source and drain electrodes are deposited, and the drive transistor T2 is formed, as in the manufacturing method described above. a gate insulating film 5, a semiconductor layer 6, an ohmic contact layer 7, and a source.

The deposition of the metal film 9 for the drain electrode must be performed in a separate process, and therefore, the conventional thin film transistor memory has a problem in that the manufacturing process is long and the manufacturing cost is high.

The present invention has been made in view of the above circumstances, and its purpose is to provide a thin film transistor memory that can simplify the manufacturing process and reduce manufacturing costs, and also to provide a manufacturing method thereof. Our goal is to provide the following.

[Means to solve the problem]

The thin film transistor memory of the present invention includes a memory thin film transistor and a driving thin film transistor, in which a gate insulating film, a semiconductor layer, an ohmic contact layer consisting of an ohmic contact, and source and drain electrodes are laminated on a gate electrode formed on a substrate. In addition, the gate insulating films of the memory thin film transistor and the driving thin film transistor are both insulating films having a charge storage function at least in the surface layer, and the semiconductor layers of the memory thin film transistor and the driving thin film transistor are of the same i-type. It is characterized in that it is formed of a semiconductor and that an n-type impurity contained in the ohmic contact layer is diffused into a channel region of a semiconductor layer of the memory thin film transistor.

Further, the method for manufacturing a thin film transistor memory of the present invention includes:
A gate electrode of a memory thin film transistor and a driving thin film transistor is simultaneously formed on a substrate, and on the substrate on which the gate electrode is formed, a gate insulating film having a charge storage function at least on the surface layer, and a semiconductor layer made of an i-type semiconductor. , an ohmic contact layer consisting of an n-type 14 conductor,
After sequentially depositing a metal film for source and drain electrodes, the metal film for source and drain electrodes and the ohmic contact layer thereunder are patterned in the shape of the source electrode and drain electrode, and then heated. Through the treatment, the n-type impurity contained in the ohmic contact layer above the semiconductor layer is thermally diffused into the semiconductor layer, and after this heat treatment, the metal film for the source and drain electrodes of the driving thin film transistor portion and the ohmic contact layer thereunder are bonded. The method is characterized in that it is patterned into the shape of a source electrode and a drain electrode.

[Effect]

That is, in the thin film transistor memory of the present invention, both the gate insulating film of the memory thin film transistor and the gate insulating film of the driving thin film transistor are formed of an insulating film having a charge storage function at least in the surface layer, and the memory thin film transistor and the driving thin film transistor are formed with an insulating film having a charge storage function at least in the surface layer. The semiconductor layers of the thin film transistors for the memory are each made of the same i-type semiconductor, and among the thin film transistor for the memory and the thin film transistor for the drive,
By diffusing n-type impurities into the channel region of the semiconductor layer of the driving thin film transistor in which vG-ID characteristics without hysteresis are desired, this driving thin film transistor can be improved. -The ID characteristic has no hysteresis.

According to this thin film transistor memory, the gate insulating films of the memory thin film transistor and the driving thin film transistor are the same insulating film (an insulating film having a charge storage function at least in the surface layer), and the semiconductor layers of the memory thin film transistor and the driving thin film transistor are also the same. Formed with a type semiconductor,
Since n-type impurities are diffused into the channel region of the semiconductor layer of the drive thin film transistor, the gate insulating film, the semiconductor layer, the ohmic contact layer, the metal film for the source and drain electrodes, and the drive A gate insulating film, a semiconductor layer, an ohmic contact layer, and a metal film for source and drain electrodes constituting a thin film transistor can be deposited in the same process.

In addition, in this thin film transistor memory, the n-type impurity diffused into the semiconductor layer of the driving thin film transistor is the n-type impurity contained in the ohmic contact layer above this semiconductor layer, so the semiconductor layer is and ohmic contact layer and source.

By performing heat treatment after depositing the drain electrode metal film, n-type impurities can be thermally diffused into the semiconductor layer of the driving thin film transistor.

Therefore, according to the thin film transistor memory of the present invention, the manufacturing process can be simplified and the manufacturing cost can be reduced.

Further, the method for manufacturing a thin film transistor memory of the present invention includes:
After depositing the gate insulating film, semiconductor layer, ohmic contact layer, and metal film for source and drain electrodes that constitute the memory thin film transistor and drive thin film transistor in the same process, the metal film for the source and drain electrodes of only the memory thin film transistor portion is deposited. The ohmic contact layer underneath is patterned into the shape of the source electrode and drain electrode, and then the n-type impurity contained in the second ohmic contact layer is thermally diffused into the semiconductor layer by heat treatment. After the treatment, the metal film for the source and drain electrodes of the drive thin film transistor portion and the ohmic contact layer thereunder are patterned into the shapes of the source and drain electrodes.

According to this manufacturing method, prior to heat treatment for thermally diffusing n-type impurities into the semiconductor layer, the metal film for source and drain electrodes and the ohmic contact layer of the memory thin film transistor portion are patterned into the shape of the source and drain electrodes. Therefore, even if there is an ohmic contact layer on the semiconductor layer of the thin film transistor for memory, the semiconductor layer of the thin film transistor for memory contains n-type impurities only under the source and drain electrodes except for the channel region. [Thin film for memory]
The VcIo characteristics of the transistor have hysteresis depending on the charge storage function of the gate insulating film, and the metal film for the source and drain electrodes in the driving thin film transistor part and the ohmic contact layer thereunder are heated. No patterning is performed before processing, and the n-type impurity is diffused into the semiconductor layer and then patterned into the shape of the source and drain electrodes, so the channel region of the semiconductor layer in the drive thin-film transistor portion is also doped with n-type impurities. By diffusing it, the v6ID characteristics of the driving thin film transistor can be made to have no hysteresis.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 4.

FIG. 1 is a cross-sectional view of the thin film transistor memory of this embodiment. This thin film transistor memory includes a memory thin film transistor (hereinafter referred to as a memory transistor) TIO and a drive thin film transistor on one substrate made of glass or the like. (hereinafter referred to as a drive transistor) T20, and the memory I/transistor T. On the gate electrode GIO formed on the substrate 11, a gate insulating film 12, a semiconductor layer]3, an ohmic contact layer]5]4, and source and drain electrodes S, o, D, o are laminated. It is configured as follows. The gate insulating film 12 is an insulating film whose surface layer has a charge storage function, and the gate insulating film 2 is a voltage-retaining insulation film made of silicon nitride (St N) that does not have a charge storage function. On the film 12a, there is a memory insulating film 12b made of silicon nitride that has a charge storage function by increasing the composition ratio of silicon atoms Si.
It has a two-layer film structure. The semiconductor layer 13 is made of an n-type semiconductor, such as n-type amorphous silicon or polysilicon (i-8i), and the ohmic contact layer 14 is made of an n-type semiconductor, such as phosphorus (P). n-type amorphous silicon or polysilicon doped with n-type impurities (n4-3t
) is formed.

Further, the drive transistor T2o is arranged on the gate electrode G2o formed on the substrate].
A semiconductor consisting of the same gate insulating film as the gate insulating film of 1o (a two-layer film of a breakdown voltage holding insulating film 12a and a memory insulating film 12b) 12, and a memory transistor]-6 the same n-type semiconductor as the semiconductor layer 13 of T10. layer 13, an ohmic contact layer 14 made of the same n-type semiconductor as the ohmic contact layer 14 of the memory transistor T1o, and source and drain electrodes S20+.
Furthermore, the gate electrode G20 of this drive transistor T2o is formed of the same metal film as the gate electrode GIO of the memory transistor T1o, and the source and drain electrodes S20+D20 are stacked with the memory transistor T20. ,. source.

It is formed of the same metal film as the drain electrodes S, o, D, and o. Although not shown, the memory transistor T
,. and the gate electrode GIOIG of the drive transistor T20.
20 are connected to gate lines integrally formed therewith, and the source electrode SIO and drain electrode 0 of the memory transistor TIO are connected to the source electrode S20 and the drain electrode D of the drive transistor T2o.
2Q is connected to a source line and a drain line formed integrally with these electrodes, respectively.

Also, a memory transistor T. The semiconductor layer 13 of
A small amount of n is applied only to the portion below the source and drain electrodes S I Or D I O of this memory transistor Tlo.
Type impurities are diffused into the semiconductor layer 13 of the drive transistor T2o, and the entire region including the source and drain electrodes S20rD20 of the drive transistor T2o and the channel region between the source and drain electrodes S20 and D28 are diffused. A trace amount of n-type impurity is diffused throughout. The n-type impurity diffused into the semiconductor layer 13 of the memory transistor TIO and the drive transistor T2o is an n-type impurity (such as phosphorus) contained in the ohmic contact layer 14 on the semiconductor layer 13. The n-type impurity diffusion part 13a (the part shown with a dotted pattern in the figure) of No.
type silicon (n--3j).

In this way, even a small amount of n is applied to the semiconductor layer 13 of the drive transistor T2o over the entire area including its channel region.
It is this drive transistor T that diffuses the type impurity.
This is to make the VG-■D characteristics of the transistor T2o free of hysteresis by diffusing a small amount of n-type impurity into the semiconductor layer of the drive transistor T2o to make its channel region slightly n-type. Then, even if the gate insulating film 12 of the drive transistor T2o is an insulating film with a charge storage function, such as the memory insulating film 12b laminated on the breakdown voltage holding insulating film 12a, VG-1 of the drive transistor T2o is
゜Characteristics are those without hysteresis.

Note that in the semiconductor layer 13 of the memory transistor TIO,
The n-type impurity is only diffused under the source and drain electrodes SIO+DIO, and the channel region of the semiconductor layer]3 of this memory transistor T1o is an i-type semiconductor in which the n-type impurity is not diffused. Therefore, the Vo-ID characteristic of the memory transistor T1o has hysteresis according to the charge storage function of the gate insulating film 12.

2 and 3 show V6-I of the memory transistor T1o and drive transistor T2o. As shown in FIG. 2, the V6-ID characteristic of the memory transistor T1o has sufficient hysteresis as a memory element, and the V6-ID characteristic of the drive transistor T2o
As shown in FIG. 3, the ID characteristics have almost no hysteresis.

Note that the memory transistor T1o shown in FIGS. 2 and 3 and the drive!・The V6ID characteristics of the transistor T2o are as follows: The thickness of the gate insulating film 2 is 2000 mm (thickness of the insulating film 1.2a for withstand voltage is 1900 mm, the thickness of the memory insulating film 1 is 2000 mm)
The film thickness of 2b is 100), and the drain voltage VD is 10
V1 source voltage vs is OV, gate voltage V6 is +4
By changing the voltage from 0V to -40V, the memory transistor T1
This is the result of measuring the current value flowing between the source and drain electrodes S1o and D1o of the memory transistor T2o, and the current value flowing between the source and drain electrodes S20+D2o of the drive transistor T2o. Under the measurement conditions, the hysteresis width W is approximately 4
While it has a large hysteresis of .degree.V, the V6-I characteristic of the drive transistor T2o has only an extremely small hysteresis with a hysteresis width W of about 3V.

In this way, when a small amount of n-type impurity is diffused into the semiconductor layer 13 of the drive transistor T20, the hysteresis of the VC-ID characteristic of the drive transistor T2o becomes smaller. When diffused, the bandgap of this semiconductor layer 13 becomes smaller,
The difference (barrier hide) between the band gap of the semiconductor layer 13 and the band gap of the gate insulating film 12 increases,
Therefore, even if the gate insulating film 12 has a charge storage function, the effect of injecting charges between the semiconductor layer 13 and the gate insulating film 12 is almost eliminated, and the hysteresis property becomes small.

FIG. 4 shows the manufacturing method of the thin film transistor memory in the order of steps, and the memory transistor T1 and drive transistor T2 of this thin film transistor memory are manufactured in the following steps.

First, as shown in FIG. 4(a), a metal film such as chromium (Cr) is deposited on a substrate 11 made of glass or the like, and this metal film is patterned to form the gate 2 of the memory transistor TIO and the drive transistor T2o. After forming gate electrodes G1o and G2o and a gate line (not shown) at the same time, a voltage-retaining insulating film 12a made of silicon nitride and having no charge storage function is formed on the substrate 1;
A memory insulating film 12b made of silicon nitride having a charge storage function by increasing the composition ratio of silicon atoms Sj is sequentially deposited to form a gate insulating film 12 consisting of these two insulating films], 2a, and 12b. , further thereon, a semiconductor layer 13 made of an i-type semiconductor, an ohmic contact layer made of an n-type semiconductor]4, and a memory transistor T. and the source and drain electrodes S of the drive transistor T2o
,o,D,. Then, metal films 15 for source and drain electrodes, such as chromium, which become S2o and D2o are sequentially deposited.

Next, as shown in FIG. 4(b), the gate insulating film 1
2 and semiconductor layer] A laminated film of 3, an ohmic contact layer 14, and a metal film 15 for source and drain electrodes is patterned into the element shape of a memory transistor T1o and a drive transistor T2o by photolithography, and this laminated film is formed into a memory transistor. It is separated into a 110 section and a drive 1 to transistor T20 section.

Next, as shown in FIG. 4(C), a memory transistor T. The metal film 15 for the source and drain electrodes and the ohmic contact layer 14 thereunder are patterned by photolithography to form the memory transistors T and O.
The source and drain electrodes S+o+S+o of the memory transistor T and the source and drain lines (not shown) are formed.
Complete the IO.

Note that the metal film 15 for source and drain electrodes in the driving transistor 2126 portion and the ohmic contact layer 1 therebelow are
4 is left unpatterned over the entire area of the drive transistor 128.

Next, as shown in FIG. 4(c), the entire substrate 11 is heat-treated at a temperature higher than the deposition temperature of the semiconductor layer 13 and the ohmic contact layer 14, and the ohmic contact layer ( The n-type impurity (such as phosphorus) contained in the n-type semiconductor layer 14 is thermally diffused. The heating temperature in this heat treatment is
The diffusion of the n-type impurity from 4 to the semiconductor layer 13 is controlled to a very small extent. In this way, the semiconductor layer 1
When a trace amount of n-type impurity is diffused into semiconductor layer 1,
3]-3a becomes n-type silicon (nSi) with a very low degree of n-type.

In this case, the ohmic contact layer 14 is located both on the semiconductor layer 13 in the memory transistor TIO portion and on the semiconductor layer 3 in the drive transistor 2126 portion, so when the heat treatment is performed, the memory transistor 11
n contained in the ohmic contact layer 14 in the semiconductor layer 13 in the 8 part and the drive transistor 2126 part, respectively.
Type impurities are thermally diffused in the source of the memory transistor 118 portion.

Drain electrode metal film 15 and ohmic contact layer 1
4 means that the source drain electrode S
Since the semiconductor layer 13 of the memory I/transistor T1o is patterned in the shape of IO+D10,
The n-type impurity is only diffused under the source and drain electrodes S, o, D, o except for the channel region, and therefore the V, , -ID of this memory transistor T1o
The characteristics include hysteresis according to the charge storage function of the gate insulating film 12 as shown in FIG.

On the other hand, the metal film 15 for source and drain electrodes in the driving transistor 2126 portion and the ohmic contact layer 1 thereunder
4 is left unpatterned in the entire drive transistor T20 portion before the heat treatment, so that the semiconductor layer 13 in the drive transistor 2126 portion includes the source, the portion under the drain electrode S 20+ D 20, the source, N-type impurities are diffused over the entire region including the channel region between the drain electrodes S20°D20. Therefore, since the channel region of the semiconductor layer 13 of the drive transistor T20 is also slightly n-type, the drive transistor T2
Even if the gate insulating film 12 of No. 0 is an insulating film having a charge storage function, which is formed by laminating a memory insulating film 1-2b on a breakdown voltage holding insulating film 12a, the V of this drive transistor T2°
The 6-ID characteristic has no hysteresis as shown in FIG.

Next, as shown in FIG. 4(e), the metal film 5 for source and drain electrodes of the drive transistor T20 portion and the ohmic contact layer 4 therebelow are patterned by photolithography to form a drive transistor T2o. Source and drain electrodes S20+D20 and source and drain lines (not shown) are formed to complete the drive transistor T2o.

That is, the thin film transistor memory of the above embodiment is as follows:
Both the gate insulating film 12 of the memory transistor TIO and the gate insulating film 12 of the drive transistor T2o are covered with an insulating film having a charge storage function (voltage-retaining insulating film 12) on the surface layer.
The semiconductor layer 13 of the memory transistor T1o and the drive transistor T2o is formed of the same i-type semiconductor, and the memory transistor T10 and the drive transistor T
2o, V without hysteresis for good switching operation. −1, n in the channel region of the semiconductor layer 13 of the drive transistor T2o whose characteristics are desired.
By diffusing type impurities, the Vc ID characteristics of this drive transistor T2o are made to have no hysteresis.

According to this thin film transistor memory, the gate insulating film 1 of the memory transistor T1o and the drive transistor T2o is
2 are the same insulating film (an insulating film having a charge storage function on the surface layer), and the semiconductor layer 13 of the memory transistor T1o and the drive transistor T2o is also formed of the same i-type semiconductor, so that the channel of the semiconductor layer 13 of the drive transistor T2° is Since n-type impurities are diffused in the region, the gate insulating film 12, the semiconductor layer 13, the ohmic contact layer 14, the metal film 15 for source and drain electrodes, and the gate insulating film forming the drive transistor T20 constitute the memory transistor T1o. film] 2, the semiconductor layer 13, the ohmic contact layer 14, and the metal film 15 for source and drain electrodes can be deposited in the same process. In addition, in this thin film transistor memory, the n-type impurity diffused into the semiconductor layer 3 of the drive transistor T2o is the n-type impurity contained in the ohmic contact layer 4 on the semiconductor layer 3, so that the gate insulation The second part of the film 12 includes a semiconductor layer 13, an ohmic contact layer 14, and a source.

, metal film for drain electrode ] 5 is deposited and then heat-treated to form an n
Type impurities can be thermally diffused.

Therefore, according to this thin film transistor memory, the manufacturing process can be simplified and the manufacturing cost can be reduced.

Furthermore, the method for manufacturing the thin film transistor memory of the above embodiment includes the memory transistor T. and drive transistor T2
gate insulating film 12 and semiconductor layer] 3 and ohmic contact layer] 4 and metal film for source and drain electrodes 1-
5 in the same process, Memory I/Rangimeta 11
The metal film for source and drain electrodes in only 8 parts] 5 and the ohmic contact layer below] 4 is the source electrode S.

and drain electrode. After patterning into the shape of , the n-type impurity contained in the ohmic contact layer 14 thereon is thermally diffused into the semiconductor layer] 3 by heat treatment, and after this heat treatment, the source and drain electrodes of the drive transistor T2o portion are The metal film 15 and the ohmic contact layer 14 thereunder are patterned into the shapes of the source electrode S20 and the drain electrode D20.

According to this manufacturing method, prior to the heat treatment for thermally diffusing n-type impurities into the semiconductor layer 13, the memory transistor T
The metal film 15 for the source and drain electrodes and the ohmic contact layer 14 in the 10th part are connected to the source, do I twin electrode S,

, D, o, even if there is an ohmic contact layer 14 on the semiconductor layer 13 in the memory transistor TIO portion, the memory transistor T1
Semiconductor layer of o part] 3 has source and drain electrodes S+
The n-type impurity is only thermally diffused under o+D, o except for the channel region, and thus the memory transistor T,. The v6-ID characteristic has hysteresis according to the charge storage function of the gate insulating film 12,
In addition, the metal film 15 for the source and drain electrodes in the drive transistor 2128 portion and the ohmic contact I/layer 1 below it.
4 is a semiconductor layer without patterning before heat treatment] After diffusing n-type impurities into 3, source and drain electrodes S
Since the patterning is in the shape of 20+S20, n-type impurities are also diffused into the square channel region of the semiconductor layer 1B in the drive transistor 2128 portion, thereby changing the V6-ID characteristics of the drive transistor to characteristics without hysteresis. It is possible to do this.

In the embodiment described above, the gate insulating film 12 of the memory transistor TIO and the driving transistor T20 is formed on the memory insulating film 1. 2
This gate insulating film 1 is made of a two-layered film.
2 may be a single layer film in which only the memory insulating film 12b is formed to a thickness that provides sufficient dielectric strength.In short, the GaI insulating film 12 is an insulating film having a charge storage function at least in its surface layer. Good to have.

〔Effect of the invention〕

In the thin film transistor memory of the present invention, both the gate insulating film of the memory thin film transistor and the gate insulating film of the driving thin film transistor are formed of an insulating film having a charge storage function at least in the surface layer, and The semiconductor layers of the driving thin film transistors are each made of the same i-type semiconductor, and between the memory thin film transistor and the driving thin film transistor, the semiconductor layer of the driving thin film transistor is desired to have V6-ID characteristics without hysteresis. By diffusing type impurities, the VG-ID characteristics of this driving thin film transistor are made to have no hysteresis. Therefore, the thin film transistor memory of the present invention can simplify the manufacturing process and reduce the manufacturing cost. I can do it.

Further, according to the method for manufacturing a thin film transistor memory of the present invention, a thin film transistor for memory and a thin film transistor for driving
A gate insulating film, a semiconductor layer, an ohmic contact layer, and a metal film for source and drain electrodes constituting the transistor are deposited in the same process, and prior to heat treatment to thermally diffuse n-type impurities into the semiconductor layer, a thin film transistor for memory is deposited. Because the metal film for the source and drain electrodes and the ohmic contact layer are patterned in the shape of the source and drain electrodes, even if there is an ohmic contact layer on the semiconductor layer in the memory thin film transistor part, the ohmic contact layer in the memory thin film transistor part is In the semiconductor layer,
N-type impurities are only thermally diffused under the source and drain electrodes except for the channel region, and therefore the V6-ID characteristics of memory thin film transistors have hysteresis characteristics that correspond to the charge storage function of the gate insulating film. In addition, the driving thin film l, the metal film for the source and drain electrodes in the transistor part, and the ohmic contact layer underneath are not patterned before heat treatment, but after the n-type impurity is diffused into the semiconductor layer.

Since it is patterned in the shape of the drain electrode, n-type impurities are also diffused into the channel region of the driving thin film l/transistor portion of the semiconductor layer to improve the v6 I+) characteristics of the driving thin film transistor without hysteresis. It can be a characteristic.

[Brief explanation of drawings]

1 to 4 show an embodiment of the present invention, in which FIG. 1 is a cross-sectional view of a thin film transistor memory, FIGS. 2 and 3 are V3-ID characteristic diagrams of a memory transistor and a drive transistor, FIG. 4 is a manufacturing process diagram of a thin film transistor memory. FIGS. 5 and 6 are cross-sectional views of a conventional thin film transistor memory and diagrams of its manufacturing process. ]1...Substrate, Tlo...memory transistor, T
2゜...Drive I transistor, Gl. , G2o...
Gate electrode, ]2... Gate insulating film, 1.2 a...
- Insulating film for maintaining voltage resistance, 1.2 b... Memory insulating film, 13... Semiconductor layer, 1, 3 a... N-type impurity diffusion portion, 14... Ohmic contact layer, S IO
+'S2o-source electrode, D+o+D2o...drain electrode, 15...metal film for source and drain electrodes. Applicant Casio Computer Co., Ltd.

Claims (2)

[Claims] (1) In a thin film transistor memory in which a memory thin film transistor and a driving thin film transistor are formed on a substrate, the memory thin film transistor and the driving thin film transistor are formed on a gate electrode formed on the substrate with a gate insulating film and a semiconductor layer. It has a structure in which an ohmic contact layer made of an n-type semiconductor and source and drain electrodes are laminated, and the gate insulating films of the memory thin film transistor and the driving thin film transistor are both insulating films having a charge storage function at least in the surface layer, The semiconductor layers of the memory thin film transistor and the driving thin film transistor are each formed of the same i-type semiconductor, and an n-type impurity contained in the ohmic contact layer is diffused into the channel region of the semiconductor layer of the memory thin film transistor. A thin film transistor memory characterized by: (2) Gate electrodes of a memory thin film transistor and a driving thin film transistor are simultaneously formed on a substrate, and a gate insulating film having a charge storage function at least on the surface layer and an i-type semiconductor are formed on the substrate on which the gate electrode is formed. After sequentially depositing a semiconductor layer, an ohmic contact layer made of an n-type semiconductor, and metal films for source and drain electrodes,
The metal film for source and drain electrodes and the ohmic contact layer thereunder are patterned in the shape of the source and drain electrodes only in the memory thin film transistor portion, and then heat treatment is applied to the semiconductor layer to form the ohmic contact layer thereon. The included n-type impurity is thermally diffused, and after this heat treatment, the metal film for source and drain electrodes of the driving thin film transistor portion and the ohmic contact layer thereunder are patterned into the shape of the source electrode and drain electrode. A method for manufacturing a characteristic thin film transistor memory.