JPH0411388B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inkjet printer that records an image on a recording member by ejecting ink liquid.

Conventional inkjet printers that have been put into practical use are incapable of high-speed recording because they eject ink using the mechanical deformation force of piezo elements. On the other hand, Japanese Patent Laid-Open No. 54-59139 and West German Publication No. 2843064, which disclose the innovative inkjet recording principle proposed by the applicant of the present application, disclose the formation of air bubbles using thermal energy. However, a recording method is described in which ink droplets are ejected in response to the rapid formation of bubbles.
However, at present, no printer is known to have applied this new recording method to an actual printer.

The present invention applied this innovative recording method that enables high-speed recording using thermal energy to on-demand printers. The technical problem is that the image quality has deteriorated due to a change in the state.

SUMMARY OF THE INVENTION An object of the present invention is to provide an on-demand inkjet printer that can achieve high-speed inkjet recording while improving image quality.

To achieve this object, the present invention provides an inkjet printer that records an image on a recording member by ejecting ink droplets, in which a plurality of orifice groups for ejecting the ink liquid are arranged in a predetermined arrangement. A first orifice row and a plurality of orifice groups corresponding to positions where orifices of the plurality of orifice groups of the first orifice row are not arranged are arranged in a predetermined arrangement, and a second orifice row is arranged so as not to be in a straight line. Each of the liquid chambers communicating with the orifice has a thermal energy generator that generates thermal energy for ejecting the ink liquid from each orifice according to recording information to form bubbles in the ink. an inkjet recording head that ejects ink droplets using the orifices of the first orifice row and the second orifice row to form a predetermined line image; a shift register that stores the recorded information; a latch circuit for storing the output recording information; and a recording information output of the latch circuit is applied to one input terminal, and a control signal is applied to the other input terminal of the first and second orifice arrays. a first driving element group and a second driving element group corresponding to each other, one end of each driving element of the first driving element group and the second driving element group is connected to the thermal energy generating body of the corresponding orifice. This is an on-demand inkjet printer that is connected to one end of the printer to perform printing.

According to the present invention, a problem that occurs when high-speed recording is performed by high-speed signal processing by arranging a large number of thermal energy generating bodies that generate thermal energy for ejecting ink at a high density can be solved. It is possible to solve the problem that the air bubbles formed in the ink become unstable due to thermal problems after generation of heat, resulting in deterioration of image quality. Therefore, the present invention solves thermal problems even when using a large number of thermal energy generators, while taking advantage of both the improvement in recording speed through high-speed signal processing and the high-speed recording of the above-mentioned thermal energy recording method. It is possible to maintain and improve image quality while providing an ideal on-demand type inkjet printer.

First, an inkjet printer to which the present invention can be applied will be explained using FIGS. 27 to 29.

FIG. 27 is an explanatory diagram for explaining the principle of ejecting droplets by the droplet ejecting head of an inkjet printer to which the present invention is applicable.

As shown in the figure, liquid IK is supplied into the liquid chamber W constituting the discharge head by capillary action. Now, in the part of the liquid chamber W1 of width △l, which is a distance l from the orifice OF, the heating element H1
When a drive signal is applied to the heating element H1, the temperature of the heating element H1 starts to rise. When the heating element H1 reaches a temperature higher than the vaporization temperature of the liquid in the chamber W1, bubbles B are generated on the heating element H1. The bubbles B grow as the temperature of the heating element H1 further increases, and their volume increases rapidly. As a result, the pressure inside the liquid chamber W1 increases rapidly, and the liquid chamber W1 increases by the volume increased by the bubbles B.
The direction of the liquid orifice that existed in 1 and
It moves rapidly in the liquid supply direction opposite to the OF direction. Therefore, a portion of the liquid existing in the portion l in the liquid chamber W is discharged from the orifice OF.
The discharged liquid becomes a liquid column, and the liquid column eventually stops growing, but the tip of the liquid column has accumulated the kinetic energy applied up to this point. Furthermore, when the bubble B collides with the ceiling surface of the liquid chamber W1, the force changes its direction in the longitudinal direction of the orifice side, and the droplet driving force is further increased.

By cutting off the drive signal applied to the heating element H1, the temperature of the heating element H1 gradually decreases. Due to this temperature drop, the bubble B begins to shrink in volume a little later than the point at which the drive signal is cut off. As the volume of the bubble B shrinks, liquid is supplied to the Δl portion from the liquid supply direction on the orifice OF side and the opposite side. That is, the liquid near the orifice OF is drawn back to the liquid chamber W1. As a result, the directions of the kinetic energy at the tip of the liquid column and the kinetic energy of the liquid column near the orifice OF are reversed, and the tip of the liquid column separates and becomes a minute droplet ID, which flies in the direction of the member PP and onto the member PP. adheres to the designated position. Here, the bubbles B on the heating element H1 gradually disappear due to heat radiation. This slow disappearance of the bubble B causes the meniscus IM to slowly retreat, and this slow retreat of the meniscus causes the meniscus to retreat while maintaining its surface condition. Note that the meniscus surface is stable, so it is possible to solve the problem of the meniscus receding too much caused by air flowing in from the meniscus destruction port, making the next discharge impossible. This slow shrinkage phenomenon of bubbles B is due to the liquid supply method based on capillary action, heat radiation phenomenon, and other reasons. Orifice
The size of the droplet ID discharged from OF is determined by the amount of energy applied, the width of the area △l that is affected by energy, the inner diameter d of the liquid chamber W, the distance l from the orifice OF to the heating element H1, and the amount generated in the liquid IK. It depends on the equipment conditions such as the surface tension, or the material properties such as the specific heat, thermal conductivity, thermal expansion coefficient, and viscosity of the liquid IK. In addition, a laser beam can be used instead of the heating element mentioned above.
Even when LZP is instantaneously irradiated, bubble B is similarly generated rapidly and gradually disappears, expelling a single droplet. In this case, H1 in the Δl portion can be used as a reflection plate, a heat storage plate, or other purposes to make heat generation by the laser pulse LZP more efficient, but is not necessarily required. Also, liquid IK is not limited to recording liquid, but also water,
It is possible to accurately spit out various liquids such as chemical solutions, fertilizer solutions, and others.

FIG. 28 t0 to t9 are schematic diagrams showing the liquid discharge process, showing the orifice OF, the liquid chamber w, and the heating element H.
1 is shown, and liquid IK is supplied from the direction opposite to the orifice OF by capillary action.

FIG. 29A is an example of a driving pulse, and t0~
t9 indicates the time corresponding to t0 to t9 in FIG. 28. Further, T shown in FIG. 29B is a graph showing the temperature change of the heating element H1, and FIG. 29C is a graph showing the volume change of the bubble B.

Now, at t0 in FIG. 28, the state before discharge is shown, and at tp between t0 and t1, the driving pulse E is applied to the heating element H.
1 is given. As shown in t1, the heating element H
The temperature increase of 1 is started at the same time as the drive pulse E is applied. At t1, the temperature of the heating element exceeds the vaporization temperature of the liquid, and bubbles B begin to form, and the liquid surface IM is lowered by the liquid IK from the orifice surface due to the bubbles B.
It shows the state in which it swells in proportion to the amount of pressure applied to it. At t2, bubbles B have grown further and the liquid level
IM swells further. At t3, the driving pulse E falls as shown in FIG. 29A, and when the temperature of the heating element H1 reaches the maximum as shown in FIG. 29B, the liquid level IM further expands. At t4, the temperature T of the heating element begins to drop as shown in Figure 29B, but at
As shown in Figure 9C, the volume of bubble B is at its highest level, and the liquid level IM is further expanded. At t5, the bubble volume B begins to shrink. Therefore, the orifice
The liquid IK in the liquid chamber W reaches the orifice by the amount that the bubble B contracts with respect to the liquid surface IM that bulges out from the OF.
It becomes a state where it is pulled in from the OF side. As a result, the liquid level IM is constricted at the part indicated by the arrow Q. t
At 6, the contraction of bubble B further progresses, and the droplet ID and liquid level
Separation occurs between IM′ and IM′. At t7, the droplet ID is ejected and flies, the bubble B further contracts, and the liquid level IM' further approaches the orifice OF surface. At t8, the bubble B is about to disappear, and the liquid level IM' further retreats and is drawn into the inner surface of the bubble through the orifice OF. t9 is liquid IK
This shows that the supply of is performed by capillary action and the state has returned to t0.

The recording liquid discharged from the liquid chamber W in this manner adheres to the recording member PP, and an image is recorded on the recording member PP.

Next, a circuit example of an inkjet printer to which an embodiment of the present invention is applied will be explained.

In FIG. 1, one end of each of a large number of recording bodies, such as heating elements 1H1 to 56H32, is commonly connected by a common conductor L. and a control element at each other end,
For example, the collectors of transistors 1T1 to 56T32 are connected. Also, transistors 1T1 to 1T3
2 as one chip, the emitter terminals of the transistor arrays of each chip are commonly connected to the respective chip selection switching elements MD1 to MD56, and the transistors 1T1 to 1T32,..., 56T1 of each chip are connected in common to the respective chip selection switching elements MD1 to MD56.
The bases at relative positions of ~56T32 are connected to common pixel information input terminals P1 to P32.

For example, to make the heating element 1H1 generate heat, close the chip selection switching element MD1, and
Open MD56 and apply pixel information to terminal P1. This drive voltage makes transistor 1T1 conductive, HV-1H1-1T1-MD1-earth EA
The heating element 1H1 generates heat by the circuit.

At this time, the collectors and emitters of the transistors 1T2 to 1T32 are biased in the forward direction.
1 because there is no pixel information input signal in P2 to P32.
T2 to 1T32 do not generate heat. Also MD
Since MD2 to MD56 are open, the pixel signal supplied from P1 flows only to the transistor 1T1, and only the heating element 1H1 generates heat.

As mentioned above, the chip selection switching element
Closing of MD1 to MD56 and pixel information input terminal P1 to
By selecting a combination of voltages applied to P32, a target heating element can be selectively caused to generate heat.

FIG. 2 shows an example of a drive circuit in which a common-base transistor array is used instead of the common-emitter type shown in FIG. 1. This utilizes the current amplification factors of individual transistors in the array configuration to reduce the current values on both the individual emitters on the array and the external lead line of the common base. According to this embodiment, there is an advantage that the load on the drive circuit can be reduced, and at the same time, there is no need to pay special attention to the current value etc. when drawing out the bonding wires from the array.

FIG. 3 shows an example in which all of the elements in the previous example were constructed with field effect transistors (FETs). At the same time as reduction of driving power, the element features of short storage time and short switching time make it possible to achieve high speed, and the drive circuit can be simplified due to its transfer characteristics.

It is also easy to understand that FIG. 3 can be of a common gate type, similar to FIG. 2. Further, the element shown in FIG. 1 may be constructed by a bipolar transistor. Furthermore, by using a PNP transistor or P-channel FET instead of an NPN transistor or N-channel FET,
It is also clear that the power supply polarity can be reversed.

FIG. 4 is a cross-sectional view of an example of a recording head using the drive circuits shown in FIGS. 1, 2, and 3, in which a heating element Hi is provided on an insulating layer IS, and a conductive substrate
Equipped with CD and board HS.

The insulating layer IS not only has the purpose of electrical insulation, but also functions as a heat storage layer for controlling the flow rate of heat generated by the heating element H1.

The heating element H1 formed on the insulating layer IS is further provided with a selection electrode li and a common electrode L for selectively applying pixel signals to the heating element, as shown in the figure. This common electrode L is connected to a heating element 1H1 as shown in FIG.
56H32, and is connected to a power source HV via a conductive substrate CD. An output terminal of the transistor array TA is connected to each selection electrode li. Furthermore, at least one of the block selection electrodes D1 to D56 and the pixel selection electrodes P1 to P32 are connected to the input terminal of the transistor array TA.

FIG. 5 shows another embodiment of the recording head of this embodiment. As shown in the figure, this is an example in which an insulating substrate IS' is formed under the conductive layer CD, and the substrate HS is made conductive and used as an electrode for the ground potential EA. In addition, the ground potential EA is connected to the conductive layer CD, and the power supply potential HV is introduced from another source, or the power supply potential is applied to the substrate HS.
It is clear that HV can be introduced. substrate
HS functions as a heat sink for heat dissipation of the heating element Hi.

Materials for the conductive layer include metals such as Al and Au, and materials for the heating element include ZrB ₂ , HfB ₂ , Ta ₂ N, W,
Ni-Cr, thick film resistor (Pd-Ag, Ru, etc.)
A common resistor such as SnD ₂ is used.

Note that it is also desirable to provide a thin insulating protective layer on the surfaces of the electrode layers Pi, li, Di, etc. and the heating element layer Hi, etc. for the purpose of preventing mechanical wear and the like. Further, a through hole TH as shown in the figure may be used to connect the common electrode L and the conductive layer CD. Furthermore, in order to form a large number of selection electrodes within one plane with more margin, it is also effective to alternately provide multiple layers of conductive layers and insulating layers that serve as electrodes. Furthermore, for ease of attachment and detachment, it is preferable to connect using connector contact pieces Ci and CH.

FIG. 7 shows that a grooved pattern is formed on a glass plate to produce a grooved plate GL1, and then the substrate with the heating element and transistor array described above and the grooved plate GL1 are bonded and integrated to form an inkjet recording head PH. An example is shown below.

FIG. 8 shows an example in which inkjet recording head blocks are fully assembled and arranged differently above and below one common heat sink plate HS. In the figure, odd- _numbered blocks CD1, CD3 _, . Ink is supplied to each block by an ink tank, an ink pipe, a pipe for common distribution to each block, and a pipe for distribution to each block. This zigzag arrangement is preferable because the orifice spacing Q, that is, the heating element spacing is the same as shown in the figure. In the case of the example shown in FIG. 1, each block is time-divisionally driven with a duty of 1/56.

FIG. 9 shows yet another example of an inkjet block cassette. As shown in the figure, there are four lead wires _P1 to _P32 , _D1 to _D7 , etc. on the insulating layer on the conductive substrate 1C.
A block is formed, and transistor arrays TA ₁ to _{TA 7} are connected to the center of each lead wire. The aforementioned transistors and switching elements are formed in each of transistor arrays _TA1 to _TA7 . In this cassette, the plate
32 grooves of GL are considered as 1 block, and each block JB ₁
Blocks BL ₁ , BL ₂ , and BL ₃ are provided between JB ₇ and JB 7.
As mentioned above, at least 33 lead wires are required to drive 32 heating elements independently. Furthermore, since various other functions are housed within the array, the chip volume also becomes large. Therefore, if
If the full multi-nozzle array on an A4 board is arranged closely without any blanks, the pitch of the Hondengu parts will be extremely small when connecting the transistor arrays TA ₁ to TA ₇ , and commercially available wire bonders cannot be used. It disappears. Furthermore, the joining distance between each block must be at least the distance between the grooves, which makes processing very difficult. Therefore, as shown in Figure 9, blank BL ₁ ~
By providing BL ₃ , the transistor array, for example TA ₇ , can be connected using the blank length BL. These blanks BL ₁ to _{BL 3} are parts to which no information is given when recording, so they are
As shown in Figure 0, the metal substrate is
Attach them in a zigzag pattern to the top and bottom of the HS to supplement each other's blanks.

Now, here, when pixel information P1 etc. are generated sparsely, it does not require much power to drive them simultaneously, but when 32 heating elements are driven simultaneously, a considerable amount of power is consumed.

FIG. 11 shows an example of driving to solve this problem. As shown in the figure, the heating elements that are driven at the same time are
1, H9, H17, H25 are sent out as only four pulses P1, P9, P17, P25, and at the next timing, four more pulses are sent out, for example, H2, H10, H1.
8. Drive H26. In other words, only four out of eight heating elements are driven at the same time. With this configuration, the electric power required to simultaneously drive 32 heating elements becomes 1/8 compared to the case of the example shown in FIG. On the printing paper, 4 out of 8 of the 32 heating elements are driven to print 4 dots first, then 1.
The four dots next to each dot are printed, and by repeating this process eight times, 32 dots of line printing are completed.

12 and 13 are schematic diagrams of a copying machine or facsimile apparatus to which the above-described full multi-recording head and time division drive circuit are applied. This copying machine or facsimile device has a reading section RD for reading information on a document. Reading section RD
A document table PG made of glass or the like is formed on the top of the document table PG, and a document is placed on this document table PG.
A document table cover PK for fixing the document is provided on the top of the document table PG.

At the bottom of the document table PG is a light source that illuminates the document.
BL, a reflecting mirror RM provided so that the light emitted from the light source BL effectively illuminates the manuscript table PG, a self-scanning light receiver CS having a large number of light receiving elements arranged in a straight line, and this light receiver CS. The optical unit LS, which includes an optical lens that images the original on top, is the receiver CS.
It is integrated with. This optical unit
The LS and receiver CS are fixed to the carriage CA.
Carriage CA is rotated by screw G on guide rails R1 and R2 driven by motor MO.
Performs reciprocating motion in the direction or double motion in the anti-Q direction. It is also assumed that the main scanning direction of the self-scanning light receiver CS sequentially scans the document surface in the P direction. Therefore, by moving the carriage CA (sub-scanning direction Q), the information of the original placed on the document platen PG is sequentially imaged onto the light receiver CS, and if the light-receiving elements are sequentially read out (main scanning), From the CS, it is possible to obtain sequential signals obtained by raster scanning the original.

In this embodiment, the document table PG is fixed and the carriage CA is movable, but a structure in which the carriage CA is fixed and the document table PG is movable may be used. When performing copy recording, the carriage CA moves in the Q direction and raster-scans the information on the document table in the P direction. At this time, the recording paper in the recording section is recorded while moving at a speed equal to the moving speed of the carriage CA in the Q direction. The image information obtained by the reading section is sent to the recording section shown in Fig. 8 via buffer memory.
The page information is sent to the PH and recorded in parallel with reading, but for example, the page information that has been read may be stored in memory and then recorded again.

The self-scanning photoreceiver CS consists of a number of photodetectors that convert optical input into electrical signals, and can process these signals in time series. Examples include CCD image sensors, MOS image sensors, and the like. In this copying machine, the width of the document table in the P direction is 216 mm (approximately equal to the width direction of A4), and a 1728-bit CCD is used as the light receiver.
Consider the case of using a linear image sensor. Recording unit PH is 1792 dots 224 due to signal processing.
A full-line multihead with a width of mm shall be used. Then, the image sensor and head can obtain a resolution of 8 dots/mm. Now, the block array above the heat sink plate HS in Fig. 8 is set as an odd number group, and the block array below is set as an even number group, with 28 each. do.
As mentioned above, the CCD sensor CS is a 1728-bit line sensor that scans each scanning line and outputs a voltage level according to image information. This voltage level is determined by the digitization circuit AD shown in FIG.
When the image has two levels (black and white), it is converted into a binary image, and when gradation (half tone) is required, it is converted into a multi-value image using an analog/digital converter or the like. Considering binarization for simplicity, the digitization circuit AD consists of a comparator that compares the output voltage of the CCD sensor CS with a reference voltage (slice level).
Outputs a high level or low level binary signal depending on the input voltage. This digitized data is serially input to a 32-bit shift register SR, converted into parallel data, and output, and thereafter processed in 32-bit units. shift register
The data output in parallel by the SR is once held in the 32-bit latch circuit L1, and then transferred to the memory section. The memory section consists of memory M1 and memory M2, and memory M1 stores the data of the odd block group.
Memory M2 stores data of even block groups. The data held by the latch circuit L1 is alternately written to the memory M1 and the memory M2 every 32 bits. The memories M1 and M2 are, for example, RAM (random access memory), CCD memory, magnetic memory, etc., and their storage capacity is 32 bits for memory M1 and 56K bits for memory M2. Memory M
1, M2 consists of 1 word with 32 bits,
Therefore, memory M1 has 1 word and memory M2 has 1792 words.
Consists of words. In addition, memories M1 and M2
The output of enable signal lines L4 and L5 are high.
When the level is high, it is assumed to be in a high impedance state, a so-called three-state state.

Data selectively read from memories M1 and M2 is once held in a 32-bit latch circuit L2. At this time, the states of memory M1 and memory M2 are as follows:
When one of the latch circuits is in the write state, the other is in the read state, and when one of the latch circuits L1 and L2 holds data in the memory M1, the other one is in the memory M2.
holds data.

Therefore, the data in the memory M1 and the data in the memory M2 are alternately held in the latch circuit L2. The data held in the latch circuit L2 is output to 32 NAND gates NG1 to NG32, and the NAND gates NG1 to NG32 are transistors when the timing PG of the print command signal line K10 from the control circuit CC is output. Selectively operate TP1 to TP32. Transistors TP1 to TP32
The collector terminal of is connected to the data input terminals P1 to P32 of the recording section PH. 56 of said part PH
The selection signal input terminals D1 to D56 are connected to the collectors of the transistors TD1 to TD56. The transistors TD1 to TD56 are sequentially scan-controlled by the output of the decoding circuit DC. The decoding circuit DC is a 6-to-56 line decoder and is controlled by six signal lines L11 from the control circuit CC. The control circuit CC is a circuit that generates signals for controlling each of the above elements, and the reference clock is made of a crystal oscillator.

Each control signal is shown in Figs. 13, 14, and 15.
This will be explained using the timing chart in the figure. The CCD is given drive pulses via the signal line L1, such as a start pulse φx to start line scanning, a reset clock φR for the output amplifier, and two-phase shift clocks φ1 and φ2 (not shown) for the shift register in the CCD. . The pulse interval of the start pulse φx in FIG. 1 corresponds to the scanning time of one scanning line, and during this period the second reset clock φR is
Output from CC. The reset clock φR is
It is assumed that image information is output from the CCD when the reset clock φR, which is a signal corresponding to the bit of the CCD, is in a low level state.

Therefore, as shown in FIG. 14, a transfer signal SCK that rises at the same period as the reset clock φR when the reset clock φR is at a roll level is applied to the signal line L2 that controls the shift register SR from the control circuit CC. It will be done.

In the control circuit CC, this transfer signal SCK is counted and sent to latch circuit L1 and latch circuit L every 32 bits.
2, connect the load clocks LCK1 and LCK2 to the signal line L.
3.Give at L9. The load clock LCK1 applied to the latch circuit L1 rises after the 32-pulse shift clock SCK is issued as shown in FIG. 14.

On the other hand, the memory enable signal ENB for selecting the memories M1 and M2 is applied after the load clock LCK1 of the latch circuit L1 rises, as shown in FIG.
Goes to role level and makes memory operational. While this memory enable signal ENB is held at low level, the load clock LCK2 applied to the latch circuit L2 must rise.

The read/write signal R/W, which controls writing and reading of memories M1 and M2, is a signal whose level changes every 32 pulses of the CCD reset signal φK, as shown in FIG. 14, and as shown in FIG. As in, the level changes 28 times during one scanning line. As mentioned above, the writing and reading operations of the memories M1 and M2 are reversed, so when the signal R/W given to the memory M2 by the signal line L7 is as shown in the figure, the signal inverted by the inverter I is sent to the memory M1. is given by signal line L8.

Signal PG given to NAND gates NG1 to NG32
is a signal that determines the timing and duration of energization to the heating element, and is applied to the signal line L10 after the load clock LCK2 of the latch circuit L2, as shown in FIG. 14. This signal PG is also generated every pulse of the reset clock φR32.

When using the above-mentioned driving method, this PG signal is further time-divided by a ring counter or ROM in the CC, and then output to the above-mentioned AND gates A1 to A1.
It is sufficient to apply it to A32. The binary signal input to the decoding circuit DC is 56-decimal in one scanning line, and is the output of a 56-decimal counter that counts up by one every time 32 pulses of the CCD reset signal φR are counted. Therefore, 56 transistors
TD1 to TD56 are sequentially turned on one by one for every pulse of the reset signal φR32, and selective drive pulses D1 to D56 in FIG. 1 are sequentially generated to cause the heating element to generate heat. Here, the operation shown in FIG. 13 will be described in more detail with reference to FIGS. 14 and 15. first
After the CCD start pulse φx is generated, when the read/write signal R/W is at a low level in the second half of the first cycle (when it is at a high level, it is the last two cycles of the previous scanning line).
(writing and reading are being performed on the memory corresponding to the block), data for the heating element group of the odd block DA1 is written from SR, L1 to the memory M1. In the first half of the next second cycle, the first
The data written in the memory M1 in the cycle is read out to the latch L2 and written into the data memory M2 for the second block DA2. Furthermore, in the second half of the second cycle, data for the third block DA3 is written into the memory M1. Also the second block
Read the data of DA2 to latch L2. Thereafter, similar operations are repeated, and reading for the last block DA55 of the odd block group and reading and writing for the last block DA56 of the even block group are performed while the CCD is scanning the next scanning line. Here, the memory M1 is a 1 word x 32 bit memory as described above, and written data is read out in the next cycle. On the other hand, in the memory M2, written data is read out after 64 scanning lines (1792 read/write cycles). That is, the data given to the even block group is the data 64 scanning lines before the data currently being read by the CCD. This is because, as mentioned above, there is a gap corresponding to 64 lines (8 mm) between the odd block group and the even block group.

For this reason, it is necessary to select an address for memory M2.

FIG. 16 is a diagram showing an outline of addresses in the memory M2. An address decoding circuit M2A is arranged in the memory M2, and a block counter BC and a line counter LC are arranged in the control circuit CC.

Memory M2 has a storage capacity of 56K bits, and its contents consist of 1 word (1 block) of 32 bits.
A unit of 28 words is called one line (896 bits), and it consists of 64 lines in total.

Block counter BC is a 28-decimal counter,
It is assumed that the input clock operates at the falling edge of the read/write signal R/W. Figure 15 shows how the block counter BC counts.

Line counter LC is a 64-decimal counter,
Carry output (carry) of block counter BC
The signal line 12 is counted as an input clock. Block counter BC output line l3, round counter
The output line l4 of the IC is the address selection line L in Figure 13.
6, and is decoded by address decoding circuit M2A to select a memory. In memory M2, after writing to the address of the mth block on the n line, the output of the block counter BC increases by 1, and the address of the (m+1)th block on the n line is read (this completes one read/write cycle). In the read/write cycle, writing is performed to the address of the (m+1)th block on the nth line. Here, when m reaches 28, it returns to 0 and the next line is accessed, and when n reaches 64, it returns to 0 line.

FIG. 17 is a diagram showing the state of the image information of the original GK and the state of data transition in each latch and each memory.

The 32-bit data A1 loaded into the latch circuit L1 at the current time T1 is transferred to the memory M at the time T2.
It will be written to 1. Also, at time T2, 32 bits of data A2 following data A1 is transferred to latch L1.
loaded into. At time T3, data A1 of memo M1 is transferred to latch L2, and latch L1
The next data A2 is stored in the memory M2, and the next data A3 is loaded into the latch L1. At time T4, latch L2 is loaded with data X2, and memory M1 is loaded with data A3 of latch L1.
is written, and data A4 is loaded into latch L1. The same operation is repeated thereafter. Here, the data X2 and X4 are information that was read 64 lines before the current CCD scan positions A1, A2, . . . and stored in the memory M2.

FIG. 18 is a flowchart for explaining the operations described above in an easy-to-understand manner.

FIG. 19 is a diagram showing an example of the arrangement of the reading section RD and recording section PH according to another embodiment. As described above, the self-scanning photodetector is composed of a large number of photodetecting elements that convert optical input into electrical signals, and can process these signals in time series. Here, in the embodiment shown in FIG. 16, 512-bit CCD sensors CCD1 to
It consists of 4 CCDs, and the length L of the effective light receiving part of one sensor is 12.8mm (25μ x 512 bits).
It is.

In this CCD sensor, the width of the document table in FIG. 7 in the P direction is set to 205 mm, and in order to cover this width, a lens optical system with a reduction magnification of 4 times may be used. In this case, the resolution of the input sensor is 10 dots/mm since light is received by a total of 2048-bit sensors.

Therefore, the recording part PH is also 10 dots/mm, that is, 1 mm.
Consists of 10 heating elements per unit.

In this embodiment, the recording parts PH are provided alternately above and below the heat sink plate HS as described above.
These upper and lower blocks form a full-line multi-recording head. For example, 2048 inkjet nozzles are divided into 4 blocks GL1 to GL.
Each block consists of 512 heating elements. As shown in the figure, the block (first block GL) installed under the heat sink plate HS
1. The gap between the vertical orifices of the 3rd block GL3) and the blocks installed above (2nd block GL2, 4th block GL4) is 28mm.
In other words, it is assumed that there are 280 lines.

If a copying device is constructed by arranging sensors in a horizontal line (or using a 2048-bit line sensor) for such a recording head as in the previous example,
It must have memory for image information corresponding to the orifice gap interval, that is, 280K bits. Incidentally, as mentioned above, in the example of FIG. 8, the second memory M2 of 56K bits is required.

However, in this embodiment, by adopting a sensor arrangement corresponding to the head arrangement as shown in FIG. 19, a simple system configuration that does not require memory is achieved. That is,
The reading section RD is arranged like the one shown in Fig. 19,
The CCD sensor CS may be scanned in the Q direction in the figure, and the recording unit PH may be driven using the information. Here the 19th
In the figure, the vertical distance D between the CCD sensors CCD2, 4 and CCD1, 3 is the same as that between the blocks GL2, 4 of the recording section PH.
Since the vertical distance between GL1 and GL3 is 28mm and the reduction magnification is 4x, it should be 7mm.

FIG. 20 is a block diagram for driving this embodiment. In the figure, CCD sensors CCD1 to CCD4,
Binarization circuit AD1 to AD4, shift register SR1
~SR4, latch circuit LA1~LA4,
Since the four blocks in FIG. 19 have exactly the same configuration and operation, only the circuit corresponding to one block will be explained.

As mentioned above, the CCD sensor CCD1 is a 512-bit line sensor, scans 1/4 scanning line, and outputs a voltage level according to image information.
This voltage level is binarized according to black and white by a binarization circuit AD1.

The binarization circuit consists of a comparator that compares the output voltage of the CCD sensor with a reference voltage (slice level), compares the input analog voltage with the slice level, and outputs a binary signal. If there is gradation (half tone) in the copy record,
If necessary, it is multi-valued using an analog/digital converter or the like.

The data digitized by the binarization circuit AD1 is input to a 32-bit shift register SR1, serial-to-parallel converted, and then parallel output processed in 32-bit units. shift register SR
The output data of 1 is held in a 32-bit latch circuit LA1. The data held in the latch circuit LA1 is synchronized with the print command signal PG through 32 NAND gates NI1 to NI32, and then selectively operates the transistors TI1 to TI32.
Transistors TI1 to TI32 are 32 N-P-
It consists of N transistors, and the collector terminals of each are connected to image data input terminals PI1 to PI32.

On the other hand, the 16 selection signal input terminals D1 to D16 are
16 P-N-P transistors TD1 to TD16
is connected to the flexor. These transistor circuits TD1 to TD16 are sequentially scan-controlled by the output of the decoding circuit DC. decoder circuit dc
is a 4-line-to-16-line decoder, and the 1st to 16th lines of TD1 to TD16 are sequentially selected by a signal from the control circuit CC.

The control circuit CC is a circuit that generates a driving clock for the CCD, a shift clock for the shift register, a clock for the latch circuit, a timing clock for the gate circuit, a selection signal for the decoding circuit, etc. These reference clocks are made of a crystal oscillator.

Each control signal will be explained with reference to timing charts in FIGS. 20 and 21. CCD1 to CCD4 are supplied with drive pulses on the signal line L1, such as a start pulse φX for starting line scanning (Fig. 21 1, a reset clock KφR of the output amplifier (Fig. 21 2, and a two-phase shift clock φ1 of the shift register section). ，
φ2 (not shown) is given by the control circuit CC.
The pulse interval of the start pulse φX corresponds to the scanning time of one scanning line, and during this period the reset clock φR is generated from the 512 pulses CC. Reset clock φR is a signal corresponding to the CCD bit, and when reset clock φR is at low level,
It is assumed that image information is output from the CCD.

Therefore, from the control circuit CC to the shift register SR1
As shown in FIG. 21, the signal line L2 that controls the transfer signal SCK, which rises at the same period as the reset clock φR when the reset clock φR is at a low level, is connected to the signal line L2 that controls the reset clock φR.
is given.

In the control circuit CC, this transfer signal SCK is counted and a load clock is applied to the latch circuits LA1 to LA4 via the signal line L3 every 32 bits. latch circuit
The load clock (signal line L3) applied to LA1 to LA4 rises after the 32-pulse shift clock (SCK in FIG. 21) is issued as shown in FIG. 21.

One signal given to the gate circuits NI1 to NIV32 is a signal PG that determines the timing and duration of energization to the heating element, and as shown in FIG.
(LCK)) and is given on the signal line L11.
This signal PG is also generated every pulse of the reset clock φR32.

On the other hand, the binary signal input to the decoding circuit DC is hexadecimalized during one scanning line, so the CCD
This is the output of a hexadecimal counter that counts up by one every time 32 pulses of the reset signal φR are counted.
Therefore, the 16 transistors TD1 to TD16 are sequentially turned on one by one for each pulse of the reset signal φR32 (see D1, D2, D3, . . . in FIG. 11).

In this embodiment, the memory can be saved significantly compared to the previous example, which is extremely preferable.

In this case, if manufacturing accuracy allows, CCD1~
Even if the CCD 4 and GL1 to GL4 are arranged in a straight line, the same effect as described above can be expected. Furthermore, in the event of a failure or the like, CCD1 to CCD4 and GL1 to GL4 can be separated individually, which is convenient. Also, it is more useful to improve surface accuracy etc. if they are manufactured individually.

FIG. 22 shows still another embodiment of the present invention. In this case as well, the geometrical arrangement of the recording section PH and the CCD reading section RD is the same as in the previous example. In this example, the configuration is further simplified by reducing the number of matrix wiring lines and by sharing the data processing circuit with four CCDs. That is, the data processing circuit shown in FIG. 20 processes information from four CCDs in parallel, whereas the data processing circuit shown in FIG. 22 processes information in a serial time-division manner. That is, the outputs of the four CCDs CS1 to CS4 shown in FIG. 22 are input to a 4-line-to-1-line analog data selector DS. The analog data selector DS is one scanning line (205mm long on the document table)
Switch the input of CCD1 to CCD4 every 1/4 of
One scanning line is formed by sequentially connecting the inputs of four CCDs. Selection of the inputs of the four CCDs is performed sequentially by signals on the control signal line L12 of the control circuit CC.

The subsequent processing is the same as the previous example, and the binarization circuit AD32
Bit shift register SR, 32-bit latch circuit LA, 32 NAND gates NG1 to NG32,
It is connected to image data input terminals P1 to P32 via transistors TR1 to TR32. In this case, a 6-line to 56-line decoder is used as the decoding circuit DC.

Further, other embodiments will be described.

FIG. 23 shows an ink jet block JB ₁ having a large number of heating elements and orifices (for example, 32), and constructed in a cassette type. figure
DA ₁ is a diode array containing a large number of diodes to prevent run-around, and OP1 is an ink supply pipe that is detachable from GL1. When this is removed, the inkjet block cassette JK ₁ will be removed from the main body of the device.

FIG. 24 is a sectional view showing an example of a connection configuration between the ink supply pipe _OP1 and the ink introduction port IS.

As shown in the figure, the packing FH is inserted into the inlet IS drilled in plate GL ₁ , and the O-ring OR
Is receiving. The 0 ring OR is held by the flange FG. The flange FG is inserted into the ink supply pipe OP ₁ , and the ink supply pipe OP ₁
Spring SP ₁ that presses the packing FH and flange FG is attached to prevent ink leakage between the connectors. This figure shows an example of how to smoothly attach and detach the ink supply pipe OP ₁ in the cassette configuration of this embodiment, and does not limit the connection method of the ink supply pipe OP ₁ in the cassette configuration. However, it is desirable to connect the ink supply pipe _OP1 using a pressure bonding means as shown in this figure. FL is the same filter as described above.

As described above, various improvements have been made by forming the inkjet nozzle array into a block cassette and combining a plurality of the cassetted inkjet blocks. In particular, vacuum thin film forming equipment for forming heating elements, lead electrodes, protective films, and insulating films on small cassette-shaped substrates _SS1 , or masks and mask aligners necessary for creating heating element and lead electrode patterns. etc. have the feature that they can be easily produced using commercially available small scale equipment. Furthermore, if the pipe OP ₁ is made flexible, it can be easily bent during attachment and detachment, so attachment and detachment operations can be performed without any trouble.

Further, the inkjet block cassette of this embodiment may have other forms than the one shown in FIG. 23, and is not particularly limited to this form. In other words, reducing the size of the heating element board improves its productivity, making it a cassette makes it easier to replace faulty blocks, and eliminates various risks that occur when connecting with the diode array. It has many features such as being extremely effective in improving yield. Further, manufacturing errors for each block can be made uniform by adjusting the amplitude, time width, etc. of the drive pulse as described above.

Furthermore, FIG. 25 shows the inkjet head blocks of FIG. 23 assembled in a fully multi-cassette manner and arranged alternately above and below one common plate. In the figure, odd-numbered blocks JB ₁ , JB ₃ ,...
JB _o , even number blocks JB ₂ , JB ₄ ,..., JB _o on the bottom surface
join. Each block has an ink tank
IT, ink pipe IP, each block common distribution pipe OP, EP and each block distribution pipe OP ₁ ~
Ink IK is supplied by OP _o . The pipes OP ₁ to _{OP o} connected to each block are flexible and detachable from the block, as shown in _an example in FIG _.
It is convenient to bend easily.

DA ₁ to _{DA o} are diode arrays, which are the same as described above, and each electrode 1 on the substrate with heating element SS ₁ to _{SS o}
It is connected to l1 to 1d32. This staggered arrangement allows the orifice to be adjusted as shown in Figure 26.
The interval Q between OF ₁ and OF ₂ is the same on the upper and lower sides, and it is possible to ensure an equal orifice interval Q for all full multi-line lines. In addition, the common board HS uses one metal plate common to all blocks in order to effectively perform heat dissipation assembly.

As described above, according to each embodiment to which the present invention is applied, by arranging the nozzles in a so-called zigzag pattern,
In addition to realizing high density recorded images, by providing multiple rows of drive elements, the actual mounting density of the drive elements can be made coarser, so a full-line multi-nozzle head can be easily realized.
High-speed image recording is possible.

The present invention is applied to the field of inkjet recording, and since the element that forms ink droplets is a heating element, it is possible to arrange a plurality of heating elements and corresponding ejection ports at a higher density than with conventional piezo elements. The so-called staggered arrangement solves the problem of unstable bubble formation due to heat accumulation after heat generation when thermal energy generators in a large number of orifices are arranged in a straight line. It is possible to eliminate the constraint signal processing by using a shift register and latch circuit, and to stabilize bubble formation at high speed while alleviating thermal effects, resulting in high-speed ink recording by final ink ejection. This can improve image quality.

[Brief explanation of drawings]

FIG. 1 is an embodiment diagram of a circuit used in an embodiment to which the present invention is applied, FIGS. 2 and 3 are diagrams showing other embodiments of the present invention, and FIGS. 4, 5, and 6 are 7 is a perspective view of a configuration example of a recording head according to an example of the present invention, FIG. 8 is a front view of an example of the present invention, and FIG. 9 is a diagram showing another example of a recording head. 1
FIG. 0 is an enlarged view of the front view and its relationship with the reading sensor, FIG. 11 is a waveform diagram for explaining the operation of the drive circuit that can be used in the present invention, and FIG. 12 is an overview diagram of the document reading section as an example of the present invention. FIG. 13 is a block diagram of an example of the present invention, FIGS. 14 and 15 are waveform diagrams for explaining its operation, FIG. 16 is a partially detailed diagram of the memory, and FIG.
FIG. 7 is a diagram showing the movement of memory contents during reading, FIG. 18 is a flowchart for explaining the overall operation, and FIG. 19 is a diagram showing another configuration example of the reading section and recording section.
Fig. 20 is a general block diagram of the ink supply unit, Fig. 21 is a waveform diagram for explaining its operation, Fig. 22 is a diagram of another example block, Fig. 23 is a schematic diagram of a cassette, and Fig. 24 is a sectional view of the ink supply section. , FIG. 25 is an example of a full multi-head, FIG. 26 is a partially enlarged view of the front of the head, and FIGS. 27, 28, and 29 are diagrams explaining the principle of the inkjet. In the figure, W...liquid chamber, IKW...liquid,
HW...heating element, OFW...orifice, PPW...
...Recorded member, 1H1-56H32W...Heating element, LW...Common conductor, 1T1-56T32W...
...Transistor, SRW...Shift register, L
1, L2W……Latch circuit, TA ₁ ~ TA ₇ W……
Transistor array, JB ₁ ~ JB ₇ W...block.

Claims (1)

[Scope of Claims] 1. In an inkjet printer that records an image on a recording member by ejecting ink droplets, a first orifice row in which a plurality of orifice groups for ejecting the ink liquid are arranged in a predetermined arrangement. and a second orifice row in which a plurality of orifice groups corresponding to positions where no orifice of the plurality of orifice groups of the first orifice row are arranged in a predetermined arrangement are arranged so as not to be in a straight line, and recording. The liquid chambers communicating with each of the orifices each include a thermal energy generator that generates thermal energy for ejecting ink liquid from each orifice according to the information to form bubbles in the ink, and the first orifice row and an inkjet recording head that ejects ink droplets using each orifice of a second orifice row to form a predetermined line image; a shift register that stores the recorded information; and the recorded information output from the shift register. a latch circuit for storing the information, and a latch circuit corresponding to each of the first and second orifice rows, the recorded information output of the latch circuit being applied to one input terminal and a control signal being applied to the other input terminal. a first drive element group and a second drive element group, one end of each drive element of the first drive element group and the second drive element group is connected to one end of the thermal energy generator of the corresponding orifice. An on-demand inkjet printer that performs recording using 2. The inkjet recording head is a full-line inkjet recording head capable of recording the width of the first and second orifice rows in a direction crossing the conveying direction of the recording member. On-demand inkjet printer.