JPH03295270A - Memory element - Google Patents

Abstract

PURPOSE:To enable a transistor-type memory cell of high density to be formed by a method wherein a memory cell is provided, where a conductor needle is covered with an insulating film, a conductive film is deposited thereon to serve as an outer coat conductor to constitute a capacitor, the inner conductor needle is connected to the drain of a MIS transistor, and the outer coat conductor is connected to a DC level. CONSTITUTION:A capacitor is composed of an inner conductor needle 1', a dielectric film 2', and a conductor 3, which surrounds them. 4', 5', and 6', or 4'', 5'', and 6'' denote the source, the gate, and the drain of a transistor respectively. The drain 6'(6'') is connected to a bit line Y'(Y'') through a contact 7'(7''). The inner conductor needle 1' is connected to the source 4' and the contact 8'' through the intermediary of a connecting conductor 9'(9''). The transistor concerned is formed through a normal silicon wafer process. The connecting conductor 9'(9'') is additionally provided. The connecting conductor 9' is formed of solder. Then, a capacitor is separately formed. In succession, a transistor and a capacitor are made to confront each other, and the conductor needle 1' and the conductor 9' are mechanically bonded together.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a one-transistor type dynamic memory cell.

(Prior Art) One type of semiconductor memory cell is a trench type, but it is becoming difficult to miniaturize this type. Furthermore, in the stacked type, since the capacitor is formed after the transistor is formed, it is difficult to use, for example, a ferroelectric film or a high dielectric constant film as the insulating film.

(Problems to be Solved by the Invention) An object of the present invention is to provide a structure that solves the above problems of stacked memory cells.

(Means for Solving the Problems) The present invention covers an insulating film around a conductor needle and a conductor film thereon to form an outer covering conductor, and uses the internal conductor needle as a drain of an MIS transistor. A memory element characterized in that it has a memory cell having an outer covering conductor connected to a DC level.

The capacitor capacity can be increased by using a ferroelectric film or a high dielectric constant film as the insulating film.

(Example) FIG. 1 shows an embodiment of the present invention.

(a) shows the structure of the memory cell, and (b) shows its equivalent circuit. In the equivalent circuit of (b), C is a capacitor and T is MO8
It's a transistor. X, S, and D are the gate, source, and drain electrodes of the transistor T, respectively.

Further, x, Y, and Vp are the word line, bit line, and plate voltages of the respective memory cells.

Next, let's explain the structure of (a). A capacitor C is constituted by a conductor needle 1, an insulating film 2 covering the needle, and a conductor film 3 surrounding the needle. Here, the conductor film 3 is fixed at the plate voltage Vp, and the internal conductor needle 1 is connected to the source 4 (S in (b)) of the MOS transistor. The gate electrode 5 of the transistor is connected to the word line X, and the drain 6 is connected to the word line
is connected to bit line Y.

FIG. 2 shows the structure of two memory cells. This diagram shows an example of how a capacitor and a transistor are connected.

(a) is a plan view. (B) is a sectional view taken along line AA' in (A). The memory cells are symmetrical in the figure, and each one is a 1-bit cell. The one-bit cell on the left side will be explained below. In the cross-sectional view, the internal conductor needle 1', the dielectric film 2', and the surrounding conductor 3' constitute a capacitor. The source, gate, and drain of the transistor are respectively designated 4', 5', and 6' in the cross-sectional view, and 4', 5'', and 6'' in the plan view. The drain 6'(6") is connected to the bit line Y'(Y") through the contact 7'(7'"). The internal conductor needle 1' of the capacitor is connected to the source 4'
and the contact 8'' via a connecting conductor 9'(9'').

An example of a manufacturing method for the above structure will be explained. The transistors are made using standard silicon wafer processes.

In particular, make up to the connection conductor 9'(9'').The connection conductor 9' is formed with solder.Next, make a capacitor separately.

Figure 3 shows the manufacturing method of the capacitor. Vapor phase growth method (SiH4+ 02→5i02 + H
20), a 5i02 film 2″ was grown, and A13 was further grown on top of it.
A capacitor is created by vapor-depositing ``''.The cut portion is irradiated with an ion beam to cut the wire, and each capacitor is cut into individual capacitors.The capacitor capacity can be easily increased by lengthening the interval between the cuts. Next, prepare a jig 25 with holes drilled to accommodate the capacitors in an array that is equal to the pinch of the memory cell, insert the cut-out capacitors into the holes, and dip them into the melted solder. Cool and solidify. Next, the conductor needle 1' and the conductor 9' are mechanically bonded with the transistor and capacitor facing each other.

In the above embodiments, a 5i02 film was used as the dielectric film, but in the present invention, a ferroelectric material such as 5rTi02 or a high dielectric constant material such as Ta205 can be used.

(Effects of the Invention) The present invention has made possible a one-transistor type high-density memo cell.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the structure of a memory cell, Figure 2 (A), (
B) are a plan view and a cross-sectional view of the memory cell, respectively. Figure 3 (
a) and (b) are diagrams showing the manufacturing process of a capacitor.

Claims (1)

[Claims] 1. Cover the conductor needle with an insulating film, cover it with a conductive film to form an externally covered conductor, use this as a capacitor, connect the internal conductor needle to the drain of the MIS transistor, and A memory element comprising a memory cell in which a covered conductor is connected to a DC level. 2. The memory element according to claim 1, wherein a ferroelectric film or a high dielectric constant film is used as the insulating film.