JPH0322289A - Dynamic ram - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a dynamic RAM (Random Access Memory), and relates to a dynamic RAM (Random Access Memory) using a direct sense method in which, for example, an amplified signal from a sense amplifier is outputted through an amplifying MOSFET. This article relates to effective technology that can be used in type RAM. [Conventional technology] Dynamic type R using a CMOS sense amplifier
An example of AM is, for example, Electronic Technology J, published in January 1986, pages 39 to 44.

[Problem to be solved by the invention]

When outputting the stored information of the memory cell to the input/output line,
There is a so-called direct sense method in which an amplifying MOSFET with a common source gate input is provided. In this type of direct sense method, the input/output line and the data line connected to the memory cell are separated from each other in terms of direct current, so there is no need to worry about data line information being destroyed due to load on the input/output line. .

This allows the column selection switch MO S F E
The operation timing of T can be set arbitrarily. However, even if the column selection timing is made faster, it takes time for the potential difference between the data line pairs to open up, or in other words, it takes time for the sense amplifier to amplify the minute signal read from the memory cell. , the problem is that the features of the direct sense method are not fully utilized. An object of the present invention is to provide a dynamic RAM that achieves high-speed read operation and low power consumption with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, C
A resistance means is provided between a sense amplifier having a MOS structure and a complementary data line to which it is coupled.

[Function] According to the above-described means, since the input/output nodes of the sense amplifier and the data line having a relatively large parasitic capacitance can be separated by the resistor means, the load is lightened during the amplification operation of the sense amplifier. This enables faster operation and lower power consumption.

〔Example〕

FIG. 1 shows a circuit diagram of a main part of an embodiment of a dynamic RAM according to the present invention.

FIG. 1 shows a schematic circuit diagram of an embodiment of a dynamic RAM according to the present invention. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon using known CMOS integrated circuit manufacturing techniques. In the same figure, the channel part (bank gate)
MOSFETs with arrows added are P-channel type.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET consists of a source region, a drain region formed on the surface of a semiconductor substrate, and polysilicon formed on the surface of the semiconductor substrate between the source and drain regions with a thin gate insulating film interposed therebetween. It is constructed from a gate electrode. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate serves as a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the i-plate gate of the P-channel MOSFET formed thereon.

The substrate gate of the P-channel MOSFET, ie, the N-type well region, is coupled to the power supply terminal Vcc of FIG. Although the internal details of the substrate bias voltage generation circuit VBG are not shown because they are not directly related to the present invention, the terminal Vcc-
It consists of an oscillation circuit OSC which receives a voltage between Vss as an operating voltage and forms periodic oscillation pulse signals, and a charge pump circuit CHP which receives such oscillation pulses.
The charge bomb circuit CHP is composed of a plurality of diode-connected MOSFETs and a capacitor (not shown), and generates a negative back bias voltage -vbb to be supplied to the semiconductor substrate by receiving an oscillation pulse signal.
As a result, a back bias voltage is applied to the substrate gate of the N-channel MOSFET,
As a result, the source of the N-channel MOSFET. Since the parasitic capacitance value between the drain and the substrate is reduced, the circuit can operate at high speed, and the minority carriers generated in the substrate are absorbed, thereby preventing the information charge accumulated in the information storage capacitor from being lost. Since this is reduced, the refresh cycle can be lengthened. The more specific structure of an integrated circuit can be roughly explained as follows. That is, out of the surface portion of a semiconductor substrate made of single crystal P-type silicon and in which an N-type well region is formed, other than the surface portion that is used as an active region, in other words, the semiconductor wiring region, the capacitor shape region, and the N-type well region are formed. A relatively thick field insulation formed by a well-known selective oxidation method is used except for the channel and the source, drain, and channel-shaped regions (gate-shaped regions) of the P-channel MOSFET. A film is formed. The capacitor type area is not particularly limited, but the capacitor type If
i. On the 9M region, there is a relatively thin insulating film (oxide film)
A third polysilicon layer is formed through the polysilicon layer. t
The mth polysilicon layer extends onto the field insulating film. The surface of the first polysilicon layer is covered with a thin oxide film formed by its own thermal oxidation. On the surface of the semiconductor substrate in a certain region of the capacitor type,
A channel is formed by forming an N-type region by ion implantation or by supplying a predetermined voltage. As a result, a capacitor consisting of the 1N-th polysilicon layer, a thin insulating film, and a channel region is formed. The first polysilicon layer on the field oxide film is
It is considered a type of wiring.

A 2M-th polysilicon layer is formed on a certain region of the channel shape to serve as a gate electrode via a thin gate oxide film. This 2Mth polysilicon layer is extended on the field insulation film and on the INth polysilicon layer. Although not particularly limited, word lines and dummy word lines in a memory array to be described later are constructed from the second polysilicon layer. On the surface of the active region not covered by the field insulating film, the first polysilicon layer, and the second polysilicon layer, source, drain, and semiconductor wiring regions are formed by a known impurity doping technique that uses them as an impurity doping mask. Teru. A relatively thick glabellar insulating film is formed on the surface of the semiconductor substrate including the first and second polysilicon layers, and a conductor layer made of aluminum is formed on this glabellar insulating film. has been done. The conductor layer is electrically coupled to the polysilicon layer and the semiconductor region through a contact hole provided in the insulating film below. A data line in a memory array, which will be described later, is composed of a conductor layer extending on this glabella insulating film, although it is not particularly limited.

The surface of the semiconductor substrate including the glabellar insulating film and the conductor layer is covered with a final passivation film consisting of a silicon nitride film and a phosphorus silicate glass film. Although not particularly limited, the memory array MARY is of a two-intersection (folded bit line) type. Figure 1 specifically shows the pair of lines. A pair of parallelly arranged complementary data lines (bit lines or digin I-lines) DO. MOSFE for address selection in DO
TQm and information storage capacitor C! The input/output nodes of each of the plurality of memory cells organized by I and I are distributed and connected with a predetermined regularity as shown in the figure. The precharge circuit PC is a MOS shown as a representative.
As shown in FE'rQ5t71, the complementary data line DO. It consists of a switch MOSFET installed between DO and DO.
The MOSFET Q5 is turned on when the chip is not selected or before the memory cell is set to the selected state by supplying the precharge signal φpc generated in the chip non-selected state to its gate. As a result, in the previous operation cycle, complementary data generated by the amplification operation of the sense amplifier SA, which will be described later! By shorting the high and low levels of IDO and DO, complementary data iDQ. DO approximately V
The precharge voltage is set to cc/2 (HVC). Note that, although not particularly limited, when the chip is left in a non-selected state for a relatively long time, the precharge level is reduced due to leakage current or the like.

Therefore, in this embodiment, the switch MOSFET
By providing Q45 and Q45, half precharge voltage H
Supply VC. Although the specific circuit thereof is not shown, the voltage generating circuit HLVG that generates the half precharge voltage HVC is designed to have only a relatively small current supply capability in order to compensate for the leakage current and the like. This suppresses an increase in power consumption.

The above precharge M is caused by the RAM chip non-selection state etc.
Before OSFETQ5 etc. are turned on, the sense amplifier SA is brought into a non-operating state. As a result, the complementary data line Do. Do maintains a high level and a low level in a high impedance state. Furthermore, when the RAM is put into operation, the precharge MOSFET Q5 is connected before the sense amplifier SA is put into operation.
, Q45, Q46, etc. are turned off. As a result, the complementary data lines DO, Do maintain the above-mentioned half precharge level in a high impedance state.

In such a half precharge method, complementary data lines DO. Since the high level and low level of DO are simply short-circuited, power consumption can be reduced. In addition, in the amplification operation of the sense amplifier SA, the complementary data line DO. D.O.
changes in common mode, such as high level and low level, so it is possible to reduce the noise level generated by capacitive coupling. The unit circuit of the sense amplifier SA is shown as an example, and includes P-channel MOSFB'T'Q7, Q9 and N
CMOS consisting of channel MOSFETQ6, QB
It consists of a latch circuit, and its pair of input/output nodes are connected to corresponding complementary data lines via a resistor circuit R.
In the same figure, one of the circuits is exemplarily shown as a representative, and it is a MOSFET that uses the above-mentioned resistor circuit R in order to achieve high-speed operation and low power consumption as will be described later.
The complementary data line DO. through TQ66 and Q67. D.O.
is combined with MOSFET that composes resistance circuit R
Q66 and Q67 gates have these MOSFETQ6
A bias voltage VG is supplied to keep Q6, Q67, etc. in a steady on state. The MOSFBT Q66, Q67 transmits the read voltage read from the memory cell to the sense amplifier SA, and the high level and low level signals raised to a sufficient level by the operation of the sense amplifier SA are transmitted again via the complementary data line. It is desirable to turn on the signal determined by the sense amplifier SA so as to be supplied to the memory cell. Therefore, M.O.
SFETQ66. The bias voltage VG applied to the gate of Q67 is Vcc+Vth (however, vth is M
OSFETQ66. Q67 threshold voltage) or higher. In this embodiment, the bias voltage VG is a steady or direct current voltage, although it is not particularly limited. The voltage generation circuit HVG includes a bootstrap capacitor (not shown),
and a rectifier diode-connected MOSFET, and receives an oscillation pulse from an oscillation circuit OSC to
A bias voltage vG of a level higher than c+VLh is applied. Especially for the CMOS latch circuit that constitutes the sense amplifier mentioned above! 11, but the power supply voltage Vc is passed through parallel P-channel MOSFETs Q12 and Q13.
n-channel MOSFET Q in parallel form,
The ground voltage VSS of the circuit is supplied through I O,Ql1. These power switch MOSFET QI O
, Ql 1 and MOSFETs Ql2, Q13 are connected to latch circuits (
Commonly used for unit circuits. In other words, the sources PS and SN of the P-channel MOSFET and N-channel MOSFET in the latch circuit in the same memory array are commonly connected. The above MOSFETQIO. A complementary tie a is connected to the gate of Q12 to activate the sense amplifier SA during the operation cycle.
ng pulse φpal. φpal is applied, MO
The gates of SFETQI 1 and Ql 3 are connected to the above tie ξ
Complementary timing pulses φpa2 and φpa2, which are delayed from the timing pulses φpal and φpal, are applied. By doing this, the operation of the sense amplifier SA can be divided into two stages. Thai straw balus φpal
, φpal is generated, that is, in the l-th stage, the MOSFET with relatively small conductance
Due to the current limiting effect of QIO and Q12, the minute read voltage applied between the pair of data lines from the memory cell is amplified without undergoing undesired level fluctuations. After the potential difference of the output node is increased by the amplification operation in the sense amplifier SA, when the tying pulse φpa2+φpa2 is generated, that is, when the second stage is entered, the MOS with a relatively large conductance
FETQI 1 and Ql 3 are turned on. The amplification operation of the sense amplifier SA is performed using MOSFETQI l. Ql
3 is turned on.

The row decoder R-DCR is a row address buffer R-
It decodes the address signals aO to am supplied from the ADH and performs a word line selection operation in synchronization with a word line selection timing signal φX (not shown). Although not particularly limited,
The word line is provided with a switch MOSFETQ at its far end (the end opposite to the decoder side). The gates of these MOSFETs Q38 to Q41 are supplied with timing signals wcoo to -Cll that are set to high level corresponding to non-selected word lines. As a result, the unselected word lines can be fixed at the ground potential of the circuit, and the unselected word lines can be prevented from being raised to an intermediate potential in response to the rise of the selected word line due to capacitive coupling between the word lines.

The input/output nodes of the unit circuits constituting the sense amplifier SA are connected to the gates of the amplification MOSFETs Q6 0 and Q6 1. The sources of these amplification MOSFETs Q61 and Q60 are coupled to ground potential.

And its drain is the column switch R for reading.
Switch MOSFET Q63 and Q62 that constitute WC
Common data for reading gRCD. Connect to RCD. In this case, the above MOSFETQ60 and Q6
1 is a non-inverting data line DO for performing an inverting amplification operation.
The drain output of MOSFETQ61 corresponding to f'L is coupled to the common data line RCD for inverted reading through column switch MOSFETQ63, and the drain output of MOSFETQ61 corresponding to f'L is connected to the common data line RCD for inverted readout.
) Drain output is column switch MOSFETQ62
is coupled to a non-inverting read common data line RCD through the . This common data line RCD, RC for reading
D is conveyed to the input of main unit MA.

In this embodiment, although not particularly limited, the write common data line WCD. A switch MO in which WCD is provided independently and constitutes a write column switch circuit WCW.
The complementary data line D is connected via SFETQ64 and Q65.
It is coupled to O, Do.

The write common data lines WCD, WCD are coupled to the output terminal of the data input buffer DIB.

Corresponding to the provision of column switches RWC and WCW for reading and writing as described above, the column decoder C-DCR has a pair of complementary data lines Do and DO.
A column selection line RYS for reading and a column selection line wys for writing are provided correspondingly. In read operation mode, column decoder C-DC
R decodes the supplied column system address signal and
One column selection line RYS is brought into a selected state in response to a data line selection timing signal φy. In this case, the timing signal φy is generated at an early timing. That is, the tying signal φy is generated in response to the reception of the column system address signal without waiting for the completion of the amplification operation of the sense amplifier SA. Even if the selection operation of the column system is accelerated in this way, the complementary data lines DO, DO, etc. and the common complementary data IRCD, RCD for reading are connected to the amplification MOSFET Q60. ．． There is no problem because it is separated in terms of direct current by Q61 etc. Then, the amplified signal according to the amplification operation of the sense amplifier SA is transmitted to the MOSFE.
Since the signal is further amplified by TQ60 and Q61 and transmitted to the common complementary data lines RCD and RCD for reading, high-speed reading becomes possible.

In this embodiment, the input/output nodes of the sense amplifier and the complementary data lines DO, DO, etc. are separated in an alternating current manner by MOSFETs Q66 and Q67, which act as resistance elements by constantly applying a voltage VC to their gates. can. In other words, for the human output node of the sense amplifier,
Complementary data 4'iDO, which has a relatively large parasitic capacitance by combining a large number of memory cells;
Do can be isolated in an alternating current manner by providing MOSFETs Q66 and Q67 that interact with the resistive element. As a result, the sense amplifier SA receives the timing pulse φpaO
．． When activated by PAL or the like, it is only necessary to discharge or charge up the parasitic capacitance that has an extremely small capacitance value at the input/output node. As a result, the amplified output signal expands to high level and low level at high speed, and when the data lines DO and DO are selected, the read common data line RCD. This will be communicated to RCD.

In the amplification operation of the sense amplifier SA, the operating current of the sense amplifier can be reduced as the load becomes lighter. As a result, when the sense amplifier starts its amplification operation, the DC current flowing between the power supply voltage and the ground potential can be reduced.This reduces the noise generated in the power supply line and grounding during the sense amplifier's amplification timing. It is possible to reduce this and improve the operating margin. The potential difference between the complementary data lines DO and DO is such that the amplified output of the sense amplifier is connected to the MOSFETQ as the resistive element.
Since the signal is transmitted through Q66 and Q67, it gradually expands, and when it finally reaches a high level and a low level, this high level or low level is rewritten into the selected memory cell. As a result, the storage charge that is about to be lost in the information storage capacitor of the memory cell is recovered by the word line selection operation.

At this time, MOSFETQ acting as the above resistance element
As described above, the voltage G supplied to the gates of 66 and Q67 is raised to a high level higher than the power supply voltage Vcc at the latest when performing the write operation to the memory cell. Thereby, the high level amplified by the sense amplifier can be transmitted to the complementary data IDO or DO without any level loss. Pcha as a resistance element
I-channel MOSFET and N-channel MOSFET
By using a parallel-connected device, the step-up voltage described above can be eliminated. In write mode, column decoder C-DCR selects column selection line wys for writing. As a result, the write signal through the common data lines WCD, WCD for writing is applied to the switch MOSFETs Q64, Q65, etc. that constitute the column switch circuit WCW, which are turned on according to the selection level of the column selection line WYS. The data is transmitted to the complementary data lines Do, DO, etc., and written into the selected memory cell. In this embodiment, a configuration is adopted in which the write signal is directly transmitted to the complementary data lines Do, DO, etc. without passing through the MOSFETs Q66 and Q67, which act as the resistance elements, so that writing can be performed at high speed with a relatively small current. It can be carried out.

The row address buffer R-ADB has a tie ξ generated by a timing generation circuit TG, which will be described later, based on a row address strobe signal RAS supplied from an external terminal.
The address signal AO-A is put into an operating state by a switching signal (not shown), and is supplied from an external terminal in synchronization with the row address strobe signal RAS in the operating state.
When m is taken in and held, internal complementary address signals aO to am are generated and the row address decoder R
- Inform DCR1 and R-DCR2. Here, an internal address signal having the same phase as the address signal AO supplied from the external terminal and an internal address signal having the opposite phase are combined to form a complementary address signal aO. (same as below).
The row address decoder R-DCR decodes the complementary address signals aO to am as described above, and selects a word line in synchronization with the word line selection tie signal φX. On the other hand, the column address buffer C-ADB receives the column address strobe signal CAS supplied from an external terminal.
is activated by a timing signal (not shown) generated by a timing generation circuit TG, which will be described later, based on The input address signals AO to An are taken in and held, and internal complementary address signals aO to an are generated and transmitted to the column address decoder C-OCR. The column decoder C-DCR is basically constituted by an address decoder circuit similar to the above address decoder R-DCR2, and decodes the complementary address signals aO to an supplied from the column address buffer C-ADH to output data. In synchronization with the line selection timing signal φy, a selection signal to be supplied to the column switch for reading or writing is formed depending on the operation mode.

In addition, in the same figure, the row address buffer R-AD
B and column address bus C-ADB are collectively represented as address bus sofa R, C-ADB.

Between the common data lines RCD and RCD for reading,
An N-channel precharge MOSFET Q44 constituting a precharge circuit similar to the above is provided.

A pair of input/output nodes of a main amplifier MA of a circuit fllI similar to the unit sense amplifier USA are coupled to the common data lines RCD, RCD. The output signals of the output nodes MO and MO of the main amplifier MA are sent to the external terminal Dout via the data output bus sofa DOB. For read operation, data output buffer D
OB is activated by the timing signal φrI1, and amplifies the output signal of the main amplifier MA, which is activated at this time, and sends it out from the external terminal Dout. In the case of a write operation, the output (Dout) of the data output buffer DOB is placed in a high impedance state by the timing signal φr.

The above writing common data line WCD. WCD is coupled to the output terminal of data input bumper DIB. If it is a write operation, the data input bus sofa DIB is connected to its tie ξ
It is activated by the switching signal φr-, and the external terminal Di
By transmitting a complementary write signal in accordance with the write signal supplied from n to the common data lines WCD, WCD,
Writing is performed to the memory cell coupled to the selected data line. In addition, for read operation, the above tie ξ
The output of the data input buffer DrB is brought into a high impedance state by the switching signal φrw.

As described above, in the write operation to the dynamic memory cell consisting of the address selection MOSFETQm and the information storage capacitor Ca, full writing is performed on the information storage capacitor Cs.In other words, the address selection MOSFETQm In order to prevent a level loss of the high level written to the information storage capacitor 9Cs due to threshold voltages such as, a word line bootstrap circuit BST activated by a word line selection timing signal φκ° is provided. This word line bootstrap circuit BST has a word line selection tying bond φ
Using κ° and its delayed signal, the high level of the word line selection timing signal φX is set to a high level higher than the power supply voltage Vcc.

The various timing signals mentioned above are generated by the timing generation circuit T.
It is shaped by G. The timing generation circuit TO generates the main timing signals listed above. That is, this timing generation circuit TG is . The series of various tying pulses is generated by receiving the address strobe signals R A S and CAS and the write enable signal WE supplied from external terminals.

The circuit symbol REFC is an automatic refresher circuit 1, which includes a refresh address counter and the like. This automatic refresh circuit REFC is connected to address slope signals RAS and CAS, although not particularly limited.
When the column address strobe signal CAS is set to low level before the row address strobe signal RAS is set to low level, the logic circuit receiving the row address strobe signal RAS determines this to be a refresh mode, and outputs an address using the row address strobe signal RAS as a clock. Refresh address signal aQ' formed by the counter circuit
am' is sent. This refresh address signal aQl~am'' is transmitted to the row address decoder circuit R-OCR via the row address buffer R-ADB having a multiplexer function.Therefore, the refresh address signal aQl~am'' is transmitted to the row address decoder circuit R-OCR in the refresh mode. At this time, a control signal (not shown) is generated to switch the address buffers R-ADB.As a result, refresh is performed by selecting one word line corresponding to the refresh address signals aO゛~am'. An operation is performed (CAS before RAS refresh).

FIG. 2 shows a circuit diagram of a main part of another embodiment of the dynamic RAM according to the present invention.

In the embodiment shown in the figure, a resistance element is provided between the input/output node of the sense amplifier and the offset data laDo, Do. As this resistance element, a diffused resistance or a polysilicon resistance is used. The effects obtained from the above examples are as follows. That is, (1) A resistance means is provided between a CMOS-configured sense amplifier and a complementary data line to which it is coupled, and the input/output node of the sense amplifier is connected to a data line having a relatively large parasitic capacitance. By separating the sense amplifiers in an alternating current manner, the load during the amplification operation of the sense amplifier becomes lighter, and the effect of increasing the speed of the amplification operation and reducing power consumption can be obtained.

(2) By applying the present invention to the direct sense method, the features of the direct sense method can be utilized to the fullest, resulting in the effect of realizing high-speed reading. (3) Since the operating current of the sense amplifier can be reduced due to (1) above, the direct current (through current) flowing through the sense amplifier when the sense amplifier starts operating can be reduced. This has the effect of reducing the noise level generated on the power supply line during the operation of the sense amplifier, and improving the operating margin. Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, a column switch for writing may be connected to the human output node of the sense amplifier. In this case, a write signal is transmitted to the complementary data line via the resistance means.

Since the write signal has a high signal level and the time required for it is extremely short, there is no problem even if the write signal is transmitted through the resistance means as described above. By adopting such a configuration, common data lines for reading and writing can be arranged adjacently. Further, the common data line may be an input/output line for reading and writing. In this 4'N rule, the input/output nodes of the sense amplifier are connected to the above input/output lines via column switch MOSFETs. Even if such a direct sensing method is not adopted, the amplification operation of the sense amplifier can be made faster by inserting the above-mentioned resistor means, so the column selection timing can be made faster, and the readout operation can be made faster accordingly. It is something that can be achieved.

In the above-mentioned direct sense method, it is important to speed up the selection timing of the Y system, so in order to further speed up the selection timing, a configuration is adopted in which the X address signal and the Y address are supplied from independent terminals. It may also be one that takes In other words, the so-called pseudo-static type RA
This can be applied to M as well. The bias voltage VG for the resistance circuit R does not have to be a DC voltage as in the embodiment. The bias voltage VC is applied to the timing signal φp based on the external control signal RAS, for example.
Before a, the VQ voltage was changed to high level,
End of memory access (RAS changes to high level)
It may also be a signal that returns to 0 volts again. The resistance circuit R is an N-channel MOSFET.
A P-channel MOSFET may be used instead of T. In this case, the bias voltage vG can be determined without a bootstrap circuit.

In addition to the dynamic type RAM, this invention is applicable to the above-mentioned pseudo-static type RAM, a random input/output function such as for images, a serial input/output function, or a video RAM having a serial input/output function. It can be widely used in a dynamic RAM in a broad sense using a dynamic ξ-link type memory cell and a sense amplifier based on the CMOSFlt standard.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a resistance means is provided between a sense amplifier having a CMOS structure and a complementary data line to which it is coupled, and an alternating current is established between the input/output node of the sense amplifier and the data line having a relatively large parasitic capacitance. By separating the sense amplifiers, the load during the amplification operation of the sense amplifier becomes lighter, making it possible to speed up the amplification operation and reduce power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the dynamic RAM according to the present invention, and FIG. 2 is a circuit diagram of main parts showing another embodiment of the dynamic RAM according to the invention. MARY...Memory array, PC...Precharge circuit, SA...Sense amplifier, RWC...Column switch circuit for reading, WCW...Column switch circuit for writing, MA...Main amplifier, R...Resistance circuit, R ,C-
ADB: address buffer, R-DCR: row address decoder, C-DCR: column address decoder, TG: timing generation circuit, REFC: automatic refresh circuit, DOB: data output bath sofa, DIR
・・Data buffer, VBG・・Substrate bias generation circuit, OSC・・・Oscillation circuit, CHP・・Charge pump circuit, HLVG, HVG・・・Voltage generation circuit

Claims (1)

[Claims] 1. A dynamic RAM characterized in that a resistance means is provided between a CMOS-configured sense amplifier and a complementary data line to which it is coupled. 2. The dynamic RAM according to claim 1, wherein the resistance means is composed of a MOSFET. 3. The amplified signal of the sense amplifier is transmitted to the common data line for readout through an amplification MOSFET with a common source gate input and a readout column switch circuit.
Dynamic RAM described in Section 1.