JPH0287670A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform highly reliable metallic wiring which has low resistance and is superior in barrier properties and adhesion as well by forming a metallic wiring film which uses a metal or its alloy having a high melting point at its upper face of an insulating film as well as at the inside of a contact hole, thereby annealing its wiring film in an atmosphere of a specified gas. CONSTITUTION:The whole upper face of a layer insulation film 6 including the inside of a contact hole is formed into a piece of an alloy having a high melting point, for example, titanium tungsten 9a with a treating process, for example, DC magnetron sputtering. In such a case, a silicon substrate 1 which forms titanium tungsten 9a is taken out from a vacuum state and annealing is performed in an atmosphere of an ammonium gas. It is preferable to perform annealing within one minute at a temperature of 600-700 deg.C.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a method of manufacturing a semiconductor device using a high melting point metal or an alloy thereof as metal wiring of the semiconductor device.

(b) Prior Art Aluminum alloys are widely used as metal wiring for semiconductor devices. However, with the recent increase in the density of integrated circuits, deterioration of contact characteristics due to the reaction between this aluminum alloy and the silicon substrate has become a problem. Therefore, methods of using high melting point metals such as titanium tungsten, titanium nitride, tungsten silicide, or molybdenum silicide or alloys thereof for metal wiring have been attempted. This involves inserting a high melting point metal into the underlying layer of the metal wiring so that only the high melting point metal comes into contact with the substrate silicon, or using a high melting point metal called barrier metal or its alloy itself as the metal wiring. It is.

A conventional method for manufacturing a semiconductor device using a high-melting point metal as the base layer for modern wiring will be described with reference to FIG. here,
The case where a metal wiring is connected to the source or drain of a MOS-FET is shown.

First, as shown in FIG. 2 (J), after forming a field oxide film 12 on a silicon substrate 11, a gate oxide film 1
3. Form a gate electrode 14 and a diffusion layer 15, and further cover the entire upper surface with an interlayer insulating film 16. Next, Figure 2 cb
As shown in +, a contact hole 18 is formed by removing the interlayer insulating film 16 and gate oxide film 13 on the diffusion layer 15 using the photoresist 17 as a mask. As shown in FIG. 2C, after removing the photoresist 17, the entire upper surface of the interlayer insulating film 16, including the inside of the contact hole 18, is covered with a high melting point metal film 19a, and the entire upper surface is roughly covered. Metal film wire II covered with aluminum alloy 119b! form 19. This high melting point gold, 1
The Ij 119a and the aluminum alloy film 19b are formed by sputtering or CVD.

As a result, the diffusion layer 15 in the silicon substrate 11 and the metal film 1 on the interlayer insulating film 16 are connected via the contact hole 18.
11119 can be connected.

(c) Problems to be Solved by the Invention However, when a high-melting point metal or its alloy is used in this way, in the conventional manufacturing method, the bond between the metal wiring film and the substrate silicon is higher than when a metal wiring film is formed using only an aluminum alloy. A problem has arisen in that contact resistance tends to increase.

The contact resistance with a high melting point metal or its alloy increases significantly especially in the case of a p← type scattered layer on a silicon substrate.

Furthermore, when titanium tungsten or titanium ytride is used as the high melting point metal, the contact resistance increases significantly.

A common cause of the increase in contact resistance is a polymer film of C and F formed on the silicon substrate surface during reactive ion etching. However, AES shows that such polymeric film was removed during post-process cleaning.
A similar increase in contact resistance is also observed when confirmed by analysis.

Therefore, the increase in contact resistance here is thought to be due to some kind of alteration occurring in the surface layer of the substrate silicon exposed within the contact hole (which is thought to be about a fraction of the surface layer) itself due to reactive ion etching. .

In addition to this increase in contact resistance, there are the following three problems. For one thing, when the film thickness of the barrier metal is thin, the barrier metal loses its barrier properties and destroys the source and drain junctions. In particular, titanium-tungsten reacts with aluminum and the underlying diffusion layer silicon to form a three-element alloy with tungsten, so a film thickness of at least a certain level is required. In order to obtain this film thickness at the bottom of the contact hole, it became necessary to increase the deposited film thickness considerably.

The second problem is poor adhesion to the underlying insulating film.

In the case of titanium-tungsten, titanium is mixed into tungsten to improve adhesion, but in a laminated structure with aluminum, titanium-tungsten sometimes lifts or peels off during the photolithography process and etching process. .

Finally, the crystal growth of aluminum silicon on titanium tungsten was sometimes suppressed. In other words, the aluminum silicon crystals on titanium tungsten are several times smaller than those on the insulating film. Considering that electromigration is rate-determined by grain boundary diffusion of aluminum atoms, it is expected that electromigration resistance is poor.

The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide a method for manufacturing a semiconductor device that can produce metal wiring with low resistance, excellent barrier properties, and high adhesion and reliability.

(D) Means for Solving the Problems According to the present invention, an insulating film is formed on a semiconductor substrate, a predetermined position of the insulating film is removed by etching to open a contact hole, and then the upper surface of the insulating film is etched. Also provided is a method for manufacturing a semiconductor device, which comprises forming a metal film line using a high melting point metal or an alloy thereof on the inner surface of a contact hole, and then annealing in a specific gas atmosphere.

In this invention, the specific gas atmosphere may be any gas atmosphere containing nitrogen so that a nitride layer of the high melting point metal or its alloy is formed when annealing is performed, and an ammonia gas atmosphere may be used. is optimal.

(e) Effect: By annealing the high melting point metal or its alloy in a specific gas atmosphere, the damaged layer on the semiconductor surface of the semiconductor substrate that occurs during contact hole etching is removed by annealing out or a silicide reaction. , the contact resistance between the high melting point metal or its alloy and the semiconductor substrate is reduced, and a nitride of the high melting point metal or its alloy is formed to improve barrier properties.

(F) EXAMPLES Hereinafter, examples of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to the following examples.

This embodiment shows a case where a metal wiring is connected to the source or drain of a MOS-FET, as in the conventional example.

First, as shown in FIG. 1 (J), after forming a field oxide I!!2 on a silicon substrate 1, a gate oxide film 3
, a gate electrode 4 and a diffusion 15 are formed, and the entire upper surface thereof is further covered with an interlayer insulating film 6. Field oxide film 2 is an insulating film for isolating each element of the integrated circuit. The gate oxide film 3 is a thin oxide film for forming the MO8 structure of the gate. Gate electrode 4 constitutes the gate of the FET.

The diffusion JI5 is a region in which impurities are diffused into the silicon substrate 1 using the gate electrode 4 as a mask, and is a region where impurities are diffused into the silicon substrate 1.
constitutes the source or drain of the The interlayer insulating film 6 is an insulating film that covers the entire upper surface of these.

Next, as shown in FIG. 1<b>, a photoresist is formed on the interlayer insulating film 6. The photoresist is used in a photolithography technique for opening a contact hole 8, which will be described next, and the upper center portion of the diffusion layer 5 is removed by exposing and developing a resist pattern.

Then, as shown in FIG. 1 (C1), a contact hole 8 is opened by reactive ion etching using this photoresist as a mask. Contact hole 8
is the interlayer insulating film 6 and gate oxidation other than the part masked by the photoresist! This is the hole formed by removing 3. Therefore, this contact hole 8
Inside, the central surface of the diffusion layer 5 in the silicon substrate 1 is exposed. In this way, the reactive ion etching method only removes the interlayer insulating film 6 and the gate oxide film 3, and should not affect the substrate silicon of the diffusion layer 5. However, in reality, during this reactive ion etching, the surface of the diffusion layer 5 exposed in the contact hole 8 is physically affected and altered, and a surface-altered portion 5a is formed in this surface layer. It turns out. Conventionally, this surface layer altered portion 5a has been a cause of increasing contact resistance.

After the contact hole 8 is formed, the photoresist is removed, and as shown in FIG. A melting point metal alloy such as titanium tungsten 9a is formed to have a thickness of about 3000 Å. The silicon substrate 1 on which the titanium-tungsten 9a has been formed is taken out of the vacuum and annealed in an ammonia gas atmosphere using ammonia gas as a specific gas as shown in FIG. Annealing is performed at a temperature of 600-100℃.
Preferably within minutes. In this example, a rapid thermal annealing (RTA) method using a halogen lamp was used.

It should be noted that if the annealing is performed at a higher temperature and for a longer time than the above-mentioned temperature and time, a silicide reaction will occur rapidly, resulting in destruction of the bond between the semiconductor substrate 1 and the titanium-tungsten 9a, which is not preferable. By this annealing, a nitride layer 9b having a thickness of about 100 to 500 layers is formed on the surface layer of the titanium tungsten 9a.

After this, using the DC magnetron sputtering method again, as shown in Fig.
As shown in h, aluminum silicon 9C is coated with a film thickness of about 9
It is formed on the upper surface of the nitride layer 19b by 1,000 people. The nitride layer 9b has low reactivity with aluminum, so crystal growth of the aluminum silicon 9c proceeds smoothly, and the crystal grain size is controlled and becomes large. This contributes to improving electromigration resistance. This formed aluminum silicon 9
A metal wiring film 9 is constituted by carbon, titanium tungsten 9a, and nitride layer 9b.

(G) Effects of the Invention According to this invention, by annealing, it is possible to remove the influence of the altered portion (damaged layer) on the surface of the substrate semiconductor, connect the metal wiring film to the semiconductor with low resistance, and at the same time Adhesion between the barrier metal and the underlying insulating film can also be improved. Furthermore, since a nitride layer is formed on the surface of the high melting point metal or its alloy, barrier properties are improved.

[Brief explanation of drawings]

1(a) to +f+ are manufacturing process explanatory diagrams showing an embodiment of the present invention, and FIGS. 2(J to 2C) are manufacturing process explanatory diagrams showing a conventional example. 1...Semiconductor Substrate, 6... Interlayer insulating film, 8... Contact hole, 9...
...Metal wiring film. Fuesen (a) First country (b) Figure (c) Figure (a) Figure (b) Figure (C) Figure (d) m (e)

Claims (1)

[Claims] 1. Form an insulating film on a semiconductor substrate, open a contact hole by removing a predetermined position of the insulating film by etching, and then apply a high melting point metal or its alloy to the upper surface of the insulating film and the inner surface of the contact hole. 1. A method for manufacturing a semiconductor device, which comprises forming a metal wiring film using a metal wiring film, and then annealing it in a specific gas atmosphere.