JP6706653B2 - Active matrix substrate - Google Patents

Description

The present invention relates to an active matrix substrate formed using an oxide semiconductor.

An active matrix substrate used in a liquid crystal display device or the like includes a switching element such as a thin film transistor (hereinafter, referred to as “TFT”) for each pixel. As such a TFT (hereinafter, “pixel TFT”), a TFT having an amorphous silicon film as an active layer (hereinafter, “amorphous silicon TFT”) or a TFT having a polycrystalline silicon film as an active layer (hereinafter, “Polycrystalline silicon TFT”) is widely used.

On the other hand, a technique is known in which peripheral circuits such as a drive circuit are monolithically (integrally) provided on a substrate. By forming the drive circuit monolithically, the non-display area can be narrowed and the cost can be reduced by simplifying the mounting process. In the present specification, TFTs that form a peripheral circuit monolithically formed on the active matrix substrate are referred to as “circuit TFTs”.

As a material for the active layer of the TFT, an oxide semiconductor may be used in place of amorphous silicon or polycrystalline silicon. Such a TFT is called an "oxide semiconductor TFT". An oxide semiconductor has higher mobility than amorphous silicon. Therefore, the oxide semiconductor TFT can operate at higher speed than the amorphous silicon TFT. Therefore, the oxide semiconductor TFT can be suitably used not only as a pixel TFT but also as a circuit TFT.

The active matrix substrate also includes a plurality of gate bus lines and a plurality of source bus lines. The gate electrode of the pixel TFT is electrically connected to one corresponding gate bus line, and the source electrode is electrically connected to one corresponding source bus line. Connected to. The gate electrode of the pixel TFT is often formed of the same conductive film as the gate bus line, and the source and drain electrodes are often formed of the same conductive film as the source bus line. In this specification, a layer formed of the same conductive film as the gate bus line is called a "gate metal layer", and a layer formed of the same conductive film as the source bus line is called a "source metal layer". For the gate metal layer and the source metal layer, a metal layer such as a copper (Cu) layer or an aluminum (Al) layer is used.

In recent years, particularly in large-sized display panels, higher resolution has been advanced. For example, a display panel having a resolution of "8K" (7680x4320 pixels) corresponding to four times "4K" (3840x2160 pixels) (or 16 times "full HD" (1920x1080 pixels)) has been developed.

As the display panel becomes larger and the definition becomes higher, the number of pixels increases and the writing time Tg per pixel becomes shorter. Therefore, it is necessary to reduce the time constant of the gate bus line, and it is required to further reduce the resistance of the gate metal layer.

In order to reduce the sheet resistance of the gate metal layer, it is preferable to use a Cu layer having a lower electric resistance than the Al layer for the gate metal layer. For example, in Patent Document 1, a Cu layer is used as a main layer of the gate metal layer, and titanium (Ti) is provided on the substrate side of the Cu layer for the purpose of ensuring adhesion between the Cu layer and the substrate surface (or the underlying surface). The provision of layers is disclosed. In this specification, such a laminated structure is referred to as a “Cu/Ti laminated metal structure”.

Japanese Patent No. 5685204

However, as a result of studies by the present inventors, there were cases where the sheet resistance of the gate metal layer could not be reduced to a desired value even if the Cu layer was used.

For example, when a gate metal layer having a Cu/Ti laminated metal structure is applied to an active matrix substrate, the following problems may occur.

In an active matrix substrate having a bottom gate type pixel TFT, a TFT process such as forming a gate insulating layer, a semiconductor layer and a source metal layer is performed after forming a gate metal layer on the substrate. In this TFT process, Ti contained in the lower layer of the gate metal layer may diffuse into the Cu layer under the influence of heat such as film formation by the plasma CVD method and annealing treatment for the oxide semiconductor layer. As a result, the Cu layer has a high resistance, and the sheet resistance of the gate metal layer becomes high.

As described above, conventionally, it was difficult to keep the sheet resistance of the gate metal layer low.

One embodiment of the present invention has been made in view of the above circumstances, and an object thereof is to provide an active matrix substrate having a low-resistance gate metal layer, or to have low resistance and adhesion. An object is to provide an active matrix substrate having an excellent gate metal layer.

This specification discloses the active matrix substrate described in the following items.
[Item 1]
An active matrix substrate having a plurality of pixel regions,
Board,
A source metal layer including a plurality of source bus lines supported on the substrate; and a gate metal layer including a plurality of gate bus lines,
A thin film transistor and a pixel electrode arranged in each of the plurality of pixel regions,
The thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, an oxide semiconductor layer disposed on the gate insulating layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer. And the gate electrode is formed in the gate metal layer and electrically connected to a corresponding one of the plurality of gate bus lines, and the source electrode is formed of the plurality of source bus lines. Electrically connected to the corresponding one, the drain electrode is electrically connected to the pixel electrode,
The gate metal layer has a laminated structure including a copper alloy layer and a copper layer, the copper alloy layer is the bottom layer of the gate metal layer, the copper layer is disposed on the copper alloy layer Cage,
The copper alloy layer is made of a copper alloy containing Cu and at least one additional metal element, the at least one additional metal element contains Al, and the content of Al in the copper alloy is 2 at% or more and 8 at% or less. There is an active matrix substrate.
[Item 2]
Item 2. The active matrix substrate according to item 1, wherein the at least one additional metal element further contains Mg.
[Item 3]
Item 3. The active matrix substrate according to Item 1 or 2, wherein the content of Mg in the copper alloy is 1 at% or more and 3 at% or less.
[Item 4]
4. The active matrix substrate according to any one of Items 1 to 3, wherein the content of Cu in the copper alloy is 80 at% or more.
[Item 5]
Item 5. The active matrix substrate according to any one of Items 1 to 4, wherein the at least one additive metal element does not contain P.
[Item 6]
The active according to any one of Items 1 to 5, wherein the gate insulating layer includes an oxygen-containing silicon layer that is in direct contact with an upper surface of the copper layer, and the oxygen-containing silicon layer is a silicon oxide layer or a silicon oxynitride layer. Matrix substrate.
[Item 7]
The oxygen-containing silicon layer is a silicon oxynitride layer represented by SiOxNy (2>x>0, 4/3>y>0), and x and y are 0.4≦x/(x+y)<1. 7. The active matrix substrate according to item 6, which satisfies:
[Item 8]
8. The active matrix substrate according to item 7, wherein the x and the y satisfy x≧y.
[Item 9]
The gate insulating layer is the oxygen-containing silicon layer, another oxygen-containing silicon layer that is in direct contact with the oxide semiconductor layer, and silicon nitride located between the oxygen-containing silicon layer and the other oxygen-containing silicon layer. Has a laminated structure including layers,
9. The active matrix substrate according to any of items 6 to 8, wherein the other oxygen-containing silicon layer is a silicon oxide layer or a silicon oxynitride layer.
[Item 10]
The other oxygen-containing silicon layer is a silicon oxide layer,
10. The active matrix substrate according to item 9, wherein the gate insulating layer further includes an intermediate layer made of silicon oxynitride between the other oxygen-containing silicon layer and the silicon nitride layer.
[Item 11]
11. The active matrix substrate according to any one of Items 1 to 10, wherein the thickness of the copper alloy layer is smaller than the thickness of the copper layer.
[Item 12]
12. The active matrix substrate according to any one of Items 1 to 11, wherein the copper alloy layer has a thickness of 30 nm or more.
[Item 13]
13. The active matrix substrate according to any one of Items 1 to 12, wherein the gate metal layer has a total thickness of 550 nm or less, and the gate metal layer has a sheet resistance of 0.05 Ω/□ or less.
[Item 14]
14. The active matrix substrate according to any one of Items 1 to 13, wherein the substrate is a glass substrate, and the copper alloy layer is in direct contact with the surface of the glass substrate.
[Item 15]
An active matrix substrate having a plurality of pixel regions,
Board,
A source metal layer including a plurality of source bus lines supported on the substrate; and a gate metal layer including a plurality of gate bus lines,
A thin film transistor and a pixel electrode arranged in each of the plurality of pixel regions,
The thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, an oxide semiconductor layer disposed on the gate insulating layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer. And the gate electrode is formed in the gate metal layer and electrically connected to a corresponding one of the plurality of gate bus lines, and the source electrode is formed of the plurality of source bus lines. Electrically connected to the corresponding one, the drain electrode is electrically connected to the pixel electrode,
The gate metal layer includes a copper layer that is in direct contact with the gate insulating layer,
The gate insulating layer includes a first oxygen-containing silicon layer in direct contact with the oxide semiconductor layer, a second oxygen-containing silicon layer in direct contact with an upper surface of the copper layer, and the first oxygen-containing silicon layer and the A laminated structure including a silicon nitride layer located between the second oxygen-containing silicon layer,
The active matrix substrate, wherein the first oxygen-containing silicon layer and the second oxygen-containing silicon layer are silicon oxide layers or silicon oxynitride layers.
[Item 16]
The second oxygen-containing silicon layer is a silicon oxynitride layer represented by SiOxNy (2>x>0, 4/3>y>0), and x and y are 0.4≦x/(x+y). ) The active matrix substrate according to item 15, which satisfies <1.
[Item 17]
17. The active matrix substrate according to item 16, wherein the x and the y satisfy x≧y.
[Item 18]
Item 18. The active matrix substrate according to any one of Items 15 to 17, wherein the first oxygen-containing silicon layer is a silicon oxide layer.
[Item 19]
19. The active matrix substrate according to item 18, further comprising an intermediate layer made of silicon oxynitride between the first oxygen-containing silicon layer and the silicon nitride layer.
[Item 20]
20. The active matrix substrate according to any one of Items 1 to 19, wherein the oxide semiconductor layer contains In, Ga and Zn.
[Item 11]
Item 11. The active matrix substrate according to item 10, wherein the oxide semiconductor layer includes an In-Ga-Zn-O-based semiconductor.
[Item 12]
12. The active matrix substrate according to item 11, wherein the oxide semiconductor layer includes a crystalline portion.

According to an embodiment of the present invention, an active matrix substrate having a low resistance gate metal layer can be provided, or an active matrix substrate having a low resistance and excellent adhesion is provided. it can.

It is a schematic diagram showing an example of a plane structure of active matrix substrate 1000 of a 1st embodiment. (A) is a schematic plan view of the TFT 101 in the active matrix substrate of the first embodiment, and (b) and (c) are respectively taken along line AA′ and line BB′ of the TFT 101. It is the typical cross section along. It is a figure which shows the relationship between the thickness of a gate metal layer, and sheet resistance. (A) is a figure which shows the cross-sectional SEM image of the active matrix substrate of an Example, (b) is a figure which shows the cross-sectional SEM image of the active matrix substrate of a comparative example. It is a figure which shows the transmittance|permeability with respect to the visible light of the display panel of an Example and a comparative example. It is a figure which shows the relationship between the sheet resistance of a gate, and a time constant. It is a sectional view for explaining the structure of a gate insulating layer. (A) And (b) is sectional drawing which illustrates another gate insulating layer, respectively. (A) And (b) is sectional drawing which illustrates the active matrix substrate of 2nd Embodiment, respectively.

(First embodiment)
The present inventor has repeatedly studied a wiring structure that can achieve both low sheet resistance and high adhesion. As a result, they have found that by providing a Cu alloy layer having a predetermined composition on the substrate side of the Cu layer, it is possible to improve the adhesion to the substrate surface while ensuring a low sheet resistance. In this specification, such a structure is referred to as a "Cu/Cu alloy laminated metal structure".

An embodiment of an active matrix substrate according to the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing an example of a planar structure of an active matrix substrate 1000 of this embodiment.

The active matrix substrate 1000 has a display region DR and a region (non-display region or frame region) FR other than the display region DR. The display region DR is composed of pixel regions Pix arranged in a matrix. The pixel area Pix is an area corresponding to the pixel of the display device, and may be simply referred to as “pixel”. Each pixel region Pix has a TFT 101, which is a pixel TFT, and a pixel electrode PE. Although not shown, when the active matrix substrate 1000 is applied to a horizontal electric field mode display device such as an FFS (Fringe Field Switching) mode, the active matrix substrate 1000 includes a pixel electrode PE and an insulating layer (dielectric layer). Common electrodes are provided so as to face each other.

The non-display area FR is an area located around the display area DR and does not contribute to the display. The non-display area FR includes a terminal portion formation area in which a terminal portion is formed, a drive circuit formation area in which a drive circuit is integrally (monolithically) provided, and the like. In the drive circuit formation region, for example, a gate driver GD, an inspection circuit (not shown), etc. are monolithically provided. The source driver SD is mounted on, for example, the active matrix substrate 1000.

In the display region DR, a plurality of source bus lines SL extending in a first direction (here, column direction) and a plurality of gate bus lines extending in a second direction (here, row direction) intersecting the first direction. GL is formed. Each pixel is defined by the gate bus line GL and the source bus line SL, for example. The gate bus lines GL are connected to the respective terminals of the gate driver GD. The source bus lines SL are connected to the respective terminals of the source driver SD mounted on the active matrix substrate 1000.

<Structure of Pixel Region Pix>
Next, the structure of each pixel region Pix in the active matrix substrate 1000 will be described. Here, an active matrix substrate applied to an FFS mode LCD panel will be described as an example.

2A is a plan view of one pixel region Pix in the active matrix substrate 1000, and FIGS. 2B and 2C are lines AA′ and B- in FIG. 2A, respectively. It is sectional drawing which followed the B'line.

The pixel region Pix is a region surrounded by the source bus line SL and the gate bus line GL. The pixel region Pix has the substrate 1, the TFT 101 supported by the substrate 1, the lower transparent electrode 15, and the upper transparent electrode 19. In this example, the lower transparent electrode 15 is the common electrode CE and the upper transparent electrode 19 is the pixel electrode PE. The lower transparent electrode 15 may be the pixel electrode PE and the upper transparent electrode 19 may be the common electrode CE.

The TFT 101 is, for example, a channel-etch type bottom gate structure TFT. The TFT 101 includes a gate electrode 3, a gate insulating layer 5 covering the gate electrode 3, an oxide semiconductor layer 7 arranged on the gate insulating layer 5, and a source electrode 8 electrically connected to the oxide semiconductor layer 7. And a drain electrode 9.

The gate electrode 3 is formed in the gate metal layer including the plurality of gate bus lines GL. That is, the gate electrode 3 and the gate bus line GL are formed using the same conductive film. The gate electrode 3 is electrically connected to the corresponding one of the plurality of gate bus lines GL. As shown, the gate electrode 3 and the corresponding gate bus line GL may be integrally formed.

In this embodiment, the gate metal layer has a laminated structure (Cu/Cu alloy laminated metal structure) including the copper alloy layer g1 and the copper layer g2 from the substrate 1 side.

The copper alloy layer g1 is the lowermost layer of the gate metal layer and is in direct contact with the surface of the substrate 1, for example. Although not shown, when a base insulating film is provided between the substrate 1 and the gate metal layer, the copper alloy layer g1 is in direct contact with the base insulating film. The copper layer g2 is arranged on the copper alloy layer g1. The copper layer g2 may be in contact with the upper surface of the copper alloy layer g1.

The copper alloy layer g1 is a layer made of a Cu alloy containing Cu and at least one additive metal element. The additive metal element of the Cu alloy contains Al, and the content of Al in the Cu alloy is 2 at% or more and 8 at% or less. By containing 2 at% or more of Al, the adhesion to the substrate surface can be improved. Moreover, since the corrosion resistance of the gate metal layer can be improved, the reliability can be improved. On the other hand, when the content of Al is 8 at% or less, it is possible to suppress the resistance increase of the copper layer g2 due to the oxidation of the copper layer g2 by Al.

The Cu alloy may be a Cu-Al alloy (binary system). Alternatively, the Cu alloy may include other metal elements such as Mg, Ca, Mo, and Mn in addition to Al as an additional metal element. The types and contents of other metal elements are not particularly limited. However, it is preferable that the Cu alloy does not contain phosphorus (P), sodium (Na), boron (B), etc. from the viewpoint of impurities to the semiconductor.

As an example, the Cu alloy may include Al and Mg as additional metal elements. By adding Mg in addition to Al, the reliability such as corrosion resistance can be further enhanced and the stability of the Cu alloy can be improved. In this case, the content of Mg may be, for example, 1 at% or more and 3 at% or less. The content of Mg may be equal to or less than the content of Al. The Cu alloy may be a Cu-Al-Mg alloy (ternary system) or may further contain another metal element.

In the present specification, the “Cu alloy” refers to an alloy containing Cu as a main metal element. The Cu content in the Cu alloy is, for example, 80 at% or more and 98 at% or less.

The copper layer g2 is a layer containing Cu as a main component. The Cu content in the copper layer g2 may be, for example, 90% or more. Preferably, the copper layer g2 is a pure Cu layer (Cu content ratio: for example, 99.99% or more).

The copper alloy layer g1 and the copper layer g2 may contain unavoidable impurities.

The oxide semiconductor layer 7 is arranged so that at least a part thereof overlaps with the gate electrode 3 with the gate insulating layer 5 interposed therebetween. The oxide semiconductor layer 7 is, for example, an In-Ga-Zn-O-based semiconductor layer.

The source electrode 8 and the drain electrode 9 are arranged so as to be in contact with part of the upper surface of the oxide semiconductor layer 7, respectively. A portion of the oxide semiconductor layer 7 which is in contact with the source electrode 8 is called a source contact region and a portion of which is in contact with the drain electrode 9 is called a drain contact region. The region located between the source contact region and the drain contact region and overlapping with the gate electrode 3 when viewed in the normal direction of the substrate 1 is a “channel region”. The source electrode 8 is electrically connected to the corresponding one of the plurality of source bus lines SL. The drain electrode 9 is electrically connected to the pixel electrode PE.

The source electrode 8 and the drain electrode 9 may be formed in the source metal layer including the plurality of source bus lines SL. That is, the source electrode 8, the drain electrode 9 and the source bus line SL may be formed using the same conductive film. The source electrode 8 may be integrally formed with the corresponding source bus line SL.

The TFT 101, the gate metal layer and the source metal layer are covered with the interlayer insulating layer 13. The interlayer insulating layer 13 is not particularly limited, but may include, for example, an inorganic insulating layer (passivation film) 11 and an organic insulating layer 12 arranged on the inorganic insulating layer 11. The inorganic insulating layer 11 may be in contact with the channel region of the TFT 101. The interlayer insulating layer 13 does not have to include the organic insulating layer.

On the inter-layer insulating layer 13, a lower transparent electrode 15 that serves as the common electrode CE, a dielectric layer 17, and an upper transparent electrode 19 that serves as the pixel electrode PE are provided. The pixel electrode PE and the common electrode CE are arranged on the interlayer insulating layer 13 so as to partially overlap with each other with the dielectric layer 17 interposed therebetween. The pixel electrode PE is separated for each pixel. The common electrode CE does not need to be separated for each pixel. Here, the common electrode CE is formed on the interlayer insulating layer 13. The pixel electrode PE is formed on the dielectric layer 17, and is electrically connected to the drain electrode 9 in the contact hole CH provided in the interlayer insulating layer 13 and the dielectric layer 17. In this example, the contact hole CH is a portion where the opening 13p of the interlayer insulating layer 13 and the opening 17p of the dielectric layer 17 overlap. Although not shown, the pixel electrode PE has at least one slit or notch for each pixel. The common electrode CE has an opening 15p in a region where the contact hole CH is formed. The common electrode CE may be formed over the entire pixel region Pix except this region.

Such an active matrix substrate 1000 can be applied to, for example, an FFS mode display device. The FFS mode is a lateral electric field mode mode in which a pair of electrodes (pixel electrode PE and common electrode CE) are provided on one substrate and an electric field is applied to liquid crystal molecules in a direction (horizontal direction) parallel to the substrate surface. is there.

The active matrix substrate of this embodiment may be applied to a vertical electric field drive type display device such as a VA mode. In that case, the common electrode CE is formed on the counter substrate which is arranged to face the active matrix substrate with the liquid crystal layer interposed therebetween.

<Effects of this embodiment>
In the active matrix substrate 1000 of this embodiment, since the copper alloy layer g1 is provided on the substrate side of the copper layer g2 of the gate metal layer, the adhesion to the surface of the substrate 1 can be improved.

As described above, in the conventional gate metal layer having the Cu/Ti laminated metal structure, the sheet resistance may increase due to the diffusion of Ti into the Cu layer due to the influence of heat in the TFT process. On the other hand, in this embodiment, the gate metal layer can maintain a low sheet resistance even after the TFT process. This is because the content of metal elements other than Cu (such as Al) in the lower layer of the gate metal layer is suppressed (for example, the total content of added metal elements is 5% when the content of Cu is 95%). This is because even if the metal element diffuses into the copper layer g2, the resistance increase of the copper layer g2 due to the diffusion is suppressed. Therefore, a gate metal layer having low sheet resistance and excellent adhesion can be realized.

The Cu content in the copper alloy layer g1 may be, for example, 80 at% or more. As a result, the total content of the additive metal elements such as Al is suppressed to 20 at% or less, so that the resistance increase of the copper layer g2 due to the diffusion of the additive metal elements can be suppressed more effectively.

The copper alloy layer g1 preferably has a thickness of, for example, 30 nm or more. Thereby, the adhesiveness to the surface (or the base surface) of the substrate 1 can be further enhanced. On the other hand, the thickness of the copper alloy layer g1 may be 100 nm or less, for example. As a result, it is possible to suppress an increase in the thickness of the entire gate metal layer. The thickness of the copper alloy layer g1 may be smaller than the thickness of the copper layer g2. By thickening the copper layer g2 having a low electric resistance, the sheet resistance of the gate metal layer can be reduced more effectively.

The present embodiment also has the following advantages. When forming a conventional gate metal layer having a Cu/Ti laminated metal structure, for example, a hydrogen peroxide-based etching solution containing ammonium fluoride and/or ammonium acid fluoride is used for patterning the gate metal layer. Be done. This etches both the Cu and Ti layers. However, when the gate metal layer is directly formed on the surface of the glass substrate, the surface portion of the underlying glass substrate is also etched along the gate pattern, which may reduce the strength of the glass substrate. On the other hand, in the present embodiment, it is possible to use a hydrogen peroxide-based etching solution containing neither ammonium fluoride nor acidic ammonium fluoride for patterning the gate metal layer. Both the copper layer g2 and the copper alloy layer g1 are etched by this etching solution, but the glass substrate is hardly etched. Therefore, the over-etching of the glass substrate can be suppressed, and the strength of the glass substrate can be secured.

In addition, by using a hydrogen peroxide-based etching solution containing neither ammonium fluoride nor acidic ammonium fluoride, the gate metal can be used as compared with the case of using a hydrogen peroxide-based etching solution containing ammonium fluoride and/or acidic ammonium fluoride. There is also an advantage that the shift amount on the side surface of the layer can be reduced.

Further, in the display panel using the active matrix substrate of the present embodiment, the backlight light reflected on the lower surface of the Cu alloy layer can be reused, so that the gate metal layer having the Cu/Ti laminated metal structure is used. The transmittance with respect to visible light can be improved as compared with the conventional display panel.

<Structure of gate insulating layer>
Here, an example of the structure of the gate insulating layer 5 in the present embodiment will be described.

The gate insulating layer 5 includes a silicon oxide (SiOx, 0<x≦2) layer, a silicon nitride (SiNz, 0<z<4/3) layer, a silicon oxynitride (SiOxNy, 2>x>0, 4/3). >y>0) layers and the like can be used. The gate insulating layer 5 may have a laminated structure. As used herein, "silicon oxynitride" refers to silicon oxynitride in which the oxygen ratio x is larger than the nitrogen ratio y (x>y) and silicon oxynitride in which the nitrogen ratio y is larger than the oxygen ratio x (y>x). Including. In this specification, silicon layers (insulating layers) containing oxygen such as silicon oxide and silicon oxynitride are collectively referred to as “oxygen-containing silicon layers”.

FIG. 7 is a diagram for explaining the structure of the gate insulating layer in the TFT 101, and shows a cross-sectional structure taken along the line A-A′ in FIG.

As illustrated in FIG. 7, the gate insulating layer 5 is a stacked layer including a silicon nitride layer n and an oxygen-containing silicon layer (hereinafter referred to as a first oxygen-containing silicon layer) a1 disposed on the silicon nitride layer n. It may have a structure. The first oxygen-containing silicon layer a1 is the uppermost layer of the gate insulating layer 5 and is in direct contact with the oxide semiconductor layer 7. The first oxygen-containing silicon layer a1 is preferably a silicon oxide layer. The first oxygen-containing silicon layer a1 may be a silicon oxynitride (SiOxNy, x>y) layer. Further, a silicon nitride oxide (SiOxNy, y>x) layer may be used instead of the silicon nitride layer n. However, it is preferable to use the silicon nitride layer n having excellent moisture impermeability.

When the first oxygen-containing silicon layer (eg, an oxide layer such as SiO ₂ ) a1 is used as the uppermost layer of the gate insulating layer 5 (that is, a layer in contact with the oxide semiconductor layer), the oxide semiconductor layer 7 has oxygen vacancies. When it occurs, oxygen deficiency can be recovered by oxygen contained in the oxide layer, so that oxygen deficiency in the oxide semiconductor layer 7 can be reduced. Further, by providing the silicon nitride layer n having excellent barrier properties on the substrate 1 side of the first oxygen-containing silicon layer a1, it is possible to effectively diffuse impurities and the like from the substrate 1 into the oxide semiconductor layer 7. It can be prevented.

<Modification>
The gate insulating layer 5 may include an oxygen-containing silicon layer that is in contact with the upper surface of the copper layer g2. The oxygen-containing silicon layer is a film having higher stability than the silicon nitride layer, and the amount of impurities contained in the oxygen-containing silicon layer is smaller than that of the silicon nitride layer. Therefore, when the oxygen-containing silicon layer (hereinafter referred to as the second oxygen-containing silicon layer) is arranged as the lowermost layer of the gate insulating layer 5, the diffusion of impurities from the gate insulating layer 5 to the copper layer g2 is suppressed. Therefore, the sheet resistance of the gate metal layer (copper layer g2) can be more effectively reduced, and the variation in sheet resistance can be suppressed.

8A and 8B are cross-sectional views for explaining the gate insulating layer 5 in the active matrix substrates of Modifications 1 and 2, respectively. Hereinafter, differences from the gate insulating layer 5 shown in FIG. 7 will be mainly described, and common description will be appropriately omitted.

As shown in FIG. 8A, the gate insulating layer 5 of Modification 1 further includes a second oxygen-containing silicon layer a2 on the substrate 1 side of the silicon nitride layer n, and thus the gate insulating layer shown in FIG. Different from 5. That is, the gate insulating layer 5 of Modification 1 includes the first oxygen-containing silicon layer a1 that is in direct contact with the oxide semiconductor layer 7, the second oxygen-containing silicon layer a2 that is in direct contact with the upper surface of the copper layer g2, and the first oxygen-containing silicon layer a2. Has a laminated structure including the silicon nitride layer n located between the oxygen-containing silicon layer a1 and the second oxygen-containing silicon layer a2.

The second oxygen-containing silicon layer a2 is a silicon oxide layer (SiOx, 2>x>0) or a silicon oxynitride layer (SiOxNy, 2>x>0, 4/3>y>0). Among these, it is preferable to use the silicon oxynitride layer from the viewpoint of ensuring the adhesion to the surface of the copper layer g2. The oxygen ratio x and the nitrogen ratio y in the second oxygen-containing silicon layer a2 can be set to satisfy, for example, 0.4≦x/(x+y)<1. By increasing the oxygen content rate such that x/(x+y) is 0.4 or more, the stability of the second oxygen-containing silicon layer a2 can be ensured, so that the diffusion of impurities into the copper layer g2 is more effective. Can be suppressed. Preferably, the oxygen ratio x is greater than or equal to the nitrogen ratio y (x≧y), and more preferably the oxygen ratio x is greater than the nitrogen ratio y (x>y, that is, x/(x+y)>0.5). On the other hand, when x/(x+y) is 0.8 or less (x/(x+y)≦0.8), the adhesion of the copper layer g2 to the surface can be more reliably enhanced.

The second oxygen-containing silicon layer a2 may be a graded layer in which the oxygen ratio x and the nitrogen ratio y change in the thickness direction. In this case, the composition (x, y) of the lower surface (the surface in contact with the gate metal layer) of the second oxygen-containing silicon layer a2 should satisfy the above relationship.

As shown in FIG. 8B, the gate insulating layer 5 of Modification 2 further includes an intermediate layer b made of silicon oxynitride between the first oxygen-containing silicon layer a1 and the silicon nitride layer n. Therefore, it is different from the gate insulating layer 5 of Modification 1.

Between the first oxygen-containing silicon layer a1 (refractive index: for example, 1.4 to 1.5) and the silicon nitride layer n (refractive index: for example, 1.9 to 2.0), an intermediate refractive index between them is provided. By providing the intermediate layer b, the interface reflection is reduced. As a result, the interference color can be suppressed more effectively.

The composition of the intermediate layer b is not particularly limited. For example, the oxygen ratio x and the nitrogen ratio y in the intermediate layer b may be set so as to satisfy 0.3≦x/(x+y)≦0.7. For example, x:y may be set to be about 1:1. The intermediate layer b may be a graded layer in which the oxygen ratio x and the nitrogen ratio y change in the thickness direction.

In Modifications 1 and 2, the thickness of each layer forming the gate insulating layer 5 is not particularly limited.

The silicon nitride layer n is preferably thicker than the first oxygen-containing silicon layer a1, the second oxygen-containing silicon layer a2, and the intermediate layer b. Thereby, the barrier property of the gate insulating layer 5 can be further improved. The thickness of the silicon nitride layer n is, for example, 100 nm or more and 500 nm or less.

The thickness of the first oxygen-containing silicon layer a1 may be, for example, 15 nm or more and less than the thickness of the silicon nitride layer n. If it is 15 nm or more, oxygen vacancies in the oxide semiconductor layer 7 can be reduced more reliably.

The thickness of the second oxygen-containing silicon layer a2 may be, for example, 20 nm or more and less than the thickness of the silicon nitride layer n. When the thickness is 20 nm or more, the diffusion of impurities into the copper layer g2 can be suppressed more reliably.

The thickness of the intermediate layer b is not particularly limited, but may be, for example, 100 nm or more and less than the thickness of the silicon nitride layer n. If it is 100 nm or more, a moisture permeation preventing effect can be obtained.

The laminated structure of the gate insulating layer 5 in the present embodiment is not limited to the structure illustrated in FIGS. The gate insulating layer 5 may have a laminated structure of five layers or more. For example, a plurality of intermediate layers b may be included. Alternatively, another intermediate layer may be included between the second oxygen-containing silicon layer a2 and the silicon nitride layer n.

<Method of manufacturing TFT 101>
Hereinafter, an example of a method for manufacturing the TFT 101 will be described with reference to FIG.

First, a gate metal layer including the gate electrode 3 and the gate bus line GL is formed on the substrate 1.

As the substrate 1, for example, a glass substrate, a silicon substrate, a heat-resistant plastic substrate (resin substrate), or the like can be used.

The gate metal layer is formed as follows. First, a laminated metal film is obtained by forming a Cu alloy film and a Cu film in this order on a substrate (for example, a glass substrate) 1 by a sputtering method or the like. Next, wet etching of the laminated metal film is performed. For wet etching, a hydrogen peroxide-based etching solution (containing no ammonium fluoride or acidic ammonium fluoride) is used. As a result, a gate metal layer having a laminated metal structure in which the copper alloy layer g1 is the lower layer and the copper layer g2 is the upper layer is obtained. The gate metal layer includes the gate electrode 3 and the gate bus line GL.

The gate metal layer has only to include the copper alloy layer g1 and the copper layer g2, and may have a laminated structure of three or more layers. For example, you may have the further Cu alloy layer on the copper layer g2. However, for patterning by wet etching using a hydrogen peroxide-based etching solution, it is preferable that the gate metal layer does not include a Ti layer, a W layer, or an alloy thereof.

Next, the gate insulating layer 5 is formed so as to cover the gate metal layer. The gate insulating layer 5 can be formed by a CVD method or the like.

As the gate insulating layer 5, a silicon oxide (SiO ₂ ) layer, a silicon nitride (SiNz) layer, a silicon oxynitride (SiOxNy; x>y) layer, a silicon nitride oxide (SiNzOy; x>y) layer, or the like is appropriately used. You can These layers can be formed by a known method (for example, a CVD method, a plasma CVD method, etc.).

As the gate insulating layer 5, as described above with reference to FIG. 7, for example, a silicon nitride layer, a silicon nitride oxide layer, or the like is formed on the substrate side (lower layer) to prevent diffusion of impurities and the like from the substrate 1. Alternatively, a silicon oxide layer, a silicon oxynitride layer, or the like may be formed over the layer (upper layer) thereover in order to ensure insulating properties. Here, a laminated film including a SiNz film having a thickness of 300 nm and a SiO ₂ film having a thickness of 50 nm in this order may be formed from the substrate 1 side (see FIG. 7).

Alternatively, as the gate insulating layer 5, as described above with reference to FIG. 8A, a SiOxNy (for example, x≧y) layer having a thickness of 100 nm is used as the second oxygen-containing silicon layer a2, and a silicon nitride layer n is used as the thickness. A laminated film including a SiNz layer having a thickness of 300 nm and a SiO ₂ layer having a thickness of 50 nm as the first oxygen-containing silicon layer a1 may be formed in this order. When using the plasma CVD method, the composition of the SiOxNy layer can be controlled by adjusting the flow rate ratio between the source gas (SiH ₄ ) and the reaction gases (NH ₃ , N ₂ and N ₂ O). For example, the SiOxNy layer may be formed at a flow rate ratio such that x:y is approximately 1:1. The flow rate ratio may be changed stepwise or continuously so that x:y changes in the thickness direction of the SiOxNy layer.

Alternatively, as the gate insulating layer 5, as described above with reference to FIG. 8B, a SiOxNy (for example, x≧y) layer having a thickness of 100 nm and a silicon nitride layer n having a thickness of 100 nm are used as the second oxygen-containing silicon layer a2. A SiNz layer having a thickness of 300 nm, a SiOxNy layer having a thickness of 100 nm as the intermediate layer b (for example, x:y=about 1:1), and a SiO ₂ layer having a thickness of 50 nm as the first oxygen-containing silicon layer a1 in this order. You may form the laminated film containing. When the plasma CVD method is used, the composition of the second oxygen-containing silicon layer a2 and the SiOxNy layer to be the intermediate layer b can be controlled by adjusting the flow rate ratio of the source gas and the reaction gas. The composition (x:y) of the second oxygen-containing silicon layer a2 and the intermediate layer b may be the same or different. As the second oxygen-containing silicon layer a2 and the intermediate layer b, for example, a SiOxNy layer may be formed at a flow rate ratio such that x:y is approximately 1:1.

Then, an oxide semiconductor film (for example, an In-Ga-Zn-O-based semiconductor film) is formed over the gate insulating layer 5 by using, for example, a sputtering method. The thickness of the oxide semiconductor film may be, for example, 30 nm or more and 200 nm or less. After that, the oxide semiconductor film may be annealed. Here, heat treatment is performed at a temperature of 300° C. to 500° C. in an air atmosphere. The heat treatment time is, for example, 30 minutes or more and 2 hours or less. Next, the oxide semiconductor film is patterned to obtain the oxide semiconductor layer 7.

Then, a source metal layer including the source electrode 8 and the drain electrode 9 and the source bus line SL is formed.

The source metal layer may have a single layer structure or a laminated structure. Here, a Ti film (thickness: 30 nm) and a Cu film (thickness: 300 nm) are formed in this order from the oxide semiconductor layer 7 side, and the obtained laminated film is patterned to form a source metal layer. obtain. The upper layer Cu film may be patterned by wet etching using a hydrogen peroxide-based etching solution, and then the lower layer Ti film may be patterned by dry etching.

The material of the source metal layer is, for example, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), or an alloy thereof. Alternatively, a metal nitride thereof can be used as appropriate. After that, the channel region of the oxide semiconductor layer 7 may be subjected to oxidation treatment, for example, plasma treatment using N ₂ O gas. In this way, the TFT 101 is obtained.

Next, the inorganic insulating layer 11 is formed so as to be in contact with the channel region of the TFT 101. The inorganic insulating layer 11 is, for example, a silicon oxide (SiO ₂ ) film, a silicon nitride (SiNz) film, a silicon oxynitride (SiOxNy; x>y) film, a silicon nitride oxide (SiNzOy; x>y) film, or the like. Good. Here, as the inorganic insulating layer, a SiO ₂ layer having a thickness of, for example, 300 nm is formed by a CVD method. The formation temperature of the inorganic insulating layer may be, for example, 200° C. or higher and 450° C. or lower. Although not shown, an organic insulating layer may be formed on the inorganic insulating layer 11. As the organic insulating layer, for example, a positive photosensitive resin film having a thickness of 2000 nm may be formed.

On the inter-layer insulating layer 13, a lower transparent electrode 15 that serves as the common electrode CE, a dielectric layer 17, and an upper transparent electrode 19 that serves as the pixel electrode PE are provided. The pixel electrode PE and the common electrode CE are each formed of, for example, an ITO (indium/tin oxide) film, an In—Zn—O-based semiconductor (indium/zinc oxide) film, a ZnO film (zinc oxide film), or the like. May be. The pixel electrode PE and the common electrode CE may each have a thickness of, for example, 50 nm or more and 200 nm or less. The dielectric layer 17 may be, for example, a silicon nitride (SiNz) film, a silicon oxide (SiOx) film, a silicon oxynitride (SiOxNy; x>y) film, a silicon nitride oxide (SiNzOy; x>y) film, or the like. Good. The thickness of the dielectric layer 17 may be, for example, 70 nm or more and 300 nm or less.

(Second embodiment)
9A and 9B are cross-sectional views illustrating the active matrix substrate of the second embodiment, respectively.

In the active matrix substrate of this embodiment, the gate insulating layer 5 includes the first oxygen-containing silicon layer a1 that is in direct contact with the oxide semiconductor layer 7, the second oxygen-containing silicon layer a2 that is in direct contact with the upper surface of the copper layer g2, and , A silicon nitride layer n located between the first oxygen-containing silicon layer a1 and the second oxygen-containing silicon layer a2. As illustrated in FIG. 9B, the gate insulating layer 5 may further include a silicon oxynitride layer (intermediate layer) b between the silicon nitride layer n and the first oxygen-containing silicon layer a1. The specific material and thickness of each layer are the same as the material and thickness described above with reference to FIGS.

In this embodiment, the gate metal layer may include the Cu layer. As shown in the figure, it may have a laminated structure in which the copper layer g2 is an upper layer and the metal layer (for example, a copper alloy layer, a Ti layer or a Mo layer) m1 which can have high adhesion is a lowermost layer. The lowermost metal layer m1 of the gate metal layer may be a copper alloy layer containing Cu and at least one additional metal element. The type and amount of the added metal element are not particularly limited. That is, as the metal layer m1, a copper alloy layer having a composition different from that of the copper alloy layer g1 in the above-described embodiment may be used. Further, the metal layer m1 which is the lowermost layer of the gate metal layer may be a Ti layer or a Mo layer. The gate metal layer may be a single layer of Cu layer.

According to the present embodiment, by providing the second oxygen-containing silicon layer a2 as the lowermost layer of the gate insulating layer 5, it is possible to reduce the diffusion of impurities from the gate insulating layer 5 to the copper layer g2. Regardless of the material, increase in sheet resistance of the gate metal layer and variation in sheet resistance due to diffusion of impurities can be suppressed.

(Examples and Comparative Examples)
<Evaluation of sheet resistance of gate metal layer>
The active matrix substrates of Examples 1 and 2 and the comparative example were produced, and the sheet resistances of the gate metal layers were compared.

-Method for Producing Active Matrix Substrate of Example 1 First, a gate metal layer having a Cu/Cu alloy laminated metal structure was formed on a glass substrate (thickness: 0.7 mm).

Next, a gate insulating layer including the second oxygen-containing silicon layer a2, the silicon nitride layer n, and the first oxygen-containing silicon layer a1 was formed so as to cover the gate metal layer. In Example 1, a silicon oxynitride layer (thickness: 100 nm), a silicon nitride layer n (thickness: 300 nm), and a first oxygen-containing silicon layer were formed as the second oxygen-containing silicon layer a2 on the gate metal layer. A silicon oxide layer (thickness: 50 nm) was formed in this order as the layer a1. A plasma CVD method was used to form these films. When forming a silicon oxynitride (SiOxNy) film, the flow rates of the source gas (SiH ₄ ) and the reaction gas (NH ₃ , N ₂ and N ₂ O) are set so that x:y becomes approximately 1:1. The ratio was set.

Subsequently, by forming the source metal layer including the source and drain electrodes and the pixel TFT, five sample substrates A1 to C1 were produced.

Manufacturing Method of Active Matrix Substrate of Second Embodiment In the second embodiment, a gate insulating layer including the silicon nitride layer n and the first oxygen-containing silicon layer a1 and not including the second oxygen-containing silicon layer a2 is formed. did. Specifically, a silicon nitride layer n (thickness: 400 nm) and a silicon oxide layer (thickness: 50 nm) as the first oxygen-containing silicon layer a1 were formed in this order on the gate metal layer. These films were formed by using the plasma CVD method as in Example 1. Five sample substrates A2 and C2 were produced in the same manner as in Example 1 except for the gate insulating layer.

-Method for Manufacturing Active Matrix Substrate of Comparative Example A sample substrate D was manufactured in the same manner as in Example 2 except that a gate metal layer having a Cu/Ti laminated metal structure was used as the active matrix substrate of the comparative example.

Table 1 shows the thickness and composition of the gate metal layer and the gate insulating layer of each sample substrate.

Then, the sheet resistance (average value) of the gate metal layer in each sample substrate was measured. Results are shown in FIG.

From the results shown in FIG. 3, it is confirmed that the sheet resistance can be reduced by changing the material of the lower layer of the gate metal layer from Ti to Cu—Al alloy. The reason for this is considered as follows.

When the lower layer of the gate metal layer is the Ti layer (sample substrate D), Ti diffuses into the upper Cu layer under the influence of heat in the TFT process. As a result, the Cu layer has a high resistance, and the sheet resistance of the gate metal layer is high. On the other hand, in the gate metal layer having the Cu/Cu alloy laminated metal structure (sample substrates A1 to C1, A2, and C2), the resistance increase of the Cu layer due to the TFT process is suppressed. This is because the Cu alloy layer contains a small amount of Al (here, 3 at %), and even if a part of Al diffuses into the Cu layer, the electric resistance of the Cu layer does not become as high as that of the sample substrate D. Be done.

For example, when the thickness of the gate metal layer is 550 nm, the sheet resistance of the gate metal layer having the Cu/Cu alloy laminated metal structure is 0.04 Ω/□, which is half that of the gate metal layer having the Cu/Ti laminated metal structure. It can be seen that it is reduced to some extent.

Further, as can be seen from FIG. 3, generally, the thicker the gate metal layer (particularly the Cu layer), the lower the sheet resistance of the gate metal layer can be made. However, if the gate metal layer becomes too thick, the substrate may warp. When the substrate is warped, the edge of the glass substrate floats from the stage of the transport device in the manufacturing process, which may cause transport failure and reduce mass productivity. As an example, when a glass substrate having a thickness of 0.7 mm is used, by suppressing the thickness of the gate metal layer to, for example, 560 nm or less (preferably 550 nm or less), it is possible to suppress deterioration in mass productivity due to warpage. On the other hand, for example, in a liquid crystal display panel having a resolution of 8K, the writing time Tg is shortened to about 2 μs, and the gate time constant is required to be suppressed to 2 μs or less, for example. Therefore, it is preferable to reduce the sheet resistance of the gate metal layer to, for example, 0.05Ω/□ or less (see FIG. 6). According to the present embodiment, as shown in FIG. 3, while suppressing the thickness of the gate metal layer (for example, 550 nm or less) and suppressing the warp of the substrate, the sheet resistance of the gate metal layer is reduced to 0.05Ω/□ or less. It is possible to

Further, from the results shown in FIG. 3, in the sample substrates A1 to C1 provided with the silicon oxynitride (SiOxNy) layer as the lowermost layer of the gate insulating layer, the sample substrate in which the lowermost layer of the gate insulating layer is the silicon nitride (SiNz) layer. It can be seen that the sheet resistance of the gate metal layer is further reduced and variations in the sheet resistance are suppressed as compared with A2 and C2. It is considered that this is because diffusion of impurities from the gate insulating layer to the gate metal layer is suppressed, and as a result, increase in resistance of the Cu layer due to impurity diffusion is suppressed. It is also confirmed from FIG. 3 that such an effect becomes more remarkable as the Cu layer becomes thinner.

<Evaluation of adhesion of Cu alloy layer of gate metal layer>
-Relationship between thickness of Cu alloy layer and adhesiveness The relationship between the thickness of Cu alloy film and the adhesiveness was examined by using the cross-cut method specified in JIS K5600.

Specifically, first, a Cu alloy film and a Cu film were deposited in this order on the surface of the glass substrate to form a laminated metal film. As the Cu alloy film, a Cu-Mg-Al alloy film (Mg: 2 at%, Al: 3 at%) was used. In addition, a plurality of evaluation samples were manufactured by setting the thickness of the Cu film to be constant (500 nm) and varying the thickness of the Cu alloy film.

Next, in each of the evaluation samples, a cut was made in a grid pattern on the laminated metal film and cut into a grid of 10×10 and 100 cells. Then, a tape test was performed. After the tape was peeled off, the peeled state of the laminated metal film was classified into 6 levels (peeling level) at 9 points in the plane. Table 2 shows the classification of the peeling levels Lv0 to Lv6 (according to the classification of 6 levels in the cross-cut method), and Table 3 shows the evaluation results of the adhesiveness.

From the results shown in Table 3, it was confirmed that if the thickness of the Cu alloy film is 30 nm or more, preferably 35 nm or more, sufficient adhesion with the substrate surface can be ensured.

The lower limit of the thickness of the Cu alloy film that can secure the adhesiveness may change depending on the material of the underlying surface. Here, although the laminated metal film is formed directly on the surface of the glass substrate, the Cu alloy film may be further thinned when the base insulating film is formed between the glass substrate and the laminated metal film.
-Relationship between Al Content in Cu Alloy Layer and Adhesiveness of Cu Alloy Layer Using the above cross-cut method, the relation between Al content in the Cu alloy film and adhesiveness was investigated.

Specifically, a Cu alloy film and a Cu film were formed on the surface of the glass substrate to obtain a laminated metal film. Here, a plurality of evaluation samples were prepared by changing the composition of the Cu alloy film (Cu-Mg-Al alloy film). The thickness of the Cu film was 500 nm, and the thickness of the Cu alloy film was 45 nm. For comparison, an evaluation sample in which a Cu alloy film was not formed and a Cu film (thickness: 500 nm) was directly formed on the substrate surface was also prepared.

Next, the same tape test as described above was performed to evaluate the adhesion (peel level) of the laminated metal film at 9 points on the surface of each evaluation substrate. The evaluation results are shown in Table 4.

From the results shown in Table 4, it is confirmed that the Cu alloy film made of the Cu alloy containing Al has higher adhesion to the substrate surface than the Cu film. Further, it can be seen that if the Al composition ratio is 2 at% or more, high adhesion can be secured.

<Etching amount of glass substrate and cross-sectional shape of gate metal layer>
The observation substrates of Examples and Comparative Examples were produced, and the cross-sectional shapes of the gate metal layer and the glass substrate were observed.

A Cu alloy film (thickness: 45 nm) and a Cu film (thickness: 500 nm) were directly formed on the surface of the glass substrate to obtain a laminated metal film. Here, a Cu—Mg—Al alloy film (Mg: 2 at %, Al: 3 at %) was formed as the Cu alloy film. Subsequently, a hydrogen peroxide type etching solution (not containing ammonium fluoride and acidic ammonium fluoride) was used to pattern the laminated metal film to obtain a gate metal layer. Then, a predetermined TFT process was performed to manufacture the observation substrate of the example.

For comparison, a Ti film (thickness: 25 nm) and a Cu film (thickness: 500 nm) were formed as the laminated metal film, and an etching solution containing ammonium fluoride was used for patterning the laminated metal film. An observation substrate of a comparative example was manufactured by using the same material as that of the example except for the use.

After that, the cross sections of the observation substrates of Examples and Comparative Examples were observed to examine the cross-sectional shape of the gate metal layer and the etching amount of the glass substrate.

FIG. 4A is a view showing a cross-sectional SEM image of the observation substrate of the example, and is an enlarged view of the vicinity of the interface between the substrate (glass substrate) 1 and the gate electrode 3 and the gate insulating layer 5. From this figure, it is confirmed that the surface of the glass substrate was hardly etched in the patterning process of the laminated metal film in the example.

FIG. 4B is a view showing a cross-sectional SEM image of the observation substrate of the comparative example, and is an enlarged view of the vicinity of the interface between the substrate (glass substrate) 1 and the gate electrode 3 and the gate insulating layer 5. From this figure, it is understood that in the comparative example, the surface portion of the glass substrate is etched along the pattern of the gate metal layer in the patterning process of the laminated metal film. The etching amount (thickness of the etched portion) dx of the glass substrate was measured and found to be 35 nm. When the glass substrate is etched, as described above, the strength of the glass substrate is reduced, which causes the reliability of the active matrix substrate to be reduced.

<Light transmittance>
A liquid crystal panel of an example having a gate metal layer having a Cu/Cu alloy laminated metal structure and a liquid crystal panel of a comparative example having a gate metal layer having a Cu/Ti laminated metal structure were produced, respectively, and their visible light transmittances were compared. did. In the example, the thickness of the Cu alloy layer was 45 nm and the thickness of the Cu layer was 500 nm. As the Cu alloy layer, a Cu-Mg-Al alloy layer (Mg: 2 at%, Al: 3 at%) was used. In the comparative example, the thickness of the Ti layer was 350 nm and the thickness of the Cu layer was 500 nm.

Subsequently, the transmittance of the liquid crystal panels of Examples and Comparative Examples for visible light was measured. The transmittance was measured at 8 points on the substrate.

Results are shown in FIG. The “transmittance ratio” shown on the vertical axis in FIG. 5 is the transmittance ratio when the average transmittance of the active matrix substrate of the comparative example is 0.500.

From this measurement result, it can be seen that the average transmittance ratio of the liquid crystal panel of the example is 0.507, which is about 1.4% higher than that of the comparative example. This is probably because when the Cu alloy layer is provided as the lower layer of the gate metal layer, the backlight light incident on the lower surface of the gate metal layer (the lower surface of the Cu alloy layer) is reflected and can be used (reused) for display. .. On the other hand, in the comparative example, since the Ti layer having a lower reflectance than the Cu alloy layer is used as the lower layer of the gate metal layer, the backlight light incident on the lower surface of the gate metal layer (the lower surface of the Ti layer) is The proportion of light reused is smaller than that in the embodiment. Therefore, it is considered that the transmittance is lower than that in the example.

(About TFT structure and oxide semiconductor)
The TFT structure is not limited to the structure illustrated in FIG. For example, the TFT 101 shown in FIG. 2 has a top contact structure in which the source and drain electrodes are in contact with the upper surface of the semiconductor layer, but may have a bottom contact structure in which the source and drain electrodes are in contact with the lower surface of the semiconductor layer. Good.

Although the TFT 101 shown in FIG. 2 has a channel etch structure, it may have an etch stop structure. In the “channel etch type TFT”, the etch stop layer is not formed on the channel region, and the lower surfaces of the end portions of the source and drain electrodes on the channel side are arranged in contact with the upper surface of the oxide semiconductor layer. .. The passivation film covering the TFT is in direct contact with the channel region of the semiconductor layer. On the other hand, in the "etch stop type TFT", an etch stop layer is formed on the channel region. The lower surfaces of the end portions of the source and drain electrodes on the channel side are located, for example, on the etch stop layer. In the etch stop type TFT, for example, after forming an etch stop layer covering a portion of the oxide semiconductor layer to be a channel region, a conductive film for source/drain electrodes is formed on the oxide semiconductor layer and the etch stop layer. , Source/drain separation is performed.

<Oxide semiconductor>
The oxide semiconductor included in the oxide semiconductor layer 7 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.

The oxide semiconductor layer 7 may have a laminated structure of two or more layers. When the oxide semiconductor layer 7 has a laminated structure, the oxide semiconductor layer 7 may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it may include a plurality of crystalline oxide semiconductor layers having different crystal structures. In addition, a plurality of amorphous oxide semiconductor layers may be included. When the oxide semiconductor layer 7 has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor contained in the upper layer is preferably larger than the energy gap of the oxide semiconductor contained in the lower layer. However, when the difference in energy gap between these layers is relatively small, the energy gap of the oxide semiconductor in the lower layer may be larger than the energy gap of the oxide semiconductor in the upper layer.

Materials, structures, film-forming methods, and configurations of oxide semiconductor layers having a laminated structure of the amorphous oxide semiconductor and the above crystalline oxide semiconductors are described in, for example, JP-A-2014-007399. .. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2014-007399 is incorporated herein.

The oxide semiconductor layer 7 may include, for example, at least one metal element selected from In, Ga, and Zn. In the present embodiment, the oxide semiconductor layer 7 includes, for example, an In—Ga—Zn—O-based semiconductor (eg, indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio of In, Ga, and Zn (composition ratio). Is not particularly limited, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2. Such an oxide semiconductor layer 7 can be formed from an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

The In-Ga-Zn-O-based semiconductor may be amorphous or crystalline. As the crystalline In-Ga-Zn-O-based semiconductor, a crystalline In-Ga-Zn-O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.

The crystal structure of a crystalline In-Ga-Zn-O-based semiconductor is disclosed in, for example, JP-A-2014-007399, JP-A-2012-134475, JP-A-2014-209727, and the like. ing. For reference, all the disclosures of JP2012-134475A and JP2014-209727A are incorporated herein. A TFT having an In-Ga-Zn-O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than 1/100 that of an a-Si TFT). It is preferably used as a driving TFT (for example, a TFT included in a driving circuit provided on the same substrate as a display area around a display area including a plurality of pixels) and a pixel TFT (a TFT provided in a pixel).

The oxide semiconductor layer 7 may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor. For example In-Sn-Zn-O based semiconductor (e.g. _IbO 3 -SnO ₂ -ZnO; InSnZnO) may contain. The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc). Alternatively, the oxide semiconductor layer 7 is an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O. -Based semiconductors, Cd-Ge-O-based semiconductors, Cd-Pb-O-based semiconductors, CdO (cadmium oxide), Mg-Zn-O-based semiconductors, In-Ga-Sn-O-based semiconductors, In-Ga-O-based semiconductors , Zr-In-Zn-O based semiconductor, Hf-In-Zn-O based semiconductor, Al-Ga-Zn-O based semiconductor, Ga-Zn-O based semiconductor, In-Ga-Zn-Sn-O based semiconductor. May be included.

The above embodiment is preferably applied to an active matrix substrate using an oxide semiconductor TFT. The active matrix substrate can be used in various display devices such as a liquid crystal display device, an organic EL display device, an inorganic EL display device, and electronic equipment including the display device. In the active matrix substrate, the oxide semiconductor TFT can be used not only as a switching element provided in each pixel but also as a circuit element of a peripheral circuit such as a driver (monolithic). In such a case, the oxide semiconductor TFT according to the present invention uses an oxide semiconductor layer having a high mobility (for example, 10 cm ² /Vs or more) as an active layer, and thus is suitably used as a circuit element.

The embodiments of the present invention can be widely applied to various semiconductor devices having an oxide semiconductor TFT. For example, a circuit substrate such as an active matrix substrate, a liquid crystal display device, an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, a display device such as a MEMS display device, an imaging device such as an image sensor device, an image input device, It is also applied to various electronic devices such as a fingerprint reading device and a semiconductor memory.

1: substrate 3: gate electrode 5: gate insulating layer 7: oxide semiconductor layer 8: source electrode 9: drain electrode 11: inorganic insulating layer 12: organic insulating layer 13: interlayer insulating layer 15: lower transparent electrode 17: dielectric Layer 19: Upper transparent electrode g1: Copper alloy layer g2: Copper layers a1 and a2: Oxygen-containing silicon layer n: Silicon nitride layer b: Intermediate layer m1:: Metal layer 101: TFT
1000: Active matrix substrate DR: Display region FR: Non-display region GL: Gate bus line SL: Source bus line PE: Pixel electrode Pix: Pixel region

Claims (15)

An active matrix substrate having a plurality of pixel regions,
Board,
A source metal layer including a plurality of source bus lines supported on the substrate; and a gate metal layer including a plurality of gate bus lines,
A thin film transistor and a pixel electrode arranged in each of the plurality of pixel regions,
The thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, an oxide semiconductor layer disposed on the gate insulating layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer. And the gate electrode is formed in the gate metal layer and electrically connected to a corresponding one of the plurality of gate bus lines, and the source electrode is formed of the plurality of source bus lines. Electrically connected to the corresponding one, the drain electrode is electrically connected to the pixel electrode,
The gate metal layer has a laminated structure including a copper alloy layer and a copper layer, the copper alloy layer is the bottom layer of the gate metal layer, the copper layer is disposed on the copper alloy layer Cage,
The copper alloy layer is made of a copper alloy containing Cu and at least one additional metal element, the at least one additional metal element contains Al, and the content of Al in the copper alloy is 2 at% or more and 8 at% or less. Oh it is,
The gate insulating layer includes a first oxygen-containing silicon layer that is in direct contact with the oxide semiconductor layer, a second oxygen-containing silicon layer that is in direct contact with an upper surface of the copper layer, the first oxygen-containing silicon layer, and the second oxygen-containing silicon layer. A silicon nitride layer located between the first oxygen-containing silicon layer and the silicon nitride layer, and a stacked structure including a silicon oxynitride intermediate layer located between the first oxygen-containing silicon layer and the silicon nitride layer. Have,
The active matrix substrate, wherein the first oxygen-containing silicon layer is a silicon oxide layer and the second oxygen-containing silicon layer is a silicon oxide layer or a silicon oxynitride layer . The active matrix substrate according to claim 1, wherein the at least one additional metal element further contains Mg. The active matrix substrate according to claim 1, wherein the content of Mg in the copper alloy is 1 at% or more and 3 at% or less. The active matrix substrate according to claim 1, wherein the content of Cu in the copper alloy is 80 at% or more. The active matrix substrate according to claim 1, wherein the at least one additional metal element does not contain P. The second oxygen-containing silicon layer is a silicon oxynitride layer represented by SiOxNy (2>x>0, 4/3>y>0), and x and y are 0.4≦x/(x+y). ) <1. The active matrix substrate according to any one of claims 1 to 5 , which satisfies <1. The active matrix substrate according to claim 6 , wherein the x and the y satisfy x≧y. The thickness of the copper alloy layer is smaller than the thickness of the copper layer, the active matrix substrate according to any one of claims 1 to 7. The thickness of the copper alloy layer is 30nm or more, the active matrix substrate according to any one of claims 1 to 8. The total thickness of the gate metal layer has a 550nm or less, the sheet resistance of the gate metal layer is 0.05? / □ or less, an active matrix substrate according to any one of claims 1 to 9. The substrate is a glass substrate, the copper alloy layer is in direct contact with the surface of the glass substrate, the active matrix substrate according to any one of claims 1 to 10. An active matrix substrate having a plurality of pixel regions,
Board,
A source metal layer including a plurality of source bus lines supported on the substrate; and a gate metal layer including a plurality of gate bus lines,
A thin film transistor and a pixel electrode arranged in each of the plurality of pixel regions,
The thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, an oxide semiconductor layer disposed on the gate insulating layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer. And the gate electrode is formed in the gate metal layer and electrically connected to a corresponding one of the plurality of gate bus lines, and the source electrode is formed of the plurality of source bus lines. Electrically connected to the corresponding one, the drain electrode is electrically connected to the pixel electrode,
The gate metal layer includes a copper layer that is in direct contact with the gate insulating layer,
The gate insulating layer, the oxide semiconductor layer and the first oxygen-containing silicon layer in direct contact with, the second oxygen-containing silicon layer in direct contact with the upper surface of the copper layer, the before and Symbol first oxygen-containing silicon layer first A laminated structure including a silicon nitride layer located between the second oxygen-containing silicon layer and an intermediate layer formed of silicon oxynitride located between the first oxygen-containing silicon layer and the silicon nitride layer. Have
The active matrix substrate, wherein the first oxygen-containing silicon layer is a silicon oxide layer, and the second oxygen-containing silicon layer is a silicon oxide layer or a silicon oxynitride layer. The second oxygen-containing silicon layer is a silicon oxynitride layer represented by SiOxNy (2>x>0, 4/3>y>0), and x and y are 0.4≦x/(x+y). ) The active matrix substrate according to claim 12 , which satisfies <1. The active matrix substrate according to claim 13 , wherein the x and the y satisfy x≧y. Wherein the oxide semiconductor layer, including In, Ga and Zn, the active matrix substrate according to any one of claims 1 to 14.

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