JP4755455B2 - Control circuit for controlling on / off of power transistor, switching regulator using the same, and electronic device - Google Patents

Description

  The present invention relates to a driving technique for a power transistor used in a switching regulator or the like, and more particularly to a technique for reducing the power consumption.

  Various electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and notebook personal computers in recent years are equipped with microprocessors that perform digital signal processing. The power supply voltage required to drive such a microprocessor has been reduced with the miniaturization of the semiconductor manufacturing process, and some of them operate at a low voltage of 1.5 V or less.

  On the other hand, a battery such as a lithium ion battery is mounted on such an electronic device as a power source. The battery voltage output from the lithium ion battery is about 3V to 4V. If the battery voltage is supplied to the microprocessor as it is, wasteful power consumption occurs. Therefore, it is common to step down the battery voltage using a step-down switching regulator or the like, to make it constant voltage, and to supply it to the microprocessor. For example, Patent Documents 1 to 3 disclose techniques related to a step-down switching regulator.

JP 2004-32875 A JP 2002-252971 A JP 2003-319643 A

  In electronic devices that require a longer battery life, increasing the efficiency of switching regulators is a very important technical issue. One factor limiting the efficiency of a switching regulator is the on-resistance of a power transistor used as a switching element. In order to increase the efficiency of the switching regulator, it is desirable to design the on-resistance that acts as a loss as small as possible, that is, to increase the transistor size.

  However, if the transistor size is designed to be large with emphasis on the efficiency under heavy load in which a certain amount of current flows through the power transistor, the gate capacitance of the power transistor increases. Although depending on the semiconductor manufacturing process, the gate capacitance of the power transistor is as large as several tens of pF to several hundreds of pF. As a result, there arises a problem that the gate drive current required for changing the gate voltage to turn on and off the power transistor increases. In particular, the efficiency is limited by the gate drive current at a light load with a small current flowing through the power transistor.

  The present invention has been made in view of such problems, and one of its purposes is to reduce the gate drive current of a power transistor that functions as a switching element of a switching regulator.

  One embodiment of the present invention relates to a control circuit that controls the gate voltage of a power transistor that repeatedly turns on and off in a time-sharing manner. The control circuit includes a charge transfer switch and a charge storage capacitor provided in series between the gate of the power transistor and the fixed voltage terminal, and a second voltage lower than the first voltage or the first voltage at the gate of the power transistor. And a driver circuit that controls on / off of the charge transfer switch in synchronization with the power transistor.

  According to this aspect, the charge stored in the gate of the power transistor is transferred to and stored in the charge storage capacitor, and the stored charge is transferred again to the gate when the gate voltage is transitioned next time. As a result, the gate drive current can be reduced and the power consumption can be reduced.

  The capacitance of the charge storage capacitor may be set larger than the gate capacitance of the power transistor. As the capacitance value of the charge storage capacitor is increased, the gate drive current can be reduced.

  When the gate voltage of the power transistor is increased from the second voltage to the first voltage, the driver circuit turns on the charge transfer switch to transfer the charge from the charge storage capacitor to the gate of the power transistor, and then for the charge transfer While turning off the switch, the first voltage may be applied to the gate of the power transistor.

  When the driver circuit lowers the gate voltage of the power transistor from the first voltage to the second voltage, the driver circuit turns on the charge transfer switch to transfer the charge from the power transistor gate to the charge storage capacitor, and then While the transfer switch is turned off, the second voltage may be applied to the gate of the power transistor.

The charge transfer switch, the charge storage capacitor, and the driver circuit may be integrated on a single semiconductor substrate. Further, the power transistors to be controlled may be further integrated.
Note that “integrated integration” includes the case where all the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated, and is used for adjusting circuit constants. Part of the resistors, capacitors, and the like may be provided outside the semiconductor substrate.

  Another aspect of the present invention is a step-down switching regulator. This switching regulator has a switching transistor having one end applied with an input voltage, a cathode connected to the other end of the switching transistor, an anode grounded, and one end at the connection point between the switching transistor and the rectifying diode. The output inductor connected, the output capacitor provided between the other end of the output inductor and the ground, and the above-described control circuit that controls on / off of the switching transistor in a time-sharing manner are provided.

  The switching regulator may include a synchronous rectification transistor instead of the rectification diode. The control circuit may control ON / OFF of the switching transistor and the synchronous rectification transistor, and may provide a charge storage capacitor and a charge transfer switch between at least one gate of the switching transistor or the synchronous rectification transistor and the ground.

  According to this aspect, the gate drive current of the step-down switching transistor can be reduced, and the efficiency of the switching regulator can be improved.

  Yet another embodiment of the present invention is a step-up switching regulator. This switching regulator includes an inductor having an input voltage applied to one end, a switching transistor provided between the other end of the inductor and the ground, a rectifying diode having an anode connected to the connection point of the inductor and the switching transistor, and rectification An output capacitor provided between the cathode of the operating diode and the ground, and the above-described control circuit that controls on / off of the switching transistor in a time-sharing manner.

  The switching regulator may include a synchronous rectifying transistor instead of the rectifying diode. The control circuit may control on / off of the switching transistor and the synchronous rectification transistor, and may provide a charge transfer switch and a charge storage capacitor between at least one gate of the switching transistor or the synchronous rectification transistor and the ground.

  According to this aspect, the gate drive current of the step-up switching transistor can be reduced, and the efficiency of the switching regulator can be improved.

  Yet another embodiment of the present invention is an electronic device. This electronic device includes a battery and the above-described switching regulator that supplies a load by stepping down or boosting a battery voltage output from the battery.

  According to this aspect, it is possible to improve the efficiency of the switching regulator by reducing the gate drive current of the power transistor, thereby extending the life of the battery.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the control circuit for controlling the gate voltage of the power transistor according to the present invention, the gate drive current can be reduced.

(First embodiment)
The first embodiment relates to a control circuit that controls on / off of a power transistor used as a switching element in a time division manner in a switching regulator, an H bridge circuit of a motor driver, and a charge pump circuit.

  FIG. 1 is a circuit diagram showing a configuration of a control circuit 100 according to the first embodiment. In the present embodiment, a case where the power transistor M1 to be driven is a P-channel MOSFET (Metal Oxide Field Effect Transistor) will be described. The power transistor to be driven may be an N-channel MOSFEET. In this case, the high level and the low level of the gate voltage may be reversed.

  The power supply voltage Vdd is applied to the source of the power transistor M1, and the control circuit 100 controls on / off of the power transistor M1 by switching the gate voltage of the power transistor M1. A load (not shown) such as an N-channel MOSFET or a resistor is connected to the drain of the power transistor M1.

The control circuit 100 includes a charge transfer switch SW1, a charge storage capacitor C1, and a driver circuit 10. In the following description, reference numerals assigned to signals and capacitors are used to represent respective voltage values and capacitance values as necessary.
The charge transfer switch SW1 and the charge storage capacitor C1 are provided in series between the gate of the power transistor M1 and the ground which is a fixed voltage terminal. The capacitance of the charge storage capacitor C1 is set larger than the gate capacitance Cg1 of the power transistor M1. The capacitance of the charge storage capacitor C1 is desirably designed to be as large as possible so that it is at least 1.5 times or more, preferably 3 to 10 times or more the gate capacitance Cg1 of the power transistor M1.

  The driver circuit 10 is supplied with a pulse signal SIG1 that instructs on / off of the power transistor M1. The driver circuit 10 turns on the power transistor M1 when the pulse signal SIG1 is at a low level, and turns off the power transistor M1 when the pulse signal SIG1 is at a high level. The driver circuit 10 outputs a first voltage V1 or a second voltage V2 lower than the first voltage V1 from its output terminal 12, and applies it to the gate of the power transistor M1. In the present embodiment, it is assumed that first voltage V1 and second voltage V2 are power supply voltage Vdd and ground potential 0V, respectively. The power transistor M1 is turned off when the first voltage V1 = Vdd is applied to the gate by the driver circuit 10, and is turned on when the second voltage V2 = 0V is applied to the gate.

  Further, the driver circuit 10 controls on / off of the charge transfer switch SW1 in synchronization with the control of the gate voltage Vg1 of the power transistor M1. A signal output from the driver circuit 10 to the charge transfer switch SW1 is referred to as a switch control signal SIG2. The charge transfer switch SW1 is turned on when the switch control signal SIG2 is at a high level and turned off when the switch control signal SIG2 is at a low level. The output terminal 12 of the driver circuit 10 is configured to have a high impedance during the period when the charge transfer switch SW1 is turned on.

  When the driver circuit 10 increases the gate voltage Vg1 of the power transistor M1 from the second voltage V2 = 0V to the first voltage V1 = Vdd, that is, when the power transistor M1 is switched from on to off, the driver circuit 10 switches the charge transfer switch SW1. The charge storage capacitor C1 is turned on to transfer charges to the gate of the power transistor M1, and then the charge transfer switch SW1 is turned off, and the first voltage V1 = Vdd is applied to the gate of the power transistor M1.

  Conversely, the driver circuit 10 switches the charge transfer switch when the gate voltage Vg1 of the power transistor M1 is lowered from the first voltage V1 = Vdd to the second voltage V2 = 0V, that is, when the power transistor M1 is switched from OFF to ON. SW1 is turned on to transfer charges from the gate of the power transistor M1 to the charge storage capacitor C1, and then the charge transfer switch SW1 is turned off and the second voltage V2 = 0 V is applied to the gate of the power transistor M1. .

  2A to 2D are timing charts showing operation states of the control circuit 100 of FIG. 2A shows the pulse signal SIG1 input to the driver circuit 10, FIG. 2B shows the switch control signal SIG2, FIG. 2C shows the gate voltage Vg1 of the power transistor M1, and FIG. (D) shows the voltage Vc1 appearing in the charge storage capacitor C1.

  First, an operation when the driver circuit 10 raises the gate voltage Vg1 of the power transistor M1 from the second voltage V2 = 0V to the first voltage V1 = Vdd will be described. In the state φ0 before time T1, the gate voltage Vg1 of the power transistor M1 is fixed to the second voltage V2.

  At time T1, the pulse signal SIG1 becomes high level, and the power transistor M1 is instructed to be turned off. The driver circuit 10 sets the switch control signal SIG2 to high level for a predetermined time Δt to turn on the charge transfer switch SW1, and sets the output terminal 12 to high impedance. When the charge transfer switch SW1 is turned on, the charge stored in the charge storage capacitor C1 is transferred to the gate of the power transistor M1. When the charge transfer switch SW1 is turned on, the gate voltage Vg1 of the power transistor M1 increases, the voltage Vc1 appearing at the charge storage capacitor C1 decreases, and the two voltages become equal.

  At time T2, the driver circuit 10 sets the switch control signal SIG2 to a low level to turn off the charge transfer switch SW1, and applies the first voltage V1 = Vdd to the gate of the power transistor M1. As a result, the gate voltage Vg1 of the power transistor M1 immediately rises to the power supply voltage Vdd. In a period φ2 until the pulse signal SIG1 becomes low level at time T3, the first voltage V1 = Vdd is continuously applied to the gate of the power transistor M1, and the power transistor M1 is turned off. During this time, the charge transfer switch SW1 is turned off, so that the voltage Vc1 appearing in the charge storage capacitor C1 is maintained at a constant value.

  Next, an operation when the driver circuit 10 lowers the gate voltage Vg1 of the power transistor M1 from the first voltage V1 = Vdd to the second voltage V2 = 0V will be described.

  At time T3, the pulse signal SIG1 becomes a low level, and the power transistor M1 is turned on. In a period φ3 from time T3 to time T4 after a predetermined time Δt elapses, the driver circuit 10 sets the switch control signal SIG2 to high level to turn on the charge transfer switch SW1 and set the output terminal 12 to high impedance. When the charge transfer switch SW1 is turned on, the charge stored in the gate of the power transistor M1 is transferred to the charge storage capacitor C1, the gate voltage Vg1 of the power transistor M1 is lowered, and the voltage Vc1 appearing in the charge storage capacitor C1. Rises and the two voltages are equal.

  At time T4, the driver circuit 10 sets the switch control signal SIG2 to the low level to turn off the charge transfer switch SW1, and applies the second voltage V2 = 0 V to the gate of the power transistor M1. As a result, the gate voltage Vg1 of the power transistor M1 immediately drops to the ground potential 0V. Thereafter, in a period φ4 until the pulse signal SIG1 becomes high level again at time T5, the second voltage V2 = 0V is continuously applied to the gate of the power transistor M1, and the power transistor M1 is turned on. During this time, the charge transfer switch SW1 is turned off, so that the voltage Vc1 appearing in the charge storage capacitor C1 is maintained at a constant value.

Here, attention is focused on the gate voltage Vg1 of the power transistor M1 and the voltage Vc1 appearing in the charge storage capacitor C1. In a period φ2 in which the first voltage V1 = Vdd is applied to the gate of the power transistor M1, the voltage appearing in the charge storage capacitor C1 is VcL, and a period φ4 in which the second voltage V2 = 0V is applied to the gate of the power transistor M1. , VcH is a voltage appearing in the charge storage capacitor C1. In the period φ1 from time T1 to T2, the change amount ΔQg1 of the charge Qg1 stored in the gate of the power transistor M1 and the change amount ΔQc1 of the charge Qc1 stored in the charge storage capacitor C1 are obtained from the law of charge storage. Will be equal. Therefore, the relationship of the following formula (1) is established between each voltage and the capacitance value.
VcL × Cg1 = (VcH−VcL) × C1 (1)

In the period φ3 from time T3 to T4, the change amount ΔQg1 of the charge Qg1 stored in the gate of the power transistor M1 and the change amount ΔQc1 of the charge Qc1 stored in the charge storage capacitor C1 are also equal. Therefore, the relationship of the following formula (2) is established between each voltage and the capacitance value.
(Vdd−VcH) × Cg1 = (VcH−VcL) × C1 (2)

From the expressions (1) and (2), the following expressions (3) and (4) are obtained as the voltage VcL and the voltage VcH.
VcL = C1 / (Cg1 + 2 × C1) × Vdd (3)
VcH = (Cg1 + C1) (Cg1 + 2 × C1) × Vdd (4)

Now, when the capacitance value of the charge storage capacitor C1 is designed to be sufficiently larger than the gate capacitance of the power transistor M1, that is, when C1 >> Cg1 holds, the relationship of the following formula (5) holds.
VcL = VcH = Vdd / 2 (5)

In the conventional control circuit that does not have the charge storage capacitor C1 and the charge transfer switch SW1, it is necessary to change the gate voltage Vg1 from 0 V to Vdd when the power transistor M1 is switched from OFF to ON. The amount of charge required at this time is Vdd × Cg1, and when the frequency of the switching operation is f, a current of Idrv = Vdd × Cg1 × f is required as the gate drive current Idrv.
On the other hand, as described above, when the capacitance value of the charge storage capacitor C1 is designed to be sufficiently large, the driver circuit 10 changes the gate voltage Vg1 from Vdd / 2 to Vdd when the power transistor M1 is switched from OFF to ON. It can be changed. That is, the gate drive current Idrv can be reduced by 50% compared to the conventional case.

  FIG. 3 is a circuit diagram showing a configuration example of the driver circuit 10 of FIG. In the subsequent drawings, the same or equivalent components as those already described are denoted by the same reference numerals, and repeated description will be omitted as appropriate. In FIG. 3, the charge transfer switch SW1 of FIG. 1 is configured as an N-channel MOSFET.

  The driver circuit 10 includes a first inverter INV1 to a third inverter INV3, a high side transistor 14, a low side transistor 16, and an AND gate 18.

  The high-side transistor 14 is a P-channel MOSFET, and is provided between the output terminal 12 and the first terminal 20 to which the first voltage V1 = Vdd is supplied. When the high side transistor 14 is turned on, the first voltage V1 appears at the output terminal 12, and the first voltage V1 is applied to the gate of the power transistor M1. The low-side transistor 16 is an N-channel MOSFET, and is provided between the output terminal 12 and the second terminal 22 to which the second voltage V2 = 0V is supplied. When the low-side transistor 16 is turned on, the second voltage V2 appears at the output terminal 12, and the second voltage V2 is applied to the gate of the power transistor M1. On / off of the high-side transistor 14 and the low-side transistor 16 is controlled by output signals SIG3 and SIG4 of the first inverter INV1 and the second inverter INV2, respectively. When both the high-side transistor 14 and the low-side transistor 16 are off, the output terminal 12 has a high impedance.

  The pulse signal SIG1 input to the driver circuit 10 is input to the first inverter INV1 and the second inverter INV2. The first inverter INV1 delays the rising edge (hereinafter also referred to as a positive edge) of the pulse signal SIG1 by a predetermined time Δt. The second inverter INV2 delays the falling edge (hereinafter also referred to as a negative edge) of the pulse signal SIG1 by a predetermined time Δt. The inverter that delays the positive edge or the negative edge can be realized by providing a resistance element on the current path of a general inverter in which a P-channel MOSFET and an N-channel MOSFET are connected, and configuring a CR time constant circuit in combination with a capacitance component. .

  The output signal SIG3 of the first inverter INV1 is input to the gate of the high side transistor 14, and the output signal SIG4 of the second inverter INV2 is input to the gate of the low side transistor 16. The output signals SIG3 and SIG4 control ON / OFF of the high side transistor 14 and the low side transistor 16, respectively.

The first inverter INV1, the second inverter INV2, the third inverter INV3, and the AND gate 18 function as a switch control signal generation circuit that generates a switch control signal SIG2 for controlling on / off of the charge transfer switch SW1.
The third inverter INV3 inverts the output signal SIG4 of the second inverter INV2. The AND gate 18 outputs a logical product of the output signal SIG3 of the first inverter INV1 and the output signal SIG5 of the third inverter INV3 as the switch control signal SIG2.

  4A to 4F are timing charts showing operation states of the driver circuit 10 of FIG. 4A shows the pulse signal SIG1, FIG. 4B shows the output signal SIG3 of the first inverter INV1, FIG. 4C shows the output signal SIG4 of the second inverter INV2, and FIG. ) Represents the output signal SIG5 of the third inverter INV3, FIG. 4 (e) represents the switch control signal SIG2, and FIG. 4 (f) represents the voltage applied by the driver circuit 10 to the gate of the power transistor M1.

  When the pulse signal SIG1 changes from the low level to the high level at time T1, the output signal SIG3 of the first inverter INV1 transitions from the high level to the low level at time T2 after a predetermined time Δt has elapsed. Further, the output signal SIG4 of the second inverter INV2 transitions from the high level to the low level without delay at time T1. The output signal SIG5 obtained by inverting the output signal SIG4 by the third inverter INV3 transitions from the low level to the high level at time T1.

  During the period from time T1 to time T2, the output signal SIG3 of the first inverter INV1 is at a high level, so the high side transistor 14 is turned off. Further, since the output signal SIG4 of the second inverter INV2 is at a low level, the low-side transistor 16 is also turned off. As a result, the output terminal 12 becomes high impedance. During this period, the switch control signal SIG2 that is an output signal of the AND gate 18 is at a high level, so that the charge transfer switch SW1 is turned on and charge transfer is performed.

  When the output signal SIG3 of the first inverter INV1 becomes low level at time T2, the high side transistor 14 is turned on, and the first voltage V1 = Vdd appears at the output terminal 12. At time T3, the pulse signal SIG1 becomes low level, and at the same time, the output signal SIG3 of the first inverter INV1 changes from low level to high level. Further, the output signal SIG4 of the second inverter INV2 transitions from the low level to the high level at time T4 after a predetermined time Δt has elapsed from time T3. During a period from time T3 to time T4, the switch control signal SIG2 becomes high level again, the charge transfer switch SW1 is turned on, and charge transfer is performed. During this time, both the high-side transistor 14 and the low-side transistor 16 are turned off, so that the output terminal 12 has a high impedance. When the output signal SIG4 of the second inverter INV2 becomes high level at time T4, the low-side transistor 16 is turned on, and the second voltage V2 = 0V appears at the output terminal 12.

  As described above, the driver circuit 10 having the configuration shown in FIG. 3 can suitably control the gate voltage of the power transistor M1 and the on / off control of the charge transfer switch SW1.

(Second Embodiment)
In the second embodiment, a step-down switching regulator will be described as an application example of the control circuit 100 described in the first embodiment to a specific circuit.
FIG. 5 is a circuit diagram showing the overall configuration of the switching regulator control circuit 110 and the step-down switching regulator 200 using the control circuit 100 of FIG. The synchronous rectification step-down switching regulator 200 includes a switching regulator control circuit 110, an output inductor L1, and an output capacitor C2. The switching regulator control circuit 110 is an LSI chip integrated on a single semiconductor substrate, and the switching transistor M1 functioning as a switching element and the synchronous rectification transistor M2 are built in the switching regulator control circuit 110.

  One end of the output capacitor C2 is grounded, and the other end is connected to one end of the output inductor L1. The other end of the output inductor L1 is connected to the switching regulator control circuit 110. In the step-down switching regulator 200, the switching regulator control circuit 110 controls the current flowing through the output inductor L1, performs energy conversion, and steps down the input voltage Vin. The stepped-down voltage is smoothed by the output capacitor C2, and is supplied as an output voltage Vout to a load (not shown) connected to the output terminal 204.

  The switching regulator control circuit 110 includes an input terminal 102, a switching terminal 104, and a voltage feedback terminal 106 as input / output terminals. A battery is connected to the input terminal 102, and the battery voltage Vbat is input as the input voltage Vin. The switching terminal 104 is connected to the output inductor L1 and outputs the switching voltage Vsw generated inside the switching regulator control circuit 110. The voltage feedback terminal 106 is a terminal to which the output voltage Vout applied to the load is fed back.

  The switching regulator control circuit 110 includes a pulse signal generation circuit 30, a control circuit 100, a switching transistor M1, and a synchronous rectification transistor M2. The output voltage Vout of the step-down switching regulator 200 is input to the pulse signal generation circuit 30 via the voltage feedback terminal 106. The pulse signal generation circuit 30 outputs a pulse signal SIG1 whose duty ratio changes so that the output voltage Vout approaches the desired target voltage Vset. The configuration of the pulse signal generation circuit 30 can use a generally known technique, and thus description thereof is omitted. As a generation method of the pulse signal SIG1 by the pulse signal generation circuit 30, the above-described voltage mode control for monitoring the output voltage Vout, current mode control for monitoring the current flowing through the output inductor L1, and the like are known. Therefore, a method satisfying the design specifications may be appropriately selected and configured.

  The switching transistor M1 and the synchronous rectification transistor M2 are connected in series between the input terminal 102 to which the input voltage Vin is applied and the ground terminal, and the switching voltage Vsw is used as a switching voltage Vsw. The voltage is applied to one end of the output inductor L1 connected to the outside of the control circuit 110. The switching transistor M1 is turned on when the first gate voltage Vg1 is at a low level and turned off when the first gate voltage Vg1 is at a high level. The synchronous rectification transistor M2 is turned on when the second gate voltage Vg2 is at a high level and turned off when the second gate voltage Vg2 is at a low level.

  The control circuit 100 in FIG. 1 can be suitably used to drive the power transistor M1 and the synchronous rectification transistor M2 shown in FIG. The control circuit 100 includes a driver circuit 10, a first charge transfer switch SW1a, a second charge transfer switch SW1b, a first charge storage capacitor C1a, and a second charge storage capacitor C1b.

  The driver circuit 10 complementarily turns on and off the switching transistor M1 and the synchronous rectification transistor M2 based on the pulse signal SIG1. The driver circuit 10 includes a first driver unit 10a for turning on / off the switching transistor M1 and a second driver unit 10b for turning on / off the synchronous rectification transistor M2. A first charge transfer switch SW1a and a first charge storage capacitor C1a are connected in series between the gate of the switching transistor M1 and the ground. The first driver unit 10a controls on / off of the first charge transfer switch SW1a. Similarly, the second driver unit 10b controls on / off of the second charge transfer switch SW1b. The first driver unit 10a and the second driver unit 10b may have the same configuration as that in FIG.

  According to the step-down switching regulator 200 configured as described above, the gate drive current for controlling on / off of the switching transistor M1 and the synchronous rectification transistor M2 can be reduced, and the efficiency can be improved.

  In the switching regulator control circuit 110 of FIG. 5, the first charge storage capacitor C1a and the second charge storage capacitor C1b are provided at the gates of both the switching transistor M1 and the synchronous rectification transistor M2. You may provide only. For example, when the switching transistor M1 is configured by a P-channel MOSFET and the synchronous rectification transistor M2 is configured by an N-channel MOSFET, the switching transistor M1 has a larger area. In such a case, the charge storage capacitor C1 may be provided only at the gate of the switching transistor M1. Further, the synchronous rectification transistor M2 may be replaced with a rectification diode.

  Furthermore, the application of the control circuit of FIG. 1 is not limited to a step-down switching regulator, but may be applied to a step-up switching regulator. FIG. 6 is a circuit diagram showing a configuration of a step-up switching regulator 210 using the control circuit 100 of FIG. The step-up switching regulator 210 includes a switching regulator control circuit 120, an inductor L2, and an output capacitor C3. The input voltage Vin is applied to one end of the inductor L2. The switching transistor M3 is provided between the other end of the inductor L2 and the ground. The synchronous rectification transistor M4 is connected to a connection point between the inductor L2 and the switching transistor M3. An output capacitor C3 is connected between the other end of the synchronous rectification transistor M4 and the ground. The switching regulator control circuit 120 controls on / off of the switching transistor M3 and the synchronous rectification transistor M4 in a time-sharing manner.

  According to the step-up switching regulator 210 configured as described above, the gate drive currents of the switching transistor M3 and the synchronous rectification transistor M4 can be suitably reduced, and high efficiency can be achieved. The synchronous rectification transistor M4 in FIG. 6 may be replaced with a rectification diode.

  FIG. 7 is a block diagram illustrating a configuration of an electronic device 300 including the switching regulator of FIG. 5 or 6. The electronic device 300 is a battery-driven small information terminal such as a mobile phone terminal, a CD player, or a PDA. Hereinafter, description will be given assuming that electronic device 300 is a mobile phone terminal. The electronic device 300 includes a battery 310, a power supply device 320, an analog circuit 330, a digital circuit 340, a microprocessor 350, and an LED 360. The battery 310 is a lithium ion battery, for example, and outputs about 3 to 4 V as the battery voltage Vbat. The analog circuit 330 includes high-frequency circuits such as a power amplifier, an antenna switch, an LNA (Low Noise Amplifier), a mixer, and a PLL (Phase Locked Loop), and includes a circuit block that stably operates at a power supply voltage Vcc = 3.4V. . The digital circuit 340 includes various DSPs (Digital Signal Processors) and the like, and includes a circuit block that stably operates at a power supply voltage Vdd = 3.4V. The microprocessor 350 is a block that comprehensively controls the entire electronic device 300, and operates at a power supply voltage of 1.5V. The LED 360 includes RGB three-color LEDs (Light Emitting Diodes) and is used as a liquid crystal backlight or illumination, and a driving voltage of 4 V or more is required for driving.

  The power supply device 320 is a multi-channel switching power supply, and includes a plurality of switching regulators and linear regulators that step down or step up the battery voltage Vbat as necessary for each channel, and an analog circuit 330, a digital circuit 340, and a microprocessor 350. , Supply an appropriate power supply voltage to the LED 360.

  The step-down switching regulator 200 of FIG. 5 and the step-up switching regulator 210 of FIG. 6 according to this embodiment can be used for each channel of the power supply device 320 of FIG. For example, the step-down switching regulator 200 can be applied to the microprocessor 350 that operates at 1.5 V, and the step-up switching regulator 210 can be applied to the LED 360 that requires a high voltage. By driving the power transistor of the switching regulator used for each channel of the power supply device 320 by using the control circuit 100 described above, the current consumption of the circuit can be reduced and the life of the battery can be extended.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, the switching regulator is described as an example of an application for turning on and off the power transistor in a time division manner. However, the present invention is not limited to this. The control circuit 100 can be suitably used for other applications. For example, the control circuit 100 can be suitably used for driving a MOSFET used as a switching element of a charge pump circuit or driving an H bridge circuit of a motor driver circuit. it can.

  In the embodiment, the case where the control circuit 100 is integrated in one LSI has been described. However, the present invention is not limited to this, and some components are provided as discrete elements or chip components outside the LSI. Or you may comprise by several LSI.

  The setting of the logical values of the high level and the low level described in the embodiment is an example, and can be freely changed by appropriately inverting with an inverter or the like.

It is a circuit diagram which shows the structure of the control circuit which concerns on 1st Embodiment. 2A to 2D are timing charts showing operation states of the control circuit of FIG. FIG. 2 is a circuit diagram illustrating a configuration example of a driver circuit in FIG. 1. 4A to 4F are timing charts showing operation states of the driver circuit of FIG. It is a circuit diagram which shows the structure of the whole pressure | voltage fall type switching regulator which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the whole step-up type switching regulator which concerns on 2nd Embodiment. It is a block diagram which shows the structure of the electronic device containing the switching regulator of FIG. 5 or FIG.

Explanation of symbols

  C1 charge storage capacitor, SW1 charge transfer switch, 10 driver circuit, M1 power transistor, 100 control circuit, SIG1 pulse signal, SIG2 switch control signal.

Claims (11)

A control circuit that controls the gate voltage of a power transistor that repeatedly turns on and off in a time-sharing manner,
A charge transfer switch and a charge storage capacitor provided in series between the gate and the fixed voltage terminal of the power transistor;
A driver circuit that applies a first voltage or a second voltage lower than the first voltage to the gate of the power transistor to switch the power transistor on and off, and controls on / off of the charge transfer switch in synchronization therewith; ,
Equipped with a,
When the driver circuit increases the gate voltage of the power transistor from the second voltage to the first voltage,
The charge transfer switch is turned on to transfer charge from the charge storage capacitor to the gate of the power transistor, and then the charge transfer switch is turned off, and the first voltage is applied to the gate of the power transistor. A control circuit which is applied .   2. The control circuit according to claim 1, wherein a capacity of the charge storage capacitor is set larger than a gate capacity of the power transistor. When the driver circuit lowers the gate voltage of the power transistor from the first voltage to the second voltage,
The charge transfer switch is turned on to transfer charge from the gate of the power transistor to the charge storage capacitor, and then the charge transfer switch is turned off, and the second voltage is applied to the gate of the power transistor. The control circuit according to claim 1, wherein the control circuit is applied.   The driver circuit is
  A first inverter that inverts a pulse signal that instructs on / off of the power transistor;
  A second inverter for inverting the pulse signal;
  A third inverter for inverting the output of the second inverter;
  An AND gate that outputs a signal corresponding to a logical product of the output of the first inverter and the output of the third inverter to the charge transfer switch;
  A high side transistor in which the first voltage is applied to the source and the output of the first inverter is applied to the gate;
  A low-side transistor whose drain is connected to the drain of the high-side transistor, the second voltage is applied to the source, and the output of the second inverter is applied to the gate;
  The control circuit according to claim 1, further comprising: The charge and transfer switch, said charge storage capacitor, a control circuit according to any one of claims 1 4, characterized in that integrally integrated with the driver circuit, the on one semiconductor substrate. 6. The control circuit according to claim 5 , wherein the power transistors to be controlled are further integrated. A switching transistor with an input voltage applied to one end;
A rectifying diode having a cathode connected to the other end of the switching transistor and an anode grounded;
An output inductor having one end connected to a connection point between the switching transistor and the rectifying diode;
An output capacitor provided between the other end of the output inductor and ground;
The control circuit according to any one of claims 1 to 6, which controls on / off of the switching transistor in a time-sharing manner,
A switching regulator comprising: A synchronous rectification transistor instead of the rectification diode;
The control circuit controls on / off of the switching transistor and the synchronous rectification transistor, and the charge transfer switch and the charge storage capacitor are grounded with at least one gate of the switching transistor or the synchronous rectification transistor. The switching regulator according to claim 7, wherein the switching regulator is provided in between. An inductor with an input voltage applied to one end;
A switching transistor provided between the other end of the inductor and the ground;
A rectifying diode having an anode connected to a connection point of the inductor and the switching transistor;
An output capacitor provided between the cathode of the rectifying diode and ground;
The control circuit according to any one of claims 1 to 6, which controls on / off of the switching transistor in a time-sharing manner,
A switching regulator comprising: A synchronous rectification transistor instead of the rectification diode;
The control circuit controls on / off of the switching transistor and the synchronous rectification transistor, and the charge transfer switch and the charge storage capacitor are grounded with at least one gate of the switching transistor or the synchronous rectification transistor. The switching regulator according to claim 9, wherein the switching regulator is provided in between. Battery,
The switching regulator according to any one of claims 7 to 10, wherein the battery voltage output from the battery is stepped down or boosted and supplied to a load;
An electronic device comprising:

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