JP4654509B2 - Power supply voltage conversion circuit, control method therefor, display device and portable terminal - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power supply voltage conversion circuit, a control method thereof, a display device, and a portable terminal, and more particularly to a power supply voltage conversion circuit using a charge pump, a control method thereof, a display device equipped with the power supply voltage conversion circuit, and a display thereof The present invention relates to a mobile terminal including the device.
[0002]
[Prior art]
In recent years, mobile terminals such as mobile phones and PDAs (Personal Digital Assistants) have become widespread. One of the factors of the rapid spread of these portable terminals is a liquid crystal display device mounted as an output display unit. This is because the liquid crystal display device has a characteristic that does not require power for driving in principle and is a display device with low power consumption.
[0003]
In a portable terminal, a battery having a single power supply voltage is used as a power source. On the other hand, in a liquid crystal display device, in a horizontal driving circuit that drives pixels arranged in a matrix, different DC voltages are used in the logic unit and the analog unit, and in a vertical driving circuit that writes information to the pixels, a horizontal driving circuit A DC voltage having a larger absolute value than the side is used. Therefore, in a liquid crystal display device mounted on a portable terminal, a power supply voltage conversion circuit that converts a single DC voltage into a plurality of types of DC voltages having different voltage values, a so-called DC-DC converter (hereinafter referred to as a DD converter). Is used.
[0004]
Conventionally, as a DD converter in a liquid crystal display device, one using an inductor L has been generally used, but a charge pump type is often used in accordance with the recent reduction in power consumption and miniaturization of portable terminals. It has come to be. Although the charge pump type DD converter has a relatively small current capacity, there is an advantage that it is possible to contribute to downsizing of the portable terminal because it is not necessary to use the inductor L as an external component.
[0005]
FIG. 11 shows a configuration of a charge pump type DD converter according to Conventional Example 1. In the figure, (A) shows a negative voltage generation type, and (B) shows a boost type, and the basic configuration is the same.
[0006]
In FIG. 11A, a Pch MOS transistor Qp101 and an Nch MOS transistor Qn101 are connected in series between a power supply that provides a single DC voltage VCC and the ground (GND), and each gate is connected in common. A CMOS inverter 101 is configured. A switching pulse having a predetermined frequency is applied from the pulse generation source 102 to the common gate connection point of the CMOS inverter 101.
[0007]
One end of a capacitor C101 is connected to the common drain connection point (node A) of the CMOS inverter 101. The other end of the capacitor C101 is connected to the anode of the diode D101 and the cathode of the diode D102. The cathode of the diode D101 is grounded. A load capacitor C102 is connected between the anode of the diode D102 and the ground.
[0008]
In the negative voltage generation type DD converter having the above-described configuration, in principle, −1 times the power supply voltage VCC, that is, a negative DC voltage −VCC is derived between both ends of the load capacitor C102. On the other hand, the boost type DD converter shown in FIG. 11B is different from the circuit of FIG. 11A in that the diode D101 is connected between the other end of the capacitor C101 and the power supply (VCC). In principle, twice the power supply voltage VCC, that is, a DC voltage 2 × VCC is derived across the load capacitor C102.
[0009]
However, since the charge pump type DD converter according to Conventional Example 1 having the above-described configuration uses a clamp by the diode D101, the output voltage Vout is −1 even when there is no load, as is apparent from the timing chart of FIG. There is a problem that the voltage value does not reach twice or twice, and shifts by twice the threshold voltage Vth of the diode. 12A and 12B show the signal waveforms A to C of the nodes A to C in the circuits of FIGS. 11A and 11B.
[0010]
The charge pump type DD converter according to Conventional Example 2 shown in FIG. 13 improves the problems of Conventional Example 1. In FIG. 13, the same components as those in FIG. 11 are denoted by the same reference numerals. Further, (A) shows a negative voltage generation type, and (B) shows a boost type, and the basic configuration is the same.
[0011]
In FIG. 13, the drain of the Nch MOS transistor Qn102 and the source of the Pch MOS transistor Qp102 are connected to the other end of the capacitor C101. A load capacitor C102 is connected between the source of the Nch MOS transistor Qn102 and the ground. The drain of the Pch MOS transistor Qp102 is grounded.
[0012]
One end of a capacitor C103 is connected to the common gate connection point of the CMOS inverter 101. The other end of the capacitor C103 is connected to the anode of the diode D101 and the gates of the Nch MOS transistor Qn102 and the Pch MOS transistor Qp102. The cathode of the diode D101 is grounded.
[0013]
In the negative voltage generation type DD converter having the above configuration, as is apparent from the timing chart of FIG. 14A, the output voltage Vout reaches a voltage value that is −1 times the power supply voltage VCC when there is no load. . On the other hand, in the step-up type DD converter shown in FIG. 13B, the switching transistors Qp103 and Qn103 are of the reverse conductivity type, and the diode D101 is connected between the other end of the capacitor C101 and the power supply (VCC). The only difference is the circuit of FIG. 13A, and the output voltage Vout reaches twice the voltage value of the power supply voltage VCC when there is no load.
[0014]
Each timing chart of FIGS. 14A and 14B shows signal waveforms A to C of nodes A to C in the circuits of FIGS. 13A and 13B.
[0015]
[Problems to be solved by the invention]
However, in the charge pump type DD converter according to Conventional Example 2 having the above configuration, the switching pulse voltage for the switching transistors (MOS transistors Qn102 and Qp102), that is, the voltage obtained by shifting the voltage level of the node D by the threshold voltage Vth of the diode D101. Since it is clamped by the value, there is a case where a sufficient drive voltage cannot be taken for the switching transistor, particularly the Pch MOS transistor Qp102.
[0016]
For this reason, the transistor size of the Pch MOS transistor Qp102 must be set large, and as a result, problems such as an increase in circuit area or a decrease in current capacity due to an increase in transistor size occur. In addition, when the pumping operation is temporarily stopped in the power saving mode, the clamp level of the switching pulse voltage fluctuates with the change of the duty ratio of the switching pulse, resulting in a problem such as a decrease in current capacity. appear.
[0017]
The above problems become serious when the threshold value Vth of the transistor is large and when the variation is large. For example, when a circuit is formed on a glass substrate using a thin film transistor (TFT), the problem becomes an important point. Note that amorphous silicon and polysilicon (polycrystalline silicon) used for forming a thin film transistor have poor crystallinity and poor controllability of a conduction mechanism compared to single crystal silicon. It is known that there is a large variation in.
[0018]
The present invention has been made in view of the above problems, and an object thereof is to provide a power supply voltage conversion circuit capable of obtaining a large current capacity with a small circuit scale, a control method thereof, and the power supply. An object of the present invention is to provide a display device equipped with a voltage conversion circuit and a portable terminal equipped with the display device.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, in a power supply voltage conversion circuit using a charge pump having a switch element in an output section, a first clamp circuit that diode-clamps a control pulse voltage for the switch element at startup, A second clamp circuit is provided for clamping the control pulse voltage to the circuit power supply potential at the end of the startup process. The power supply voltage conversion circuit is used as a power supply circuit for a display device. A display device provided with this power supply voltage conversion circuit is used as a display unit of a portable terminal.
[0020]
In the power supply voltage conversion circuit having the above configuration, the voltage value of the control pulse voltage is shifted from the circuit power supply potential by the threshold voltage of the diode because the first clamp circuit performs diode clamping at the start-up (when the power is turned on). Clamped to potential. The output voltage is derived by operating the switch element of the output unit based on the control pulse. At the end of the startup process, the voltage value of the control pulse voltage is clamped to the circuit power supply potential. As a result, a sufficient drive voltage can be obtained for the switch element in the subsequent pumping operation.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration example of a charge pump type DD converter which is a power supply voltage conversion circuit according to an embodiment of the present invention, where (A) shows a negative voltage generation type and (B) shows a boost type. Each is shown.
[0022]
In FIG. 1, a PchMOS transistor Qp11 and an NchMOS transistor Qn11 are connected in series between a power supply that provides a single DC power supply voltage VCC and a ground (GND), and the gates are connected in common to each other. 11 is constituted. A switching pulse having a predetermined frequency is applied from the pulse generation source 12 to the common gate connection point of the CMOS inverter 11.
[0023]
One end of a capacitor C11 is connected to the common drain connection node (node B) of the CMOS inverter 11. The other end of the capacitor C11 is connected to a switch element, for example, the drain of an Nch MOS transistor Qn12 and the source of a PMOS transistor Qp12. A load capacitor C12 is connected between the source of the Nch MOS transistor Qn12 and the ground.
[0024]
One end of a capacitor C13 is connected to the common gate connection point of the CMOS inverter 11. The anode of the diode D11 is connected to the other end of the capacitor C13. The cathode of the diode D11 constitutes the first clamp circuit 13 with its cathode grounded. The other ends of the capacitor C13 are further connected to the gates of an Nch MOS transistor Qn12 and a Pch MOS transistor Qp12, respectively. The drain of the Pch MOS transistor Qp12 is grounded.
[0025]
A Pch MOS transistor Qp13 is connected between the other end of the capacitor C13 and the ground. A clamp pulse generated by the pulse generation source 14 is level-shifted by the level shift circuit 15 and applied to the gate of the Pch MOS transistor Qp13. The Pch MOS transistor Qp13, the pulse generation source 14, and the level shift circuit 15 constitute a second clamp circuit 16 that clamps the switching pulse voltage of the switching transistors (Nch MOS transistor Qn12 and Pch MOS transistor Qp12).
[0026]
In the second clamp circuit 16, the level shift circuit 15 uses the power supply voltage VCC input to the DD converter as a positive circuit power supply and the circuit output voltage Vout derived from both ends of the load capacitor C12 as a negative circuit. The power source is used, and the clamping pulse having the first amplitude (VCC-0 [V]) generated by the pulse generation source 14 is level-shifted to the clamping pulse having the second amplitude (VCC-Vout [V]). This is applied to the gate of the Pch MOS transistor Qp13. As a result, the switching operation of the Pch MOS transistor Qp13 is more reliably performed.
[0027]
Next, circuit operation in the negative voltage generation type charge pump type DD converter having the above configuration will be described with reference to a timing chart of FIG. Note that in the timing chart of FIG. 2A, signal waveforms A to G of the nodes A to G in the circuit of FIG.
[0028]
When the power is turned on (starting up), the output potential of the capacitor C13 based on the switching pulse generated by the pulse generation source 12, that is, the potential of the node D, is first grounded by the diode D11 as the negative circuit power supply potential ( “H” level is clamped to a potential shifted from the GND) level by the threshold voltage Vth of the diode D11.
[0029]
When the switching pulse is at the “L” level (0 V), the Pch MOS transistors Qp11 and Qp12 are turned on, so that the capacitor C11 is charged. At this time, since the Nch MOS transistor Qn11 is in the off state, the potential of the node B becomes the VCC level. Next, when the switching pulse becomes “H” level (VCC), the Nch MOS transistors Qn11 and Qn12 are turned on, and the potential of the node B becomes the ground level (0 V), so that the potential of the node C becomes the −VCC level. The potential of the node C becomes the output voltage Vout (= −VCC) through the Nch MOS transistor Qn12 as it is.
[0030]
Next, when the output voltage Vout rises to some extent (at the end of the startup process), the clamp pulse level shift circuit 15 starts operating. When the level shift circuit 15 starts to operate, the clamping pulse with the amplitude VCC-0 [V] generated by the pulse generation source 14 is clamped with the amplitude VCC-Vout [V] in the level shift circuit 15. And then applied to the gate of the Pch MOS transistor Qp13.
[0031]
At this time, since the “L” level of the clamping pulse is the output voltage Vout, that is, −VCC, the Pch MOS transistor Qp13 is surely turned on. As a result, the potential of the node D is clamped to the ground level (negative circuit power supply potential), not the potential shifted from the ground level by the threshold voltage Vth of the diode D11. Thereby, in the subsequent pumping operation, a sufficient drive voltage can be obtained particularly for the Pch MOS transistor Qp12.
[0032]
As described above, in the DD converter using the charge pump, the control pulse (switching pulse) voltage for the switch elements (NchMOS transistor Qn12 and PchMOS transistor Qp12) provided at the output portion is first set to the first when the circuit is started. By clamping in two stages, such as clamping by the diode D11 of the clamping circuit 13 and clamping by the second clamping circuit 16 after the start-up process is completed, a sufficient driving voltage is obtained particularly for the Pch MOS transistor Qp12. be able to.
[0033]
As a result, a sufficient switching current can be obtained in the Pch MOS transistor Qp12, so that a stable DC-DC conversion operation can be performed and conversion efficiency can be improved. In particular, since a sufficient switching current can be obtained without increasing the transistor size of the Pch MOS transistor Qp12, a DD converter having a large current capacity can be realized with a small circuit scale. The effect is particularly great when a transistor having a large threshold Vth, for example, a thin film transistor is used.
[0034]
The basic circuit configuration and circuit operation are the same also in the step-up type DD converter shown in FIG.
[0035]
That is, in FIG. 1B, the switching transistor and the second clamping transistor (MOS transistors Qp14, Qn14, Qn13) are of the opposite conductivity type to the MOS transistors Qn12, Qp12, Qp13 in the circuit of FIG. In addition, the diode D11 is connected between the other end of the capacitor C11 and the power supply (VCC), and the level shift circuit 15 uses the output voltage Vout of this circuit as the positive circuit power supply and the ground level as the negative circuit power supply. This configuration is different from the circuit of FIG. 1A only in configuration.
[0036]
The circuit operation is basically the same as the circuit of FIG. The difference is that the switching pulse voltage (control pulse voltage) is first diode-clamped at startup, clamped to VCC level (positive circuit power supply potential) at the end of the startup process, and output voltage Vout is twice the power supply voltage VCC. It is only the point from which the voltage value 2 × VCC is derived. FIG. 2B shows a timing chart of the signal waveforms A to G of the nodes A to G in the circuit of FIG.
[0037]
[Application example]
The charge pump type DD converter (power supply voltage conversion circuit) according to the above embodiment is, for example, a display device such as an active matrix type liquid crystal display device in which pixels using liquid crystal cells as electro-optical elements are arranged in a matrix. Used as a power supply circuit. An example of the configuration is shown in FIG. Here, the case of a liquid crystal display device will be described as an example.
[0038]
In FIG. 3, on a transparent insulating substrate such as a glass substrate 21, a pair of upper and lower H drivers (horizontal drive circuits) 23U and 23D, together with a display area unit 22 in which a large number of pixels including liquid crystal cells are arranged in a matrix. A V driver (vertical drive circuit) 24 is mounted, and a charge pump type power supply voltage conversion circuit 25 according to the above-described embodiment is mounted. The glass substrate 21 includes a first substrate on which a large number of pixel circuits including active elements (for example, transistors) are arranged and formed in a matrix, and a second substrate that is arranged to face the first substrate with a predetermined gap. And the substrate. Then, liquid crystal is sealed between the first and second substrates.
[0039]
FIG. 4 shows an example of a specific configuration of the display area unit 22. Here, for simplification of the drawing, the case of a pixel array of 3 rows (n−1 rows to n + 1 rows) and 4 columns (m−2 columns to m + 1 columns) is shown as an example. 4, vertical scanning lines..., 26n-1, 26n, 26n + 1,... And data lines..., 27m-2, 27m-1, 27m, 27m + 1,. The unit pixel 28 is arranged at the intersection.
[0040]
The unit pixel 28 includes a thin film transistor TFT, which is a pixel transistor, a liquid crystal cell LC, and a storage capacitor Cs. Here, the liquid crystal cell LC means a capacitance generated between a pixel electrode (one electrode) formed by a thin film transistor TFT and a counter electrode (the other electrode) formed opposite thereto.
[0041]
The thin film transistor TFT has a gate electrode connected to the vertical scanning lines..., 26n-1, 26n, 26n + 1,..., And a source electrode connected to the data lines ..., 27m-2, 27m-1, 27m, 27m + 1,. . In the liquid crystal cell LC, the pixel electrode is connected to the drain electrode of the thin film transistor TFT, and the counter electrode is connected to the common line 29. The storage capacitor Cs is connected between the drain electrode of the thin film transistor TFT and the common line 29. A predetermined DC voltage is applied to the common line 29 as a common voltage Vcom.
[0042]
One end of each of the vertical scanning lines..., 26n-1, 26n, 26n + 1,... Is connected to each output end of the corresponding row of the V driver 24 shown in FIG. The V driver 24 is constituted by, for example, a shift register, and sequentially generates vertical selection pulses in synchronization with a vertical transfer clock VCK (not shown) and applies them to the vertical scanning lines..., 26n−1, 26n, 26n + 1,. A vertical scan is performed.
[0043]
On the other hand, in the display area section 22, for example, odd-numbered data lines..., 27m-1, 27m + 1,... Are connected to output terminals of corresponding columns of the H driver 23U shown in FIG. .., 27m-2, 27m,... Are connected to the output terminals of the corresponding column of the H driver 23D shown in FIG. An example of a specific configuration of the H drivers 23U and 23D is shown in FIG.
[0044]
As shown in FIG. 5, the H driver 23U includes a shift register 31U, a sampling latch circuit (data signal input circuit) 32U, a line sequential latch circuit 33U, and a DA converter circuit 34U. The shift register 31U performs horizontal scanning by sequentially outputting shift pulses from each transfer stage in synchronization with a horizontal transfer clock HCK (not shown). The sampling latch circuit 32U samples and latches the input digital image data of a predetermined bit in a dot-sequential manner in response to the shift pulse supplied from the shift register 31U.
[0045]
The line-sequential latch circuit 33U performs line-sequencing by re-latching the digital image data latched dot-sequentially by the sampling latch circuit 32U in units of one line, and outputs the digital image data for one line at a time. . The DA conversion circuit 34U has, for example, a reference voltage selection type circuit configuration, converts the digital image data for one line output from the line-sequential latch circuit 33U into an analog image signal, and the data lines of the pixel area section 22 described above. ..., 27m-2, 27m-1, 27m, 27m + 1,.
[0046]
Similarly to the upper H driver 23U, the lower H driver 23D includes a shift register 31D, a sampling latch circuit 32D, a line sequential latch circuit 33D, and a DA conversion circuit 34D. In the liquid crystal display device according to this example, the configuration in which the H drivers 23U and 23D are arranged above and below the display area portion 22 is adopted, but the present invention is not limited to this and is arranged only in either the upper or lower side. It is also possible to adopt a configuration.
[0047]
As is apparent from FIGS. 3 and 5, the charge pump type power supply voltage conversion circuit 25 according to the above-described embodiment is also integrated on the same glass substrate 21 as the display area unit 22. Here, for example, in the case of a liquid crystal display device having a configuration in which the H drivers 23U and 23D are arranged above and below the display area unit 22, a frame area on the side where the H drivers 23U and 23D are not mounted (of the display area unit 22). It is preferable to mount the power supply voltage conversion circuit 25 in the peripheral area.
[0048]
This is because the H drivers 23U and 23D have more components than the V driver 24 as described above, and their circuit area is often very large. Therefore, the sides where the H drivers 23U and 23D are not mounted. The power supply voltage conversion circuit 25 is integrated on the same glass substrate 21 as the display area unit 22 without reducing the effective screen rate (the area rate of the effective area unit 22 with respect to the glass substrate 21). Because it can be done.
[0049]
In the liquid crystal display device according to this example, since the V driver 24 is integrated on one side of the frame area on the side where the H drivers 23U and 23D are not mounted, the frame area on the opposite side. The power supply voltage conversion circuit 25 is integrated.
[0050]
In addition, since the thin film transistor TFT is used as each pixel transistor in the display area 22 when integrating the power supply voltage conversion circuit 25, the transistors constituting the power supply voltage conversion circuit 25, that is, the MOS transistors Qp11 to Qp13, FIG. Thin film transistors are also used as the transistors constituting Qn11 to Qn13 and the level shift circuit 15, and at least these transistor circuits are manufactured by using the same process as that of the display area unit 22, thereby facilitating the manufacture and reducing the cost. Can be realized.
[0051]
In particular, among the transistor circuits, the CMOS transistor 11 operates at 0 V-VCC, and therefore, a high-voltage-required diode D11, MOS transistors Qp12, Qp13, Qn12, Qn13, and a level shift circuit 15 except for this are configured. Since a transistor is not required to be separated when it is formed of a thin film transistor, the transistor can be easily formed by using the same process as that of the display area portion 22. In this case, other transistor circuits and the like may be formed with a silicon chip on a substrate different from the glass substrate 21.
[0052]
In the above application example, the charge pump type power supply voltage conversion circuit according to the above-described embodiment is formed integrally with the display area unit 22 on the glass substrate 21, but it is not necessarily formed integrally with the display area unit 22. However, it may be used as an external circuit of the liquid crystal display device, or may be formed on a substrate different from the glass substrate 21.
[0053]
However, it is clear from the above that it is advantageous to form the display area portion 22 on the same substrate as that of the display area portion 22. In addition, the charge pump power supply voltage conversion circuit according to the above-described embodiment can obtain a large current capacity with a small circuit scale, and uses a transistor having a large threshold Vth, particularly a thin film transistor. In such a case, the effect is extremely large. Therefore, the power supply voltage conversion circuit is integrally formed on the same substrate as the display area unit 22, thereby reducing the cost of the set including the liquid crystal display device and further reducing the thickness and size of the set. Can greatly contribute to the development.
[0054]
Incidentally, some liquid crystal display devices are configured to selectively adopt a power saving mode in order to reduce power consumption of the entire device. Specifically, as shown in FIG. 6, a power saving mode control circuit 35 is provided for controlling the power supply voltage conversion circuit 25 in the power saving mode based on external mode designation information. In FIG. 6, the H drivers 23U and 23D and the V driver 24 are collectively shown as one block (driver unit).
[0055]
[Application Example 1]
FIG. 7 is a circuit diagram showing an application example 1 of the charge pump type power supply voltage conversion circuit, that is, the DD converter (see FIG. 1) according to the above-described embodiment, in a liquid crystal display device that selectively adopts the power saving mode. The case where it uses is shown. 7A shows a negative voltage generation type, and FIG. 7B shows a boost type. In FIG. 7, the same parts as those in FIG.
[0056]
7A and 7B, the configuration is exactly the same as that of FIG. 1 except that a two-input AND circuit 17 is newly added in the previous stage of the CMOS inverter 11. The 2-input AND circuit 17 receives the switching pulse generated by the pulse generation source 12 as one input, and is supplied with an “L” level mode selection signal SEL supplied from the power saving mode control circuit 35 shown in FIG. Is the other input.
[0057]
In the DD converter according to the application example 1 having the above-described configuration, the AND circuit 17 in the DD converter of the switching pulse generated by the pulse generation source 12 is supplied with the mode selection signal SEL of “L” level in the power saving mode. Stop supplying to the circuit. As a result, the pumping operation of the charge pump is temporarily stopped, so that current consumption in the DD converter circuit is reduced and power saving is achieved.
[0058]
Even when the clock supply of the charge pump is temporarily stopped by the setting of the power saving mode, as described above, the control pulse (NchMOS transistor Qn12 and PchMOS transistor Qp12) provided in the output unit is controlled ( Since the voltage of the switching pulse is clamped in two stages at the time of start-up and after the start-up process is completed, the clamp level of the node D becomes stable, so that it is sufficient even during the clock supply / stop transition period. The current capability can be ensured, and thus a stable DC-DC conversion operation is possible.
[0059]
[Application 2]
FIG. 8 is a circuit diagram showing an application example 2 of the charge pump type power supply voltage conversion circuit, that is, the DD converter (see FIG. 1) according to the above-described embodiment, and is used as a DD converter having an output potential regulation function. Is shown. 8A shows a negative voltage generation type, and FIG. 8B shows a boost type. In FIG. 8, the same parts as those in FIG.
[0060]
8A and 8B, the regulation circuit according to this example includes resistors R1 and R2 connected in series between a circuit output terminal (node E) and a power supply (VCC) or ground, and these resistors R1. , R2 is connected to a non-inverting (+) input terminal at a voltage dividing point and a reference voltage (in this example, a ground level) is applied to the inverting (−) input terminal, and the CMOS inverter 11 is disposed in the previous stage. The AND circuit 19 has the switching pulse generated by the pulse generation source 12 as one input and the comparison output of the comparator 18 as the other input.
[0061]
Except for the addition of this regulation circuit, it is exactly the same as the configuration of FIG. 1, and the charge pump operation is basically the same as the circuit of FIG. FIGS. 9A and 9B are timing charts for explaining the circuit operation of FIGS. 8A and 8B. Note that the timing charts of FIGS. 9A and 9B show the signal waveforms A to H of the nodes A to H in the circuits of FIGS. 8A and 8B, respectively.
[0062]
In the DD converter according to the application example 2 having the above configuration, the output voltage Vout is compared with the reference voltage (for example, the ground level in the negative voltage generation type (A) and the reference voltage Vref in the boost type (B)) in the comparator 18. The circuit operation for regulating the output voltage Vout to be, for example, the ground level (0 V) is performed by controlling the supply / stop of the switching pulse in the AND circuit 18 based on the comparison result.
[0063]
In the case of the negative voltage generation type (A), feedback is applied to stop the supply of the switching pulse when the output voltage Vout falls below the target voltage, and as a result, it is determined by the voltage dividing ratio of the resistors R1 and R2. A target voltage value is obtained as the output voltage Vout. In the case of the step-up type (B), feedback is applied to stop the supply of the switching pulse when the output voltage Vout rises above the target voltage, and as a result, the target voltage determined by the voltage dividing ratio of the resistors R1 and R2 A value is obtained as the output voltage Vout.
[0064]
Further, even when the clock supply of the charge pump is temporarily stopped by the regulation operation, as described above, the voltage of the control pulse (switching pulse) for the switch elements (Nch MOS transistor Qn12 and Pch MOS transistor Qp12) is set. Since clamping is performed in two stages at the time of starting and after the start-up process is completed, the clamp level of the node D is stabilized, so that a stable regulation operation is possible.
[0065]
Similarly to the DD converter (see FIG. 1) according to the embodiment described above, the active matrix liquid crystal display device shown in FIG. It can be used as a power supply circuit. Further, the present invention is not limited to application to a liquid crystal display device, but can be similarly applied to other active matrix display devices such as an EL display device using an electroluminescence (EL) element as an electro-optical element of each pixel. It is.
[0066]
The display device according to the present invention is used as a display for OA devices such as personal computers and word processors and television receivers, and in particular, cellular phones, PDAs, etc., where the main body of the device is becoming smaller and more compact. It is suitable for use as a display unit of a portable terminal.
[0067]
FIG. 10 is an external view showing a schematic configuration of a mobile terminal to which the present invention is applied, for example, a mobile phone.
[0068]
The mobile phone according to this example has a configuration in which a speaker unit 42, a display unit 43, an operation unit 44, and a microphone unit 45 are arranged in this order from the upper side on the front side of the device casing 41. In the mobile phone having such a configuration, for example, a liquid crystal display device is used as the display unit 43, and the power source voltage conversion circuit (DD converter) according to the above-described embodiment or its application examples 1 and 2 is mounted as the liquid crystal display device. A liquid crystal display device is used.
[0069]
As described above, in a portable terminal such as a cellular phone, by using the liquid crystal display device equipped with the power supply voltage conversion circuit according to the above-described embodiment or the application examples 1 and 2 as the display unit 43, these power supply voltage conversion circuits are Since a large current capacity can be obtained with a circuit area of a small area, there is an advantage that it can greatly contribute to low power consumption of the portable terminal and further downsizing and downsizing of the apparatus body.
[0070]
【The invention's effect】
As described above, according to the present invention, in the power supply voltage conversion circuit using the charge pump having the switch element in the output unit, the control pulse voltage for the switch element is diode-clamped at the start-up, and the switch element at the end of the start-up process. Since the control pulse voltage is clamped to the circuit power supply potential based on the voltage output through the switch element, a sufficient drive voltage can be obtained for the switch element, so that a stable DC-DC conversion operation is performed. Can do. Further, since it is not necessary to increase the element size, it is possible to realize a power supply voltage conversion circuit having a large current capacity with a small circuit scale.
[Brief description of the drawings]
1A and 1B are circuit diagrams showing a configuration example of a charge pump type DD converter according to an embodiment of the present invention, where FIG. 1A shows a negative voltage generation type and FIG. 1B shows a boost type.
FIGS. 2A and 2B are timing charts for explaining the circuit operation of the charge pump type DD converter according to the embodiment. FIG. 2A shows a case of a negative voltage generation type, and FIG. 2B shows a case of a boost type. ing.
FIG. 3 is a schematic configuration diagram showing a configuration example of a display device according to the present invention.
FIG. 4 is a circuit diagram illustrating a configuration example of a display area unit of a liquid crystal display device.
FIG. 5 is a block diagram illustrating an example of a specific configuration of an H driver.
FIG. 6 is a schematic configuration diagram illustrating a display device that selectively adopts a power saving mode.
7A and 7B are circuit diagrams showing a configuration example of a charge pump type DD converter according to an application example 1 of the embodiment of the present invention, where FIG. 7A shows a negative voltage generation type and FIG. 7B shows a boost type. ing.
8A and 8B are circuit diagrams showing a configuration example of a charge pump type DD converter according to an application example 2 of the embodiment of the present invention, where FIG. 8A shows a negative voltage generation type and FIG. 8B shows a boost type. ing.
FIGS. 9A and 9B are timing charts for explaining the operation of the charge pump type DD converter according to the application example 2 of the embodiment. FIG. 9A shows a case of a negative voltage generation type, and FIG. Each is shown.
FIG. 10 is an external view showing an outline of a configuration of a mobile phone which is a mobile terminal according to the present invention.
11A and 11B are circuit diagrams showing the configuration of a charge pump type DD converter according to Conventional Example 1, wherein FIG. 11A shows a negative voltage generation type and FIG. 11B shows a boost type.
FIGS. 12A and 12B are timing charts for explaining the operation of the charge pump type DD converter according to Conventional Example 1. FIG. 12A shows a case of a negative voltage generation type, and FIG. 12B shows a case of a boost type. .
FIGS. 13A and 13B are circuit diagrams showing a configuration of a charge pump type DD converter according to Conventional Example 2, wherein FIG. 13A shows a negative voltage generation type and FIG. 13B shows a boost type.
14A and 14B are timing charts for explaining the operation of the charge pump type DD converter according to Conventional Example 2, wherein FIG. 14A shows a case of a negative voltage generation type and FIG. 14B shows a case of a boost type. .
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... CMOS inverter, 12, 14 ... Pulse generation source, 13 ... 1st clamp circuit, 15 ... Level shift circuit, 16 ... 2nd clamp circuit, 17, 19 ... AND circuit, 18 ... Comparator, 21 ... Glass substrate , 22 ... display area, 23U, 23D ... H driver (horizontal drive circuit), 24 ... V driver (vertical drive circuit)

Claims (14)

Using a charge pump having two switching transistors of opposite conductivity type at the output part ,
The first clamp circuit for clamp control pulse voltage for said two switching transistors at startup,
The second example Bei a clamp circuit for clamping the circuit power supply potential and the control pulse voltage based on the output voltage to be output through the two switching transistors in startup process at the end,
The first clamp circuit includes:
A capacitor having one end connected to a switching pulse output terminal of a switching pulse generating source for generating a switching pulse, and the other end connected to each gate of the two switching transistors;
A diode connected between the other end of the capacitor and a negative or positive circuit power supply;
The second clamp circuit includes:
A MOS transistor connected between the other end of the capacitor and a negative or positive circuit power supply;
Clamping pulse generating means for generating a clamping pulse based on the voltage value of the output voltage and applying the clamping pulse to the gate of the MOS transistor.
Supply voltage conversion circuit. The two switching transistors and the MOS transistor is Ru thin film transistor der
Power supply voltage converting circuit of 請 Motomeko 1 wherein. The clamping pulse generating means includes:
A clamping pulse generation source for generating a clamping pulse;
A level shift circuit which uses a positive or negative circuit power supply potential and the output voltage as a positive or negative circuit power supply, shifts a level of a clamping pulse generated by the clamping pulse generation source, and applies it to the gate of the MOS transistor; Consist of
請 Motomeko 1 or claim 2 supply voltage converting circuit as claimed. Using a charge pump having two switching transistors of opposite conductivity type at the output part,
A capacitor having one end connected to a switching pulse output terminal of a switching pulse generating source for generating a switching pulse, and the other end connected to each gate of the two switching transistors; and
Having a diode connected between the other end of the capacitor and a negative or positive circuit power supply;
A first clamping circuit for clamping a control pulse voltage for the two switching transistors;
A MOS transistor connected between the other end of the capacitor and a negative or positive circuit power supply; and
A clamping pulse generating means for generating a clamping pulse using the voltage value of the output voltage and applying the clamping pulse to the gate of the MOS transistor;
A second clamping circuit for clamping the control pulse voltage to a circuit power supply potential based on an output voltage output through the two switching transistors;
In controlling the power supply voltage conversion circuit equipped with
First, at start-up, the first clamping circuit diode-clamps the control pulse voltage for the two switching transistors,
Next, the control pulse voltage is clamped to the circuit power supply potential based on the voltage value of the output voltage output through the two switching transistors by the second clamp circuit at the end of the starting process.
Control method of power supply voltage conversion circuit. A display area portion in which pixels having electro-optic elements are arranged in a matrix;
A vertical drive circuit for selecting each pixel in the display area section in units of rows;
A horizontal drive circuit for supplying an image signal to each pixel in a row selected by the vertical drive circuit;
A power supply voltage conversion circuit that converts a single DC voltage into a plurality of types of DC voltages having different voltage values and applies the same to the vertical drive circuit and the horizontal drive circuit,
The power supply voltage conversion circuit is:
Using a charge pump having two switching transistors of opposite conductivity type at the output part,
A first clamping circuit for clamping a control pulse voltage for the two switching transistors at start-up;
A second clamp circuit that clamps the control pulse voltage to a circuit power supply potential based on an output voltage output through the two switching transistors at the end of a startup process;
The first clamp circuit includes:
A capacitor having one end connected to a switching pulse output terminal of a switching pulse generating source for generating a switching pulse, and the other end connected to each gate of the two switching transistors;
A diode connected between the other end of the capacitor and a negative or positive circuit power supply;
The second clamp circuit includes:
A MOS transistor connected between the other end of the capacitor and a negative or positive circuit power supply;
Clamping pulse generating means for generating a clamping pulse based on the voltage value of the output voltage and applying the clamping pulse to the gate of the MOS transistor.
Display device. The clamping pulse generating means includes:
A clamping pulse generation source for generating a clamping pulse;
A level shift circuit which uses a positive or negative circuit power supply potential and the output voltage as a positive or negative circuit power supply, shifts a level of a clamping pulse generated by the clamping pulse generation source, and applies it to the gate of the MOS transistor; Consist of
The display device according to claim 5. The power supply voltage conversion circuit is integrally formed on the same substrate as the display area portion.
The display device according to claim 5 or 6. In each pixel of the display area portion, an active element that drives the electro-optic element is formed of a thin film transistor,
In the power supply voltage conversion circuit, the two switching transistors and the second clamp circuit are formed in the same process on the same substrate as the display area portion using thin film transistors, and the remaining circuits are formed of silicon chips.
The display device according to claim 5. The electro-optic element is a liquid crystal cell
The display device according to claim 5. The electro-optic element is an electroluminescence element
  The display device according to claim 5. As a display part
Using a charge pump having two switching transistors of opposite conductivity type at the output part,
A first clamping circuit for clamping a control pulse voltage for the two switching transistors;
A second clamp circuit that clamps the control pulse voltage to a circuit power supply potential based on an output voltage output through the two switching transistors;
The first clamp circuit includes:
A capacitor having one end connected to a switching pulse output terminal of a switching pulse generating source for generating a switching pulse, and the other end connected to each gate of the two switching transistors;
A diode connected between the other end of the capacitor and a negative or positive circuit power supply;
The second clamp circuit includes:
A MOS transistor connected between the other end of the capacitor and a negative or positive circuit power supply;
Clamping pulse generating means for generating a clamping pulse based on the voltage value of the output voltage and applying the clamping pulse to the gate of the MOS transistor.
Using a display device having a power supply voltage conversion circuit
Mobile device. The power supply voltage conversion circuit is integrally formed on the same substrate as the display area portion of the display portion.
The mobile terminal according to claim 11. The display device is a liquid crystal display device
The mobile terminal according to claim 11 or claim 12. The display device is an electroluminescence display device
The mobile terminal according to claim 11 or claim 12.

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