JP4378904B2 - Manufacturing method of semiconductor substrate and manufacturing method of field effect transistor - Google Patents

Manufacturing method of semiconductor substrate and manufacturing method of field effect transistor Download PDF

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JP4378904B2
JP4378904B2 JP2001302747A JP2001302747A JP4378904B2 JP 4378904 B2 JP4378904 B2 JP 4378904B2 JP 2001302747 A JP2001302747 A JP 2001302747A JP 2001302747 A JP2001302747 A JP 2001302747A JP 4378904 B2 JP4378904 B2 JP 4378904B2
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layer
sige layer
manufacturing
semiconductor substrate
oxide film
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JP2003109901A (en
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一郎 塩野
一樹 水嶋
健志 山口
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Sumco Corp
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Sumco Corp
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Description

【0001】
【発明の属する技術分野】
本発明は、高速MOSFET等に用いられる半導体基板の製造方法及び電界効果型トランジスタの製造方法並びに半導体基板及び電界効果型トランジスタに関する。
【0002】
【従来の技術】
近年、Si(シリコン)基板上にSiGe(シリコン・ゲルマニウム)層を介してエピタキシャル成長した歪みSi層をチャネル領域に用いた高速のMOSFET、MODFET、HEMTが提案されている。この歪みSi−FETでは、Siに比べて格子定数の大きいSiGeによりSi層に引っ張り歪みが生じ、そのためSiのバンド構造が変化して縮退が解けてキャリア移動度が高まる。したがって、この歪みSi層をチャネル領域として用いることにより通常の1.3〜8倍程度の高速化が可能になるものである。また、プロセスとしてCZ法による通常のSi基板を基板として使用でき、従来のCMOS工程で高速CMOSを実現可能にするものである。
【0003】
しかしながら、FETのチャネル領域として要望される上記歪みSi層をエピタキシャル成長するには、Si基板上に良質なSiGe層をエピタキシャル成長する必要があるが、SiとSiGeとの格子定数の違いから、転位等により結晶性に問題があった。このために、従来、以下のような種々の提案が行われていた。
【0004】
例えば、SiGeのGe組成比を一定の緩い傾斜で増加させたバッファ層を用いる方法、Ge(ゲルマニウム)組成比をステップ状(階段状)に変化させたバッファ層を用いる方法、Ge組成比を超格子状に変化させたバッファ層を用いる方法及びSiのオフカットウェーハを用いてGe組成比を一定の傾斜で変化させたバッファ層を用いる方法等が提案されている(U.S.Patent 5,442,205、U.S.Patent 5,221,413、PCT WO98/00857、特開平6-252046号公報等)。
【0005】
上記従来技術、例えば、Ge組成比を一定の緩い傾斜で増加させたバッファ層を用いる場合等では、発生した転位のため、転位線の分布を反映した凹凸(いわゆるクロスハッチ)が発生してしまう。この凹凸はデバイス製造工程のフォトリソグラフィ工程で問題となるため、従来は、通常のSi同様の研磨工程を用いて研磨が行われている。
【0006】
【発明が解決しようとする課題】
しかしながら、上記従来の技術では、以下のような課題が残されている。
すなわち、上記従来の技術を用いて成膜されたSiGe層は、貫通転位密度や表面ラフネスがデバイス及び製造プロセスとして要望されるレベルには及ばない状態であった。特に、上記クロスハッチは全面に均等な凹凸を生じるのではなく、およそ数μm周期で数十nmの大きな凹凸を呈するものであり、このような凹凸は、通常のSi同様の研磨では除去することができなかった。
【0007】
本発明は、前述の課題に鑑みてなされたもので、SiGe層表面のクロスハッチを除去して表面粗さを改善することができる半導体基板の製造方法及び電界効果型トランジスタの製造方法並びに半導体基板及び電界効果型トランジスタを提供することを目的とする。
【0008】
【課題を解決するための手段】
本発明は、前記課題を解決するために以下の構成を採用した。
すなわち、本発明の半導体基板の製造方法は、Si基板上にSiGe層をエピタキシャル成長させた半導体基板の製造方法であって、
前記Si基板上にSiGe層をエピタキシャル成長するとともに、前記SiGe層上にさらにSi層をエピタキシャル成長する成膜工程と、
該成膜工程後に水分を含む雰囲気ガス中で前記Si層全体および前記SiGe層上面を酸化させて酸化膜を形成する酸化膜形成工程と、
該酸化膜形成工程後に前記酸化膜をエッチングにより除去して、該半導体基板表面のクロスハッチを取り除く酸化膜除去工程と、
前記酸化膜除去工程後に、前記SiGe層表面を研磨する研磨工程と、
仕上げ研磨された前記SiGe層上に、該SiGe層の最終的なGe組成比と同じGe組成比でSiGe層をエピタキシャル成長する研磨後成膜工程と、を有し、
前記成膜工程は、前記SiGe層のうち少なくとも一部にGe組成比を表面に向けて漸次増加させた傾斜組成領域を形成することを特徴とする。
本発明は、Si基板上にSiGe層をエピタキシャル成長させた半導体基板の製造方法であって、前記Si基板上にSiGe層をエピタキシャル成長する成膜工程と、該成膜工程後に前記SiGe層上面を酸化させて酸化膜を形成する酸化膜形成工程と、該酸化膜形成工程後に前記酸化膜をエッチングにより除去する酸化膜除去工程とを有することができる。
【0009】
この半導体基板の製造方法では、成膜工程後にSiGe層上面を酸化させて酸化膜を形成する酸化膜形成工程と、該酸化膜形成工程後に酸化膜をエッチングにより除去する酸化膜除去工程とを有するので、成膜後にクロスハッチが生じているSiGe層上面の表面粗さが酸化過程で改善され、酸化膜を除去すると良好な表面ラフネスのSiGe層表面を露出させることができる。
【0010】
また、本発明の半導体基板の製造方法は、前記酸化膜形成工程において、水分を含む雰囲気ガス中で前記SiGe層上面を熱酸化することにより前記酸化膜を形成することが好ましい。この半導体基板の製造方法では、酸化膜形成工程において、水分を含む雰囲気ガス中でSiGe層上面を熱酸化、いわゆるパイロ酸化することにより、SiGe層上面近傍のGe組成比が高くなって欠陥が生じやすくなることを抑制することができる。すなわち、水分を含まない雰囲気ガス中での熱酸化、すなわちドライ酸化では、SiGe層上面にGeを含まない酸化膜(SiO2)が形成されて、SiGe層上面近傍のGe組成比が高くなってしまうのに対し、本発明ではパイロ酸化を行うので、SiとGeとがほぼ同程度の速度で酸化されるため、SiGe層上面にGeを含んだ酸化膜(Si1Ge1-x2)が形成されて、SiGe層上面近傍のGe組成比が高くなることを防ぐことができる。
【0011】
また、本発明の半導体基板の製造方法は、前記成膜工程において、前記SiGe層上にさらにSi層をエピタキシャル成長する技術が採用される。すなわち、この半導体基板の製造方法では、SiGe層上にさらにSi層をエピタキシャル成長しているので、熱酸化の初期の段階に熱によりSiGe層上面のGeが移動して表面が荒れることを防ぐことができる。
【0012】
また、本発明の半導体基板の製造方法は、前記成膜工程において、前記SiGe層のうち少なくとも一部にGe組成比を表面に向けて漸次増加させた傾斜組成領域を形成することが好ましい。すなわち、この半導体基板の製造方法では、SiGe層のうち少なくとも一部にGe組成比を表面に向けて漸次増加させた傾斜組成領域を形成するので、傾斜組成領域においてGe組成比が漸次増えるために、転位がSiGe層に沿った方向にのび易くなってSiGe層中の特に表面側で転位の密度を抑制することができる。
【0013】
また、本発明の半導体基板の製造方法は、前記酸化膜除去工程後に、前記SiGe層表面を研磨する研磨工程を有することが好ましい。すなわち、この半導体基板の製造方法では、酸化膜除去工程後にSiGe層表面を仕上げ研磨することにより、SiGe層表面の表面粗さがさらに改善される。
【0014】
本発明の半導体基板は、Si基板上にSiGe層が形成された半導体基板であって、上記本発明の半導体基板の製造方法により作製されたことを特徴とする。すなわち、この半導体基板は、上記本発明の半導体基板の製造方法により作製されているので、表面粗さが改善された良好な表面ラフネスを有している。
【0015】
本発明の半導体基板の製造方法は、Si基板上にSiGe層を介して歪みSi層が形成された半導体基板の製造方法であって、上記本発明の半導体基板の製造方法により作製された半導体基板の前記SiGe層上に直接又は他のSiGe層を介して前記歪みSi層をエピタキシャル成長することを特徴とする。
また、本発明の半導体基板は、Si基板上にSiGe層を介して歪みSi層が形成された半導体基板であって、上記本発明の歪みSi層が形成された半導体基板の製造方法により作製されたことを特徴とする。
【0016】
これらの半導体基板の製造方法及び半導体基板では、SiGe層上に直接又は他のSiGe層を介して歪みSi層がエピタキシャル成長されるので、表面ラフネスの小さな良質な歪みSi層が得られ、例えば歪みSi層をチャネル領域とするMOSFET等を用いた集積回路用として好適な半導体基板を得ることができる。
【0017】
本発明の電界効果型トランジスタの製造方法は、SiGe層上にエピタキシャル成長された歪みSi層にチャネル領域が形成される電界効果型トランジスタの製造方法であって、上記本発明の歪みSiを有する半導体基板の製造方法により作製された半導体基板の前記歪みSi層に前記チャネル領域を形成することを特徴とする。
また、本発明の電界効果型トランジスタは、SiGe層上にエピタキシャル成長された歪みSi層にチャネル領域が形成される電界効果型トランジスタであって、上記本発明の電界効果型トランジスタの製造方法により作製されたことを特徴とする。
【0018】
これらの電界効果型トランジスタの製造方法及び電界効果型トランジスタは、上記本発明の歪みSi層を有する半導体基板の製造方法により作製された半導体基板の歪みSi層にチャネル領域を形成するので、良好な表面ラフネスの歪みSi層により高特性な電界効果型トランジスタを高歩留まりで得ることができる。
【0019】
【発明の実施の形態】
以下、本発明に係る一実施形態を、図1から図3を参照しながら説明する。
【0020】
図1は、本発明の半導体ウェーハ(半導体基板)Wの断面構造を示すものであり、この半導体ウェーハの構造をその製造プロセスと合わせて説明すると、まず、CZ法等で引上成長して作製されたp型あるいはn型Si基板1上に、図1の(a)及び図2に示すように、表面に向けて層内のGe組成比を漸次減少させたSiGeの傾斜組成領域として第1のSiGe層2を例えば減圧CVD法によりエピタキシャル成長する。
【0021】
次に、第1のSiGe層2上に、該第1のSiGe層2の最終的なGe組成比で一定組成比の第2のSiGe層3を、緩和層としてエピタキシャル成長する。さらに、第2のSiGe層3上にSiをエピタキシャル成長して歪みSi層4を形成する。なお、各層の膜厚は、例えば、第1のSiGe層2が1.5μm、第2のSiGe層3が0.7〜0.8μm、歪みSi層4が15〜22nmである。また、上記減圧CVD法による成膜は、例えばキャリアガスとしてH2を用い、ソースガスとしてSiH4及びGeH4を用いている。
【0022】
上記成膜直後のウェーハは、その表面にクロスハッチ、すなわち数μm周期で数十nmの大きな凹凸が生じている。このクロスハッチを取り除くため、次に、上記成膜を行ったウェーハを熱酸化炉においてパイロ酸化、すなわち水分を含んだ雰囲気ガス中で熱酸化処理を行う。なお、熱処理温度は、800℃から1300℃の温度範囲内に設定する。この熱酸化処理により、図1の(b)に示すように、歪みSi層4全体が酸化されると共に、第2のSiGe層3の上部では、SiとGeとがほぼ同程度の速度で酸化されてGeを含んだ酸化膜3aが形成される。なお、該酸化膜3aは、十分な平坦化効果を得るために膜厚100nm以上形成しておく。
【0023】
次に、上記酸化膜3aが形成されたウェーハをフッ酸によりエッチング処理することにより、図1の(c)に示すように、酸化膜3aが除去される。この際、酸化膜3aが除去されて露出した第2のSiGe層3の表面は、成膜直後のウェーハ表面に比べてその表面粗さがP-V(Peak to Valley)で1/5程度まで小さくなる。
【0024】
さらに、酸化膜3aが除去されたウェーハの表面を、機械的化学的研磨(CMP:メカノケミカルポリッシング)により仕上げ研磨を行うことにより、表面粗さがさらに改善され、P-Vで1nm以下とすることができる。
次に、仕上げ研磨された第2のSiGe層3上に、第2のSiGe層3と同じGe組成比でSiGe層をエピタキシャル成長して、第2のSiGe層3を所定の膜厚まで厚くし、さらにその上に新たに歪みSi層5を膜厚15〜22nm程度エピタキシャル成長することにより、本実施形態の歪みSi層を備えた半導体ウェーハWが作製される。
【0025】
このように本実施形態の半導体ウェーハWでは、成膜後に第2のSiGe層3上面を酸化させて酸化膜3aを形成し、さらに酸化膜3aをエッチングにより除去するので、成膜後にクロスハッチが生じているウェーハ上面は酸化過程で表面粗さが改善され、酸化膜3aを除去すると良好な表面ラフネスの第2のSiGe層表面を露出させることができる。
【0026】
また、水分を含む雰囲気ガス中で第2のSiGe層3上面をパイロ酸化することにより、SiとGeとがほぼ同程度の速度で酸化されて第2のSiGe層3上面にGeを含んだ酸化膜3aが形成され、第2のSiGe層3上面近傍のGe組成比が必要以上に高くなることを抑制することができる。
さらに、酸化膜形成前に、第2のSiGe層3上にさらに歪みSi層4をエピタキシャル成長して保護膜としているので、熱酸化時の熱により第2のSiGe層3上面のGeが移動して表面が荒れることを防ぐことができる。
【0027】
また、第1のSiGe層2がGe組成比を表面に向けて漸次増加させた傾斜組成領域であるので、転位が第1のSiGe層2に沿った方向にのび易くなってSiGe層中の特に表面側で転位の密度を抑制することができる。
【0028】
次に、本発明の上記半導体ウェーハWを用いた電界効果型トランジスタ(MOSFET)を、その製造プロセスと合わせて図3を参照して説明する。
【0029】
図3は、本発明の電界効果型トランジスタの概略的な構造を示すものであって、この電界効果型トランジスタを製造するには、上記の製造工程で作製した半導体ウェーハW表面の歪みSi層5上にSiO2のゲート酸化膜6及びゲートポリシリコン膜7を順次堆積する。そして、チャネル領域となる部分上のゲートポリシリコン膜7上にゲート電極(図示略)をパターニングして形成する。
【0030】
次に、ゲート酸化膜6もパターニングしてゲート電極下以外の部分を除去する。さらに、ゲート電極をマスクに用いたイオン注入により、歪みSi層5及び第2のSiGe層3にn型あるいはp型のソース領域S及びドレイン領域Dを自己整合的に形成する。この後、ソース領域S及びドレイン領域D上にソース電極及びドレイン電極(図示略)をそれぞれ形成して、歪みSi層5がチャネル領域となるn型あるいはp型MOSFETが製造される。
【0031】
このように作製されたMOSFETでは、上記製法で作製された半導体ウェーハW上の歪みSi層5にチャネル領域が形成されるので、表面粗さが改善された良質な歪みSi層5により高特性なMOSFETを高歩留まりで得ることができる。
【0032】
なお、本発明の技術範囲は上記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
【0033】
例えば、上記各実施形態の半導体ウェーハの歪みSi層上に、さらにSiGe層を成膜しても構わない。
また、上記各実施形態では、MOSFET用の基板としてSiGe層を有する半導体ウェーハを作製したが、他の用途に適用する基板としても構わない。例えば、本発明の半導体基板の製造方法及び半導体基板を太陽電池や光素子用の基板に適用してもよい。すなわち、上述した各実施形態のSi基板上に最表面で65%から100%Geあるいは100%Geとなるように第1のSiGe層及び第2のSiGe層を成膜し、上記酸化膜形成、酸化膜除去及び仕上げ研磨した表面上にInGaP(インジウムガリウムリン)あるいはGaAs(ガリウムヒ素)やAlGaAs(アルミガリウムヒ素)を成膜することで、太陽電池や光素子用基板を作製してもよい。この場合、良好な表面ラフネスで高特性の太陽電池用基板が得られる。
【0034】
【発明の効果】
本発明によれば、以下の効果を奏する。
本発明の半導体基板及び半導体基板の製造方法によれば、成膜工程後にSiGe層上面を酸化させて酸化膜を形成する酸化膜形成工程と、該酸化膜形成工程後に酸化膜をエッチングにより除去する酸化膜除去工程とを有するので、酸化過程で表面粗さが改善され、酸化膜の除去により良好な表面ラフネスのSiGe層表面を有する基板を得ることができる。
さらに、このSiGe層上に歪みSi層を形成すれば、表面ラフネスの小さな良質な歪みSi層が得られ、例えば歪みSi層をチャネル領域とするMOSFET等を用いた集積回路用として好適な半導体基板を得ることができる。
【0035】
また、本発明の電界効果型トランジスタ及び電界効果型トランジスタの製造方法によれば、上記本発明の半導体基板又は上記本発明の半導体基板の製造方法により作製された半導体基板の前記歪みSi層に前記チャネル領域が形成されるので、良好な表面ラフネスで良質な歪みSi層により高特性なMOSFETを高歩留まりで得ることができる。
【図面の簡単な説明】
【図1】 本発明に係る一実施形態における半導体基板を工程順に示す断面図である。
【図2】 本発明に係る一実施形態における第1のSiGe層及び第2のSiGe層の膜厚に対するGe組成比を示すグラフである。
【図3】 本発明に係る一実施形態におけるMOSFETを示す概略的な断面図である。
【符号の説明】
1 Si基板
2 第1のSiGe層
3 第2のSiGe層
3a 酸化膜
4、5 歪みSi層
6 SiO2ゲート酸化膜
7 ゲートポリシリコン膜
S ソース領域
D ドレイン領域
W 半導体ウェーハ(半導体基板)
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor substrate, a method for manufacturing a field effect transistor, a semiconductor substrate and a field effect transistor used for a high-speed MOSFET or the like.
[0002]
[Prior art]
In recent years, high-speed MOSFETs, MODFETs, and HEMTs using a strained Si layer epitaxially grown on a Si (silicon) substrate via a SiGe (silicon-germanium) layer as a channel region have been proposed. In this strained Si-FET, tensile strain is generated in the Si layer due to SiGe having a larger lattice constant than Si, so that the band structure of Si is changed, the degeneracy is solved, and the carrier mobility is increased. Therefore, by using this strained Si layer as the channel region, the speed can be increased by about 1.3 to 8 times the normal speed. Further, a normal Si substrate by the CZ method can be used as a substrate as a process, and a high-speed CMOS can be realized by a conventional CMOS process.
[0003]
However, in order to epitaxially grow the strained Si layer required as the channel region of the FET, it is necessary to epitaxially grow a high-quality SiGe layer on the Si substrate, but due to the difference in lattice constant between Si and SiGe, There was a problem with crystallinity. For this purpose, various proposals have been made in the past.
[0004]
For example, a method using a buffer layer in which the Ge composition ratio of SiGe is increased at a constant gentle slope, a method using a buffer layer in which the Ge (germanium) composition ratio is changed stepwise (stepped), and a Ge composition ratio exceeding There have been proposed a method using a buffer layer changed into a lattice shape and a method using a buffer layer in which the Ge composition ratio is changed at a constant gradient using a Si off-cut wafer (US Patent 5,442,205, US Patent 5,221,413, PCT). WO98 / 00857, JP-A-62-252046, etc.).
[0005]
In the above-described prior art, for example, in the case of using a buffer layer in which the Ge composition ratio is increased with a constant gentle slope, unevenness (so-called cross hatch) reflecting the distribution of dislocation lines occurs due to the generated dislocations. . Since this unevenness becomes a problem in the photolithography process of the device manufacturing process, conventionally, polishing is performed using a polishing process similar to that of normal Si.
[0006]
[Problems to be solved by the invention]
However, the following problems remain in the conventional technology.
That is, the SiGe layer formed by using the above-described conventional technique is in a state where the threading dislocation density and the surface roughness do not reach the level required for the device and the manufacturing process. In particular, the cross hatch does not cause uniform unevenness on the entire surface, but presents large unevenness of several tens of nanometers with a period of several μm. Such unevenness should be removed by polishing similar to normal Si. I could not.
[0007]
The present invention has been made in view of the above-described problems, and a semiconductor substrate manufacturing method, a field effect transistor manufacturing method, and a semiconductor substrate capable of improving the surface roughness by removing cross hatching on the surface of the SiGe layer It is another object of the present invention to provide a field effect transistor.
[0008]
[Means for Solving the Problems]
The present invention employs the following configuration in order to solve the above problems.
That is, the semiconductor substrate manufacturing method of the present invention is a semiconductor substrate manufacturing method in which a SiGe layer is epitaxially grown on a Si substrate,
A film forming step of epitaxially growing a SiGe layer on the Si substrate and further epitaxially growing a Si layer on the SiGe layer;
An oxide film forming step of forming an oxide film by oxidizing the entire Si layer and the upper surface of the SiGe layer in an atmospheric gas containing moisture after the film forming step;
The oxide film after the oxide film formation step is removed by etching, and the oxide film removing step of removing the Ri taken crosshatch of the semiconductor substrate surface,
A polishing step of polishing the surface of the SiGe layer after the oxide film removing step;
A post-polishing film forming step of epitaxially growing a SiGe layer on the finish-polished SiGe layer with the same Ge composition ratio as the final Ge composition ratio of the SiGe layer;
In the film forming step, a gradient composition region in which a Ge composition ratio is gradually increased toward the surface is formed in at least a part of the SiGe layer.
The present invention is a method of manufacturing a semiconductor substrate in which a SiGe layer is epitaxially grown on a Si substrate, the film forming step of epitaxially growing a SiGe layer on the Si substrate, and oxidizing the upper surface of the SiGe layer after the film forming step. An oxide film forming step for forming an oxide film, and an oxide film removing step for removing the oxide film by etching after the oxide film forming step.
[0009]
This method for manufacturing a semiconductor substrate includes an oxide film forming process for forming an oxide film by oxidizing the upper surface of the SiGe layer after the film forming process, and an oxide film removing process for removing the oxide film by etching after the oxide film forming process. Therefore, the surface roughness of the upper surface of the SiGe layer in which cross hatching occurs after film formation is improved during the oxidation process, and when the oxide film is removed, the surface of the SiGe layer having good surface roughness can be exposed.
[0010]
In the method for manufacturing a semiconductor substrate of the present invention, it is preferable that the oxide film is formed by thermally oxidizing the upper surface of the SiGe layer in an atmosphere gas containing moisture in the oxide film forming step. In this method of manufacturing a semiconductor substrate, in the oxide film forming step, the upper surface of the SiGe layer is thermally oxidized, that is, pyro-oxidized in an atmosphere gas containing moisture, so that the Ge composition ratio in the vicinity of the upper surface of the SiGe layer is increased and defects are generated. It can suppress becoming easy. That is, in thermal oxidation in an atmospheric gas not containing moisture, that is, dry oxidation, an oxide film (SiO 2 ) not containing Ge is formed on the upper surface of the SiGe layer, and the Ge composition ratio in the vicinity of the upper surface of the SiGe layer is increased. In contrast, since pyro oxidation is performed in the present invention, Si and Ge are oxidized at approximately the same rate, so that an oxide film containing Si on the upper surface of the SiGe layer (Si 1 Ge 1-x O 2 ). Can be prevented, and the Ge composition ratio in the vicinity of the upper surface of the SiGe layer can be prevented from increasing.
[0011]
In addition, the method for manufacturing a semiconductor substrate of the present invention employs a technique in which a Si layer is further epitaxially grown on the SiGe layer in the film forming step. That is, in this method of manufacturing a semiconductor substrate, since the Si layer is further epitaxially grown on the SiGe layer, it is possible to prevent the surface of the SiGe layer from being roughened by the movement of Ge on the upper surface of the SiGe layer by heat in the initial stage of thermal oxidation. it can.
[0012]
In the method of manufacturing a semiconductor substrate according to the present invention, it is preferable that in the film forming step, a gradient composition region in which a Ge composition ratio is gradually increased toward the surface is formed in at least a part of the SiGe layer. That is, in this semiconductor substrate manufacturing method, a gradient composition region in which the Ge composition ratio is gradually increased toward the surface is formed in at least a part of the SiGe layer, so that the Ge composition ratio gradually increases in the gradient composition region. The dislocations easily extend in the direction along the SiGe layer, and the density of dislocations can be suppressed particularly in the surface side of the SiGe layer.
[0013]
Moreover, it is preferable that the manufacturing method of the semiconductor substrate of this invention has a grinding | polishing process which grind | polishes the said SiGe layer surface after the said oxide film removal process. That is, in this semiconductor substrate manufacturing method, the surface roughness of the SiGe layer surface is further improved by finishing and polishing the surface of the SiGe layer after the oxide film removing step.
[0014]
The semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, and is manufactured by the method for manufacturing a semiconductor substrate of the present invention. That is, since this semiconductor substrate is manufactured by the method for manufacturing a semiconductor substrate according to the present invention, it has a good surface roughness with improved surface roughness.
[0015]
The semiconductor substrate manufacturing method of the present invention is a semiconductor substrate manufacturing method in which a strained Si layer is formed on a Si substrate via a SiGe layer, and the semiconductor substrate manufactured by the above-described semiconductor substrate manufacturing method of the present invention. The strained Si layer is epitaxially grown directly on the SiGe layer or via another SiGe layer.
The semiconductor substrate of the present invention is a semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer, and is manufactured by the method for manufacturing a semiconductor substrate in which the strained Si layer of the present invention is formed. It is characterized by that.
[0016]
In these semiconductor substrate manufacturing methods and semiconductor substrates, since the strained Si layer is epitaxially grown directly on the SiGe layer or via another SiGe layer, a high-quality strained Si layer having a small surface roughness can be obtained. A semiconductor substrate suitable for an integrated circuit using a MOSFET or the like having a layer as a channel region can be obtained.
[0017]
A method for manufacturing a field effect transistor according to the present invention is a method for manufacturing a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, the semiconductor substrate having strained Si according to the present invention. The channel region is formed in the strained Si layer of the semiconductor substrate manufactured by the manufacturing method.
The field effect transistor of the present invention is a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, and is manufactured by the method for manufacturing a field effect transistor of the present invention. It is characterized by that.
[0018]
The field effect transistor manufacturing method and the field effect transistor are excellent because the channel region is formed in the strained Si layer of the semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate having the strained Si layer of the present invention. A high-effect field-effect transistor can be obtained with a high yield by using a strained Si layer with surface roughness.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment according to the present invention will be described with reference to FIGS. 1 to 3.
[0020]
FIG. 1 shows a cross-sectional structure of a semiconductor wafer (semiconductor substrate) W of the present invention. The structure of this semiconductor wafer will be described together with its manufacturing process. On the p-type or n-type Si substrate 1, as shown in FIG. 1A and FIG. 2, the first SiGe graded composition region in which the Ge composition ratio in the layer is gradually decreased toward the surface is first. The SiGe layer 2 is epitaxially grown by, for example, a low pressure CVD method.
[0021]
Next, the second SiGe layer 3 having a constant composition ratio in the final Ge composition ratio of the first SiGe layer 2 is epitaxially grown on the first SiGe layer 2 as a relaxation layer. Further, Si is epitaxially grown on the second SiGe layer 3 to form a strained Si layer 4. The thickness of each layer is, for example, 1.5 μm for the first SiGe layer 2, 0.7 to 0.8 μm for the second SiGe layer 3, and 15 to 22 nm for the strained Si layer 4. The film formation by the low pressure CVD method uses, for example, H 2 as a carrier gas and SiH 4 and GeH 4 as source gases.
[0022]
The wafer immediately after the film formation has a cross-hatch on the surface, that is, large irregularities of several tens of nanometers with a period of several μm. In order to remove this cross hatch, the wafer on which the film has been formed is then subjected to pyro-oxidation in a thermal oxidation furnace, that is, thermal oxidation treatment in an atmosphere gas containing moisture. The heat treatment temperature is set within a temperature range of 800 ° C. to 1300 ° C. As a result of this thermal oxidation treatment, the entire strained Si layer 4 is oxidized as shown in FIG. 1B, and Si and Ge are oxidized at substantially the same rate above the second SiGe layer 3. Thus, an oxide film 3a containing Ge is formed. The oxide film 3a is formed with a thickness of 100 nm or more in order to obtain a sufficient planarization effect.
[0023]
Next, the oxide film 3a is removed by etching the wafer on which the oxide film 3a is formed with hydrofluoric acid, as shown in FIG. At this time, the surface of the second SiGe layer 3 exposed by removing the oxide film 3a has a surface roughness of about 1/5 in terms of PV (Peak to Valley) compared to the wafer surface immediately after film formation. Get smaller.
[0024]
Further, the surface roughness of the wafer from which the oxide film 3a has been removed is further polished by mechanical chemical polishing (CMP: mechanochemical polishing), so that the surface roughness is further improved and the PV is reduced to 1 nm or less. be able to.
Next, a SiGe layer is epitaxially grown on the finish-polished second SiGe layer 3 with the same Ge composition ratio as the second SiGe layer 3 to increase the thickness of the second SiGe layer 3 to a predetermined thickness. Further, a strained Si layer 5 is newly epitaxially grown on the film with a thickness of about 15 to 22 nm, whereby a semiconductor wafer W provided with the strained Si layer of this embodiment is manufactured.
[0025]
As described above, in the semiconductor wafer W of the present embodiment, the upper surface of the second SiGe layer 3 is oxidized to form the oxide film 3a and the oxide film 3a is removed by etching. The resulting wafer upper surface is improved in surface roughness during the oxidation process, and when the oxide film 3a is removed, the surface of the second SiGe layer having good surface roughness can be exposed.
[0026]
Further, by pyro-oxidizing the upper surface of the second SiGe layer 3 in an atmosphere gas containing moisture, Si and Ge are oxidized at substantially the same rate, and the upper surface of the second SiGe layer 3 is oxidized containing Ge. The film 3a is formed, and the Ge composition ratio in the vicinity of the upper surface of the second SiGe layer 3 can be suppressed from becoming higher than necessary.
Further, since the strained Si layer 4 is further epitaxially grown on the second SiGe layer 3 to form a protective film before the oxide film is formed, the Ge on the upper surface of the second SiGe layer 3 is moved by the heat during thermal oxidation. The rough surface can be prevented.
[0027]
Further, since the first SiGe layer 2 is a graded composition region in which the Ge composition ratio is gradually increased toward the surface, dislocations easily extend in the direction along the first SiGe layer 2, particularly in the SiGe layer. Dislocation density can be suppressed on the surface side.
[0028]
Next, a field effect transistor (MOSFET) using the semiconductor wafer W of the present invention will be described with reference to FIG.
[0029]
FIG. 3 shows a schematic structure of the field effect transistor of the present invention. In order to manufacture this field effect transistor, the strained Si layer 5 on the surface of the semiconductor wafer W manufactured in the above manufacturing process is shown. A SiO 2 gate oxide film 6 and a gate polysilicon film 7 are sequentially deposited thereon. Then, a gate electrode (not shown) is formed by patterning on the gate polysilicon film 7 on the portion to become the channel region.
[0030]
Next, the gate oxide film 6 is also patterned to remove portions other than those under the gate electrode. Further, an n-type or p-type source region S and drain region D are formed in a self-aligned manner in the strained Si layer 5 and the second SiGe layer 3 by ion implantation using the gate electrode as a mask. Thereafter, a source electrode and a drain electrode (not shown) are formed on the source region S and the drain region D, respectively, and an n-type or p-type MOSFET in which the strained Si layer 5 serves as a channel region is manufactured.
[0031]
In the MOSFET manufactured in this way, a channel region is formed in the strained Si layer 5 on the semiconductor wafer W manufactured by the above-described manufacturing method. Therefore, the high-quality strained Si layer 5 with improved surface roughness has high characteristics. MOSFET can be obtained with high yield.
[0032]
The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
[0033]
For example, a SiGe layer may be further formed on the strained Si layer of the semiconductor wafer of each of the above embodiments.
In each of the above embodiments, a semiconductor wafer having a SiGe layer is manufactured as a substrate for MOSFET. However, the substrate may be applied to other applications. For example, you may apply the manufacturing method and semiconductor substrate of the semiconductor substrate of this invention to the board | substrate for solar cells or an optical element. That is, the first SiGe layer and the second SiGe layer are formed on the Si substrate of each of the above-described embodiments so that the outermost surface has 65% to 100% Ge or 100% Ge, and the oxide film formation is performed. A substrate for a solar cell or an optical device may be manufactured by depositing InGaP (indium gallium phosphide), GaAs (gallium arsenide), or AlGaAs (aluminum gallium arsenide) on the surface after oxide film removal and finish polishing. In this case, a high-performance solar cell substrate with good surface roughness can be obtained.
[0034]
【The invention's effect】
The present invention has the following effects.
According to the semiconductor substrate and the method of manufacturing a semiconductor substrate of the present invention, an oxide film forming step of forming an oxide film by oxidizing the upper surface of the SiGe layer after the film forming step, and removing the oxide film by etching after the oxide film forming step. The surface roughness is improved during the oxidation process, and a substrate having a SiGe layer surface with good surface roughness can be obtained by removing the oxide film.
Furthermore, if a strained Si layer is formed on this SiGe layer, a high-quality strained Si layer having a small surface roughness can be obtained. For example, a semiconductor substrate suitable for an integrated circuit using a MOSFET having a strained Si layer as a channel region. Can be obtained.
[0035]
Further, according to the field effect transistor and the method of manufacturing a field effect transistor of the present invention, the strained Si layer of the semiconductor substrate of the present invention or the semiconductor substrate manufactured by the method of manufacturing the semiconductor substrate of the present invention is Since the channel region is formed, a high-quality MOSFET can be obtained with a high yield by a high-quality strained Si layer with good surface roughness.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor substrate in one embodiment according to the invention in the order of steps.
FIG. 2 is a graph showing a Ge composition ratio with respect to film thicknesses of a first SiGe layer and a second SiGe layer in an embodiment according to the present invention.
FIG. 3 is a schematic cross-sectional view showing a MOSFET according to an embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Si substrate 2 1st SiGe layer 3 2nd SiGe layer 3a Oxide film 4, 5 Strained Si layer 6 SiO 2 Gate oxide film 7 Gate polysilicon film S Source region D Drain region W Semiconductor wafer (semiconductor substrate)

Claims (3)

Si基板上にSiGe層をエピタキシャル成長させた半導体基板の製造方法であって、
前記Si基板上にSiGe層をエピタキシャル成長するとともに、前記SiGe層上にさらにSi層をエピタキシャル成長する成膜工程と、
該成膜工程後に水分を含む雰囲気ガス中で前記Si層全体および前記SiGe層上面を酸化させて酸化膜を形成する酸化膜形成工程と、
該酸化膜形成工程後に前記酸化膜をエッチングにより除去して、該半導体基板表面のクロスハッチを取り除く酸化膜除去工程と、
前記酸化膜除去工程後に、前記SiGe層表面を研磨する研磨工程と、
仕上げ研磨された前記SiGe層上に、該SiGe層の最終的なGe組成比と同じGe組成比でSiGe層をエピタキシャル成長する研磨後成膜工程と、を有し、
前記成膜工程は、前記SiGe層のうち少なくとも一部にGe組成比を表面に向けて漸次増加させた傾斜組成領域を形成することを特徴とする半導体基板の製造方法。
A method of manufacturing a semiconductor substrate in which a SiGe layer is epitaxially grown on a Si substrate,
A film forming step of epitaxially growing a SiGe layer on the Si substrate and further epitaxially growing a Si layer on the SiGe layer;
An oxide film forming step of forming an oxide film by oxidizing the entire Si layer and the upper surface of the SiGe layer in an atmospheric gas containing moisture after the film forming step;
The oxide film after the oxide film formation step is removed by etching, and the oxide film removing step of removing the Ri taken crosshatch of the semiconductor substrate surface,
A polishing step of polishing the surface of the SiGe layer after the oxide film removing step;
A post-polishing film forming step of epitaxially growing a SiGe layer on the finish-polished SiGe layer with the same Ge composition ratio as the final Ge composition ratio of the SiGe layer;
In the method of manufacturing a semiconductor substrate, the film forming step forms a gradient composition region in which a Ge composition ratio is gradually increased toward the surface in at least a part of the SiGe layer.
Si基板上にSiGe層を介して歪みSi層が形成された半導体基板の製造方法であって、
請求項1に記載の半導体基板の製造方法により作製された半導体基板の前記SiGe層上に直接又は他のSiGe層を介して前記歪みSi層をエピタキシャル成長することを特徴とする半導体基板の製造方法。
A method of manufacturing a semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer,
A method for manufacturing a semiconductor substrate, comprising: epitaxially growing the strained Si layer directly on the SiGe layer of the semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 1 or via another SiGe layer.
SiGe層上にエピタキシャル成長された歪みSi層にチャネル領域が形成される電界効果型トランジスタの製造方法であって、
請求項2に記載の半導体基板の製造方法により作製された半導体基板の前記歪みSi層に前記チャネル領域を形成することを特徴とする電界効果型トランジスタの製造方法。
A method of manufacturing a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer,
A method for manufacturing a field effect transistor, comprising forming the channel region in the strained Si layer of a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 2.
JP2001302747A 2001-09-28 2001-09-28 Manufacturing method of semiconductor substrate and manufacturing method of field effect transistor Expired - Fee Related JP4378904B2 (en)

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