JP3589033B2 - Flash memory system - Google Patents

Description

[0010]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory system including a flash memory.
[0020]
[Prior art]
2. Description of the Related Art In recent years, a flash EEPROM (hereinafter referred to as a flash memory) has attracted attention as a semiconductor memory replacing a magnetic memory such as a hard disk or a floppy disk. A flash memory is an electrically rewritable nonvolatile semiconductor memory with low power consumption, and is widely used for portable devices and the like because of its light weight, small size, and good earthquake resistance.
[0030]
In a flash memory, an EEPROM cell array in a chip is divided into a plurality of blocks, and each block is further divided into one or a plurality of sectors. Usually, programming (writing) and reading are performed in sector units, and erasing is performed in block units.
[0040]
Generally, in a computer system using a flash memory as an external storage device, a controller dedicated to the flash memory is used. The host computer (for example, a personal computer) may instruct this controller to write or read data. The controller directly controls writing and reading of data to and from the flash memory in response to an instruction from the host, and also performs memory management such as data rewriting and batch erasing for each block.
[0050]
As a part of such memory management, the controller is required to have a management function of recognizing a defective (defective) block in which data cannot be written or read normally and replacing each defective block with another normal block.
[0060]
A general flash memory system prepares an appropriate number of spare or spare blocks in a part of the memory area so that the existence or occurrence of such a defective block is allowed to a certain number. Usually, these spare blocks are used as replacement blocks.
[0070]
In a conventional flash memory system, a flag or status information indicating whether the block is normal or bad is stored in a redundant portion of each block of the flash memory. Also, address information (pointer) indicating the storage position of the replacement block to be replaced is stored. Each time a memory access is performed by the host, the controller reads the block pass / fail flag information of the addressed block, and if the block is “normal”, accesses the block as it is, and if “bad”, indicates with the pointer. To access another block (alternate block).
[0080]
[Problems to be solved by the invention]
As described above, in the conventional method, the block related information such as the block pass / fail flag is stored (saved) in the redundant portion of each block in the flash memory, and the controller stores the block related information of the block every time the memory is accessed. By reading, it is determined whether or not block replacement is necessary.
[0090]
Therefore, when the address from the host side designates a bad block, the bad block is accessed, the block related information is read therefrom, the necessity of block replacement is determined, and then the replacement block is accessed. . That is, a data read operation for two blocks is performed.
[0100]
Such a block replacement management method is not only inefficient, but also necessitates determining whether block replacement is necessary based on unreliable data (block-related information) read from a bad block. There is a problem that the reliability of the block replacement function is low. Furthermore, access to a bad block may give harmful stress to the flash memory, and may accelerate the deterioration of the memory.
[0110]
During initialization immediately after power-on or immediately after reset release, the controller reads the redundant parts of all the blocks in the flash memory, collects the respective block-related information, and based on the collected block-related information. For example, a method of forming a table for block replacement on a volatile memory such as an SRAM has been considered.
[0120]
According to this method, in response to a memory access from the host, a block replacement table is first referred to determine whether the addressed block is normal or defective, that is, whether or not block replacement is necessary. Is determined, and the block or the substitute block is accessed.
[0130]
However, even with this method, a defective block is accessed at the time of initialization (table formation), and the number of accesses is reduced, but the above problem is not basically solved. In addition, since this method collects block-related information for all blocks in the flash memory, there is a problem that the processing time required for forming the block replacement table is long and the storage capacity required for the table memory is large. In recent years, flash memories have been rapidly increasing in capacity, and this disadvantage has become more pronounced.
[0140]
The present invention has been made in view of the above problems, and has as its object to provide a flash memory system capable of efficiently performing block replacement management with a small amount of resources.
[0150]
It is another object of the present invention to provide a flash memory system which can perform unnecessary block access management with high reliability and efficiency by eliminating useless access to a bad block.
[0160]
A further object of the present invention is to provide a flash memory system that can efficiently access a substitute block that replaces a defective block in a short time.
[0170]
[Means for Solving the Problems]
In order to achieve the above object, a first flash memory system according to the present invention includes a flash memory configured to divide a storage area into a plurality of blocks, and to erase storage data collectively in block units; The address assigned to the block determined to be bad in the memorySearchableBlock replacement information registration for registering and providing a replacement address indicating a storage position of a replacement block to be used in place of the defective blockmemoryAnd an address given for memory access to the flash memory, and the input address is the block replacement information registrationmemoryIf the block is not registered in the flash memory, the block in the flash memory specified by the input address is accessed, and the input address is registered in the block replacement information.memoryAccess to a block in the flash memory designated by the alternative address corresponding to the input addressMemory control unitAndThe memory control unit is connected to the flash memory via a first bus, the memory control unit is connected to the block replacement information registration memory via a second bus, and the memory control unit via the first bus. The operation between the flash memory and the flash memory and the operation between the memory control unit and the block replacement information registration memory via the second bus are performed independently.
[0180]
The second flash memory system according to the present invention may further comprise a flash memory configured to divide a storage area into a plurality of blocks and collectively erase storage data in block units, and determine that the flash memory is defective. The logical address assigned to the blockSearchableBlock replacement information registration that registers and assigns, as a replacement address, a physical address assigned to a replacement block to be used in place of each defective block.memoryInputting an address given for memory access to the flash memory, converting the input address into a logical address in the flash memory, and registering the logical address with the block replacement informationmemoryWhen the logical address is not registered in the flash memory, the block in the flash memory indicated by the logical address is accessed, and the logical address is registered in the block replacement information.memoryAccess to the block in the flash memory designated by the substitute address corresponding to the logical addressMemory control unitAndThe memory control unit is connected to the flash memory via a first bus, the memory control unit is connected to the block replacement information registration memory via a second bus, and the memory control unit via the first bus. The operation between the flash memory and the flash memory and the operation between the memory control unit and the block replacement information registration memory via the second bus are performed independently.
[0190]
According to the present invention, the memory control unit and the block replacement information registration memory are independent of the data read / write / erase operations performed between the memory control unit and the flash memory via the first bus. Operations such as search / update are performed via the second bus. In one aspect, if the block accessed by the memory control unit in the flash memory is found to be a defective block, the memory control unit places the first and second buses in the flash memory and the block replacement information registration memory, respectively. In parallel, an erasing process for erasing the storage contents of the defective block in the flash memory and a process of searching for and updating the registration information in the block replacement information registration memory are performed in parallel. By such parallel processing, block replacement management can be efficiently developed.
[0200]
In the present invention, the block replacement information registration memory has a plurality of storage locations corresponding one-to-one with a plurality of spare blocks set as replacement blocks in the flash memory, and one of the spare blocks is replaced. When used as a block, it may include a non-volatile storage means for storing address information indicating an address assigned to a defective block replaced by the defective block in a storage location corresponding to the spare block.
[0210]
Further, at each storage location in the block replacement information registration memory, when the corresponding spare block is not used as a replacement block, first status information indicating its empty state may be stored. Second status information indicating whether the spare block to be used is normal or defective may also be stored.
[0220]
The block replacement information registration memory includes address generation means for obtaining an address of a replacement block replacing each defective block based on an address of a storage location where address information corresponding to the defective block is stored. Good. In this case, preferably, the address generation means obtains the address of the replacement block replacing the bad block by adding a predetermined offset value to the address of the storage location where the address information corresponding to the bad block is stored. Good.
[0230]
In the present invention, preferably, the nonvolatile storage means may be a NOR flash memory.
[0240]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0250]
FIG. 1 shows a configuration of a flash memory system according to an embodiment of the present invention. In this system, each chip of the controller 10, the table memory 12, and the flash memory 14 is mounted on one card, for example, a flash disk card 16. The card 16 is inserted into a card slot of the host computer 18, and the controller 10 is connected to the host computer 18 by an interface of a predetermined standard, for example, a PCMCIA-ATA or IDE interface 20.
[0260]
The flash memory 14 is a memory from / to which data can be written / read from the host 18 via the controller 10. For example, the flash memory 14 includes one or more (n) AND type flash EEPROM chips having the same configuration and function. It is connected to the controller 10 via a bus 22 and a required control line 24.
[0270]
The table memory 12 is composed of a nonvolatile semiconductor memory chip, for example, a NOR type flash memory placed under the control of the controller 10 independently of the host 18, and has a bus 26 and a control unit separate from the flash memory 14 for storing data. It is connected to controller 10 via line 28. In the table memory 12, a block replacement management table described later is constructed.
[0280]
FIG. 2 is a block diagram showing a functional configuration inside the controller 10 in the present embodiment. The controller 10 has a main sequencer 30, a flash I / F sequencer 32, a host interface unit 34, a data buffer 36, and a buffer control unit 38.
[0290]
The main sequencer 30 operates in accordance with the built-in or external firmware and controls each unit in the controller 10 to manage the exchange of data between the host 18 and the flash memory 14 as well as to directly access the table memory 12. It has a function to perform necessary and necessary memory control.
[0300]
The flash I / F sequencer 32 directly accesses the flash memory 14 under the control of the main sequencer 30 to perform necessary memory control.
[0310]
The host interface unit 34 includes a CHS register 40, an address conversion unit 42, a logic control unit 44, an I / O port 46, and the like. The CHS register 40 holds a CHS (cylinder head sector) mode address sent from the host 18. The address conversion unit 42 has an arithmetic function for converting a CHS address from the host 18 into a logical address in the system, and also has an arithmetic function for automatically updating a logical address.
[0320]
The logic control unit 44 includes various registers that can be written or read from the host 18 side, and has a function of decoding the written command and controlling the address conversion unit 42, the buffer control unit 38, and the like. I have.
[0330]
The I / O port 46 is connected to the bus 20 of the host 18 via an interface of a predetermined standard, for example, a PCMCIA-ATA or IDE interface, and has a multiplexer function for transferring data and control signals input from the host 18 to each unit. Address for decoding the address signal received from host 18decoderBuilt-in.
[0340]
The data buffer 36 is composed of a volatile semiconductor memory, for example, an SRAM. The buffer control unit 38 receives a request to write / read data from / to the data buffer 36 from the main sequencer 30, the flash I / F sequencer 32, or the I / O port 46, performs arbitration, and writes data into the data buffer 36. / Control the read operation.
[0350]
The main sequencer 30 and the flash I / F sequencer 32, the host interface unit 34, and the buffer control unit 38 are connected by data buses and control lines. These data buses are hardware-related. A common bus may be used, and the table memory 12 may be connected to the common bus.
[0360]
FIG. 3 shows an example of a storage area format in one block in the flash memory 14. The memory area in each chip FMi (i = 1, 2,..., N) of the flash memory 14 is divided into a predetermined number (N) of blocks, and the storage area in each block is divided in a predetermined format. .
[0370]
In the format example of FIG. 3, one block has a 512-byte (one sector) data storage unit, a 4-byte ECC (Error Check and Correction) code storage unit, and a 12-byte unused area (Reserve). It is classified. Since one block corresponds to one sector of a writing unit, not only erasing but also writing is performed in units of one block.
[0380]
FIG. 4 shows an example of a storage area format of the flash memory chip FMi. In this example, the storage area in each chip FMi is divided into 16384 blocks, and the physical addresses 0, 1,..., 16383 are assigned to each block in the order of arrangement.
[0390]
In the present embodiment, the logical address and the physical address correspond to the same value in a place where the replacement of the block is not performed in each flash memory chip FMi, and the logical address having the same value as the physical address is assigned.
[0400]
Of the 16384 blocks in each flash memory chip FMi, the 0th to 15359th blocks belong to a normal area and are used as data storage blocks as long as they are normal. The remaining blocks, that is, the 1024 blocks from the 15360th to the 16383th (last) belong to the spare area, and are used as replacement blocks when a defective block exists in the normal area.
[0410]
FIG. 4 also shows an example of a block replacement management table constructed in the table memory 12. In this embodiment, the same number (1024) of table addresses (physical addresses) as the number of blocks or addresses in the spare area for each flash memory chip FMi is set in the block replacement management table TBi, and each table address is set to 1 It is associated with the physical address of any one of the spare blocks in a one-to-one correspondence.
[0420]
In this example, the table address and the spare block physical address having the same arrangement order in the spare area and the table area respectively correspond to each other, and when a certain offset value AS (15360) is added to each table address, the table address becomes There is a relationship that a spare block physical address corresponding to the address is obtained.
[0430]
At the table storage location designated by each table address, information on the state of the spare block corresponding to the table address is stored as block replacement information with a predetermined data length, for example, 1 word (16 bits).
[0440]
FIG. 5 shows an example of the data format of the block replacement information in the present embodiment. In the one-word block replacement information B15-00, information indicating the pass / fail state of the (corresponding) spare block is set in the most significant two bits B15-14. That is, "11" and "00" are set in the pass / fail flag bits B15-14 according to whether the spare block is "normal" or "bad".
[0450]
It should be noted that in the present embodiment, that the block is “normal” means that it was normal when the spare block was accessed last time, and the current state is not always normal. Further, since the subsequent access to the block determined to be "bad" is prohibited, the pass / fail flag bit B15-14 once set to "00" does not change to "11".
[0460]
The field B13-00 of the lower 14 bits becomes significant when the most significant bit (pass / fail flag bit) B15-14 is "11", and indicates whether the spare block is in an unused state, that is, an empty state, or is being used as a substitute block. The information indicating whether the state is the state of is set.
[0470]
That is, when the spare block is empty, 1 is set to all bits of the field B13-00. Therefore, all the bits of the block replacement information B15-00 have a value of 1, that is, FFFFh.
[0480]
When the spare block is used as a replacement block, the field B13-00 contains the logical address assigned to the defective block in the normal area replaced by the spare block (replacement block). Is done.
[0490]
FIG. 5 also shows an arrangement structure in the table memory 12 of the block replacement management tables TB0, TB1,..., TBn corresponding to all the chips FM0, FM1,. In this example, the value of the least significant 10 bits of the physical address of the table memory 12 corresponds to the physical address of each block replacement management table TBi for one chip. Since the address of one table is given by [0000000000000] to [11111111111], when the start position of the table is 3C00h, 3FFFh is the end position.
[0500]
Note that the example of FIG. 4 shows a case where the logical addresses 4 and 5 are stored (registered) at the head position (table address 0) and the second position (table address 1) of the block replacement management table TBi, respectively. I have.
[0510]
This means that in the flash memory chip FMi, the blocks in the normal area to which the logical addresses 4 and 5 have been assigned, that is, both blocks of the physical addresses 4 and 5, are determined to be defective. It is shown that the spare block of the physical address 15360 in the chip FMi corresponding to the table address 0 is replaced by the spare block of the physical address 15361 in the chip FMi corresponding to the table address 1 and the defective block of the physical address 5 is replaced. means. With these block replacements, the logical addresses 4 and 5 have substantially shifted from the bad blocks (4 and 5) to the replacement blocks (15360 and 15361).
[0520]
Defective blocks in the flash memory can be detected not only by block quality inspection before chip shipment but also by a known method in actual memory access operation. The defect detected by the pass / fail inspection before the chip is shipped is a so-called congenital defect, and the defect during use is a so-called acquired defect. In the present invention, all the bad blocks are registered in the block replacement management table TB in the order of detection. In this case, as shown in FIG. 4, one logical address is registered for each table address in order from the top position of the table.
[0530]
When a birth defect block is recorded or listed in a predetermined redundant portion in each flash memory chip, the birth defect block is collectively registered in the block replacement management table TB based on the information in the list. Can be. If such a list cannot be obtained, the integrity of all blocks may be checked by initialization at the time of system construction to determine congenital bad blocks. Alternatively, the congenital bad block may be individually detected in actual memory access in the same manner as the acquired bad block, and registered in the block replacement management table TB each time.
[0540]
FIG. 6 and FIG. 7 show examples of the address calculation executed by the address conversion unit 42 in the present embodiment.
[0550]
In this embodiment, the address from the host 18 is given in the CHS mode. The CHS mode address includes a cylinder number (C), a head number (H), a sector number (S), the number of heads per cylinder (HpC), and the number of sectors per head (Cp) of a storage location to be specified. SpH) (data).
[0560]
As shown in FIG. 6, first, the address conversion unit 42 calculates the following expression (1) based on the input CHS mode address information (C, H, S, HpC, SpH), and calculates the logic of the corresponding value. Obtain a block address (LBA).
LBA = (C × HpC + H) SpH + S−1 (1)
[0570]
Next, the address conversion unit 42 calculates the following equations (2) and (3) from the logical block address (LBA) calculated as described above and the number of chip FMs included in the flash memory 14 (NumCHIP). The chip number (CHIP₋  NUM) and in-chip logical block number (LA)₋  BLK).
LA₋  BLK = LBA / NumCHIP (2)
CHIP₋  NUM = LBA mod NumCHIP (3)
[0580]
The above equations (2) and (3) are examples. If the storage area format of the flash memory chip FMi or the block changes, an arithmetic expression different from the above expressions (2) and (3) is used.
[0590]
Next, the operation of the present system with respect to the memory access for reading from the host 18 will be described with reference to FIGS. 8 and 9 show the processing procedure in the controller 10, and FIG. 10 shows the timing of the operation of each unit in the system.
[0600]
When data is read from the flash memory system, the host 18 specifies the read position (head position) with the CHS mode address information as described above. Also, the amount or range of the read data is designated by the sector count (SC), and a read command is sent.
[0610]
In the controller 10, the read command information (CHS, SC, command) from the host 18 received by the host interface unit 34 at the I / O port 46 is stored in a register in the logic control unit 44. Thereafter, the main sequencer 30 plays a central role in executing the following processing.
[0620]
First, an internal busy flag (BUSY) for the host provided in the logic control unit 44 is set (step A1).
[0630]
Next, the input address in the CHS mode stored in the CHS register 40 is converted into a logical address in the flash memory 14 by an operation shown in FIGS. 6 and 7 in the address conversion unit 42 (step A2). From the logical address obtained by this address conversion, the flash memory chip FMi to be subjected to the current read operation is determined.
[0640]
Next, the main sequencer 30 searches the block replacement management table TBi corresponding to the flash memory chip FMi, and determines whether the logical address specified by the host 18 is registered in the table TBi from the table head position. A search is performed in the order of addresses (steps A3 to A9).
[0650]
This search can be performed at high speed. When a NOR flash memory is used as the table memory 12 as in the present embodiment, the time required to search one row of the table can be suppressed to 100 nanoseconds or less.
[0660]
For example, it is assumed that the contents of the block replacement management table TBi are in a state as shown in FIG. 4, and the value of the logical address obtained by the address conversion is 2.
[0670]
In this case, the information read first (from the table top position) in the search of the block replacement management table TBi is “C004”, and the information does not match. Then, when the information of the second table storage position is read next, it is "C005", and this also does not match. Next, when the information of the third table position is read, it is "FFFFh", which indicates that the corresponding spare block (the block of the physical address 15361) is empty (unused). Therefore, it can be seen that "FFFFh" indicating the empty state is also stored in all the table storage positions thereafter.
[0680]
At this point, it has been found that the logical address 2 has not been registered in the block replacement management table TBi, and therefore the target flash memory read position is the block of the physical address 2 (step A6), and the table search is terminated. (Step A11), this logical address 2 is directly replaced with the physical address 2 of the access destination (step A12).
[0690]
Then, a block in the flash memory chip FMi specified by the physical address 2 is accessed through the flash I / F sequencer 32, and data is read from the accessed block (step A14). At this time, the data read from the flash memory 14 is temporarily stored in the data buffer 36 via the bus 22.
[0700]
As another example, assume that the value of the logical address obtained by the address conversion is 5. In this case, "C005" is read from the second table storage position in the above table search, and the logical address 5 matches and matches this block replacement information "C005" (step A5).
[0710]
At this point, the block of the physical address 5 in the normal area to which the logical address 5 has been assigned is defective, and the position of the physical block in the chip corresponding to the second storage location in the table TBi is It is found that the corresponding alternative block is replaced. Therefore, the table search is terminated (step A11), and a predetermined offset value As (15360) is added to the table address (1) where the collation matches, thereby obtaining the physical address (15361) in the chip to be accessed (step A11). A13).
[0720]
Then, a block of the flash memory chip FMi specified by the physical address (15361) is accessed through the flash I / F sequencer 32, and data is read from the block (step A14). Also in this case, the data read from the flash memory 14 is stored in the data buffer 36 via the bus 22.
[0730]
If there is no error in the data read from the flash memory 14 as described above, for example, if the status information sent from the flash memory 14 at the end of data reading does not indicate an error, normal reading was performed. Then, the read data in the data buffer 36 can be immediately transferred to the host 18. That is, the CPU clears the internal busy flag (BSY) and waits for the host 18 to capture the read data (step A28).
[0740]
Then, after the data transfer to the host 18 is completed, if the sector count (SC) given by the host 18 in the current memory access is 1, the reading for one block (one sector) is performed in the current memory access. The all read operation ends. However, when the sector count (SC) is 2 or more, the process returns to the beginning (step A30), and the read operation is executed in the same procedure as described above. However, the logical addresses after the second time are the values automatically updated (incremented) by the address conversion unit 42.
[0750]
FIG. 10A shows the operation timing of each unit when there is no error in the data of two sectors read from the flash memory 14.
[0760]
If there is an error in the data read from the flash memory 14, the processing of steps A16 to A25 in FIG. 9 is performed. The timing of the operation of each unit at this time is shown in FIG.
[0770]
Each flash memory chip FMi has a function of detecting whether an ECC error has occurred in data read from a memory array in the chip. If there is an error, the error is notified by the status information sent from the chip FMi to the flash I / F sequencer 32 at the end of the data reading.
[0780]
When the status information indicating the ECC error is notified, the storage contents of the block to be read this time are erased (step A16). In this erasing process, an address for specifying a block to be erased, an erase execution command, and the like are given from the flash I / F sequencer 32 via the bus 22 to the flash memory chip FMi. Then, a block erase operation is performed on the block in the chip FMi.
[0790]
In this embodiment, a block in which an ECC error has occurred at the time of reading as described above is identified as a defective block. The block determined to be defective may be a normal block belonging to the normal area in the flash memory chip FMi, or may be a spare block (substitute block) belonging to the spare area.
[0800]
If the block is in the spare area, the block replacement management table TBi performs a registration deletion process on the spare block (step A18). In this registration deletion processing, “0000h” is written in the table storage location corresponding to the spare block, and it is clearly indicated that the spare block is “bad”, that is, it is neither a substitute block nor a replaceable block. Ban. Thus, the registration of the spare block determined to be "bad" is deleted from the block replacement management table TBi.
[0810]
If the block determined to be defective this time is a block in the normal area, the deregistration processing (step A18) in the block replacement management table TBi as described above is unnecessary, and this processing is skipped (step A19). , An empty block search (step A20).
[0820]
In this empty block search, an empty spare block to be replaced with a block determined to be defective this time is searched for. More specifically, in the block replacement management table TBi, the table storage positions are sequentially accessed from the table head position, and the earliest (head) position where the empty information “FFFFh” is stored is searched for. Then, based on the found table position, the head block among the spare blocks that are still empty in the spare area is determined from the correspondence between the table address and the spare block physical address as described above.
[0830]
In the present embodiment, the respective processes (steps A18 and A20) of the spare block registration deletion and the empty block search in the block replacement management table TBi as described above are performed in parallel with the defective block erasing process (step A16) in the flash memory 14. It is possible to do.
[0840]
That is, since the table memory 12 where the block replacement management table TBi is located and the flash memory 14 where the bad block is located are connected to separate buses 26 and 22, the controller 10 controls the two memories 12 and 14 in parallel. To make the memories 12 and 14 perform the required memory operations in parallel or simultaneously.
[0850]
When an empty spare block to be a new substitute block is determined as described above, the spare block is erased (initialized), and then the data (flash memory 14) stored in the data buffer 36 is stored. The data read this time) is written to the spare block (step A21).
[0860]
This data writing process is nothing but a process of transferring data that has been accumulated in a block that has been determined to be defective this time to a spare block that is to be a new replacement block.
[0870]
This initialization erasing process is performed in the same manner as the erasing process for the defective block (step A16). When writing data to the spare block, the flash I / F sequencer 32 sends an address designating the spare block and a required command to write, and the data buffer 36 sends data to be written to the spare block. Each is sent to the corresponding flash memory chip FMi at a predetermined timing. Then, in the flash memory chip FMi, a write command is executed, and the data is written to the corresponding spare block.
[0880]
Whether the initialization and data writing in the spare block have been successfully performed or failed is confirmed based on the status information from the flash memory chip FMi in the same manner as described above (step A12). If the spare block has failed, the spare block is determined to be "bad" and the above series of processing (A18, A20, A21) for the spare block is repeated until a normal spare block usable as a new substitute block is obtained (step A23). ). At this time, in the block replacement management table TBi, “0000h” is written (deregistered) in order from the upper position of the table address.
[0890]
When a normal spare block that can be used as a new spare block is determined, the logical address (step A2) related to the current memory access is stored in the table storage position of the block replacement management table TBi corresponding to the spare block. The value is stored (registered) (step A24). This means that the logical address has been assigned to the new substitute block.
[0900]
Next, if the current read data error cannot be corrected, an error bit flag in the logic control unit 44 is set at this time (step A25). Next, the busy flag (BSY) is cleared (step A27), and the read data in the data buffer 36 can be transferred to the host 18 (step A28).
[0910]
Next, the operation of the present system with respect to the memory access for writing from the host 18 will be described with reference to FIGS. 11 to 13 show the processing procedure in the controller 10, and FIGS. 14 to 15 show the timing of the operation of each unit in the system.
[0920]
When writing data, the host 18 specifies the write position (head position) by the address information in the CHS mode, specifies the amount or length of the write data by the sector count (SC), and instructs by the write command. .
[0930]
The controller 10 stores the write command information (CHS, SC, command) from the host 18 received at the I / O port 46 in the host interface unit 34 in a register in the logic control unit 44. Thereafter, the main sequencer 30 plays a central role in executing the following processing.
[0940]
First, an internal busy flag (BUSY) in the logic control unit 44 is set (step B1).
[0950]
Next, the address conversion unit 42 performs an address conversion (operation) from the CHS mode address to the logical address in the flash memory (step B2).
[0960]
Next, the main sequencer 30 searches the block replacement management table TBi corresponding to the flash memory chip FMi in the same manner as in the above-described read operation, and stores the logical address specified by the host 18 in the table TBi. Whether or not the block is registered is searched in order of address from the table top position (steps B3 to B9), and the physical address of the block corresponding to the logical address is determined according to the search result.
[0970]
That is, when the logical address is registered in the table TBi, the physical address of the substitute block corresponding to the table address of the registered position is determined (step B13). If the logical address is not registered in the table TBi, a physical address having the same value as the logical address is determined (step B12).
[0980]
Next, the block in the flash memory chip FMi indicated by the determined physical address is erased (initialized). This initialization erasing process is performed in the same procedure as that for erasing a defective block in the above-described read operation (step A16).
[0990]
Then, the internal busy flag (BSY) is cleared to respond to the transfer of the write data from the host 18 (step B15), and the fact that the erase processing (step B14) has been successfully completed is notified from the flash memory chip FMi. Confirm with the status information (steps B16 and B17). Further, it is also confirmed that all the data from the host 18 has been loaded into the data buffer 36 (step B28).
[1000]
Then, after setting the internal busy flag (BSY) (step B29), data writing to the flash memory 14 is performed (step B30). This data write process is performed in the same procedure as the write process (step A21) for transferring data when a data error occurs in the read operation.
[1010]
That is, the relevant physical address and the write command are sent from the flash I / F sequencer 32, and the data to be written sent from the host 18 from the data buffer 36 are sent at a predetermined timing to the relevant flash memory chip. It is sent to FMi. In the flash memory chip FMi, a write command is executed, and the data is written to the corresponding block.
[1020]
Then, it is confirmed by the status information from the flash memory chip FMi that the writing has been successfully performed (step B31). When the sector count (SC) given by the host 18 is 1, the whole process is completed. When the sector count (SC) is 2 or more, the process returns to the beginning (step B42). Perform a read operation. However, the logical addresses after the second time have a value that is incremented by one in the address conversion unit 42.
[1030]
FIG. 14A shows the operation timing of each unit when data of two sectors from the host is written to the flash memory 14 without any error or failure.
[1040]
When the erasing process (step B14) for the corresponding block fails, the processes of steps B20 to B26 in FIG. 12 are performed. The timing of the operation of each unit at this time is shown in FIG.
[1050]
If there is an error in the erase process (step B14), the error is notified by the status information sent from the flash memory chip FMi to the flash I / F sequencer 32 after the end of the erase operation.
[1060]
In this embodiment, a block in which an erase error has occurred is identified as a bad block. The block determined to be defective may be a normal block belonging to the normal area in the flash memory chip FMi, or may be a spare block (substitute block) belonging to the spare area.
[1070]
If the block is in the spare area, the block replacement management table TBi performs a registration deletion process for the spare block (step B19). This deregistration process is performed in the same procedure as the deregistration process (step A18) in the read operation described above.
[1080]
If the block that has been determined to be defective this time is a block in the normal area, the table registration deletion process (step B19) is skipped (step B20), and an empty block search (step B20), as in the above-described read operation. Step B21) is performed.
[1090]
This empty block search process is also performed in the same procedure as the empty block search (step A20) in the above-described read operation, and the highest block among the empty spare blocks is determined.
[1100]
When an empty spare block to be used as a new substitute block is determined as described above, the spare block is erased in the same manner as above (step B22).
[1110]
If this erasure is successful, the spare block is recognized as a normal block that can be used as a new replacement block. If the erasure fails, this spare block is recognized as a bad block, and the above processing is performed until a normal spare block is found. Is repeated (step B24). This point is similar to the processing (steps A18 to A23) for determining a new substitute block in the above-described read operation.
[1120]
When a spare block that has been normally erased is hit, this spare block is registered as a replacement block. Therefore, in the block replacement management table TBi, the current memory is stored in the table position of the table address corresponding to the physical address of the spare block. The logical address specified by the access (step B2) is stored (step B25).
[1130]
Further, the access destination of the current data write is changed to the registered substitute block (step B26).
[1140]
When the data write processing to the flash memory 14 (step B30) fails, the processing of steps B32 to B38 in FIG. 13 is performed. FIG. 15 shows the operation timing of each unit at this time.
[1150]
If there is an error in the data write processing (step B30), the error is notified by the status information sent from the flash memory chip FMi after the end of the write operation.
[1160]
In this embodiment, a block in which data writing has failed is also identified as a bad block. Then, an alternative spare block to be replaced with the defective block is determined, and the spare block is accessed to write data from the host 18 at this time. This series of alternative processes (steps B32 to B38) are performed in the same procedure as the above-described alternative process (steps A17 to A24) when a data error occurs in the read operation.
[1170]
As a result, the data sent from the host 18 in the current memory access is written to the new spare spare block satisfying the above predetermined conditions. Then, the value of the logical address specified by the host 18 this time is stored (registered) in the table storage position of the block replacement management table TBi corresponding to the spare block (step B38), and this logical address is specified next time. When this is done, this new substitute block becomes the access destination.
[1180]
The procedures of the read operation and the write operation shown in the flowcharts of FIGS. 8, 9, and 11 to 13 correspond to the format of one block = 1 sector as shown in FIG. 3 for convenience of explanation. If one block includes a plurality of sectors, the process is not repeated from the beginning for each transfer of one sector, but all data for one block is stored in the data buffer 36, and the host interface unit 34 18 and the data transfer in units of one sector is repeated.
[1190]
As described above, in the flash memory system of this embodiment, the non-volatile table memory 12, which is preferably a NOR flash memory, is provided outside the flash memory 14 and on a separate bus 26. A block replacement management table TB as described above is constructed.
[1200]
Whenever the controller 10 (more specifically, the main sequencer 30) searches the table TB every time a memory access request is received from the host 18, a request for block replacement is made by comparing the contents of the table with a logical address specified by the host. The determination is automatically made, and the corresponding block to be accessed is found in a short time. The block at the access destination has a normal storage area at least at the time of the previous access, and it is highly probable that the block is also normal this time.
[1210]
According to the present embodiment, it is possible to avoid accessing a block known to be defective from the beginning. As a result, harmful stress on the flash memory due to access to the defective array region can be reduced as much as possible.
[1220]
If the access destination block is defective, a substitute block to be replaced with the defective block is determined appropriately and promptly while referring to the block substitution management table TB. The contents of the table TB are also updated (rewritten) as appropriate following the substitution.
[1230]
As described above, in the flash memory system, since the block replacement information is centrally managed on the block replacement management table TB, highly efficient block replacement management can be realized. In particular, only the logical address relating to the normal block determined to be defective need be registered in the table TB, and it is not necessary to register a special pointer for indicating a substitute block. Therefore, the table capacity is small, and it is possible to sufficiently cope with an increase in the capacity of the flash memory.
[1240]
Further, since the block replacement information is held in the block replacement management table TB irrespective of whether the power is turned on or off, no processing or time is required for forming the table in the system initialization performed immediately after the power is turned on. It is.
[1250]
Further, in this embodiment, the table memory 12 for providing the block replacement management table TB and the flash memory 14 for providing a memory space for storing data are connected to different buses 26 and 22, respectively. Can be executed independently of the operation on the flash memory 14 side, and block replacement management can be efficiently developed.
[1260]
However, the above-described embodiment is merely an example, and various applications and modifications of the block replacement management system in the present invention, particularly various functions related to the block replacement management table TB, are possible.
[1270]
For example, in the above-described embodiment, upon receiving a memory access request from the host 18, the controller 10 (main sequencer 30) immediately (unconditionally) searches the block replacement management table TBi. However, there is also a method of first accessing the block of the logical address specified by the host as it is, and referring to the block replacement management table TB when it is confirmed from the block related information of the redundant part that the block is defective. It is possible. Even in this case, the corresponding replacement block can be accessed through the block replacement management table TB.
[1280]
The block replacement management table TB is always updated in the form of writing data such as a logical address and a defective flag. Except for the free information (FFFFh) written to all table positions when the table is initialized, once written data is not erased. In that sense, as the nonvolatile memory used for the block replacement management table TB as in the above embodiment, the AND-type flash memory is advantageous in terms of function and cost.
[1290]
However, other types of non-volatile memory such as EEPROM and FRAM can be used. It is needless to say that the non-volatile semiconductor memory used for the table memory 12 can also store tables for various applications, various set values, firmware, and the like.
[1300]
Alternatively, it is possible to provide a block replacement management table TBi in a redundant area in each flash memory chip FMi. In this case, the processing in the table and the original memory operation in the chip conflict with each other, so that special time-sharing control is required.
[1310]
In the above embodiment, the same number of table addresses (physical addresses) as the number of blocks or addresses of the spare area in the flash memory chip is set in the block replacement management table TB, and each table address has a one-to-one correspondence. It is associated with the physical address of any one of the spare blocks. The table address and the spare block physical address having the same arrangement order in the spare area and the table area respectively correspond to each other. When a certain offset value AS is added to each table address, the spare address corresponding to the table address is obtained. There was a relationship that a block physical address could be obtained.
[1320]
However, the number of blocks or addresses in the spare area and the number of table addresses need not necessarily be the same. The offset As can be set arbitrarily and does not have to be a constant value. What is important is that there is a one-to-one correspondence between the two, and the correspondence is managed.
[1330]
Further, the search direction or the search order in the block replacement management table can be arbitrarily determined.
[1340]
The configuration of the flash disk system in the above embodiment, particularly the configuration or layout inside the controller, is merely an example, and various modifications are possible. In the above embodiment, the form of the address given by the host (CHS mode) is also an example, and the host may give a logical address in the flash memory from the beginning, or may give an address in another mode. A host or host interface having various configurations or functions can be used.
[1350]
【The invention's effect】
As described above, according to the flash memory system of the present invention, highly reliable and reliable block replacement management can be performed with a small amount of resources.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a flash memory system according to one embodiment of the present invention.
FIG. 2 is a block diagram illustrating a functional configuration inside a controller according to the embodiment.
FIG. 3 is a diagram illustrating an example of a format of a storage area in a block in the flash memory according to the embodiment;
FIG. 4 is a diagram showing an example of a storage area format in a flash memory chip and a configuration example of a block replacement management table in the embodiment.
FIG. 5 is a diagram illustrating an example of a data format of block replacement information in the embodiment.
FIG. 6 is a diagram illustrating an example of an address operation performed by an address operation unit according to the embodiment.
FIG. 7 is a diagram illustrating an example of an address operation performed by an address operation unit according to the embodiment;
FIG. 8 is a flowchart illustrating a processing procedure of a read operation in the embodiment.
FIG. 9 is a flowchart illustrating a processing procedure of a read operation in the embodiment.
FIG. 10 is a diagram showing operation timings of respective units in a read operation of the embodiment.
FIG. 11 is a flowchart illustrating a processing procedure of a write operation in the embodiment.
FIG. 12 is a flowchart illustrating a processing procedure of a write operation in the embodiment.
FIG. 13 is a flowchart illustrating a processing procedure of a write operation in the embodiment.
FIG. 14 is a diagram showing operation timings of respective units in a write operation according to the embodiment.
FIG. 15 is a diagram illustrating operation timings of respective units in a write operation according to the embodiment.
[Explanation of symbols]
10 Controller
12 Table memory
14 Flash memory
18 Host computer
22, 26 bus
30 Main sequencer
32 Flash I / F sequencer
34 Host interface section
36 data buffer
38 Buffer control unit
42 Address conversion unit

Claims (9)

A flash memory configured to divide a storage area into a plurality of blocks and to erase stored data in block units;
A block replacement information registration memory for retrievably registering an address assigned to a block determined to be defective in the flash memory, and for providing a replacement address indicating a storage position of a replacement block to be used instead of the bad block. When,
Inputting an address given for memory access to the flash memory, and accessing the block in the flash memory indicated by the input address when the input address is not registered in the block replacement information registration memory ; A memory control unit that accesses a block in the flash memory specified by the substitute address corresponding to the input address when an input address is registered in the block substitute information registration memory ;
The memory control unit is connected to the flash memory via a first bus, the memory control unit is connected to the block replacement information registration memory via a second bus, and the memory control unit via the first bus. And a flash memory system in which an operation between the flash memory and the flash memory and an operation between the memory control unit and the block replacement information registration memory via the second bus are performed independently . A flash memory configured to divide a storage area into a plurality of blocks and to erase stored data in block units;
A block replacement that registers a logical address assigned to a block determined to be defective in the flash memory in a searchable manner, and gives a physical address assigned to a substitute block to be used instead of each defective block as a substitute address. Information registration memory ,
An address given for memory access to the flash memory is input, and the input address is converted to a logical address in the flash memory. If the logical address is not registered in the block replacement information registration memory , the logical address in accessing the block in the flash memory indicated, the logical address is the block replacement information blocks in the flash memory when the registration memory has been registered to be instructed by the alternate address corresponding to the logical address A memory control unit for accessing the
The memory control unit is connected to the flash memory via a first bus, the memory control unit is connected to the block replacement information registration memory via a second bus, and the memory control unit via the first bus. And a flash memory system in which an operation between the flash memory and the flash memory and an operation between the memory control unit and the block replacement information registration memory via the second bus are performed independently . When the accessed block is determined to be a defective block, the memory control unit accesses the flash memory and the block replacement information registration memory in parallel via the first and second buses, respectively. 3. The method according to claim 1, wherein an erasing process for erasing the storage content of the defective block in the flash memory and a process for searching and updating the registration information in the block replacement information registration memory are performed in parallel. Flash memory system. The block replacement information registration memory has a plurality of storage locations corresponding one-to-one with a plurality of spare blocks set as replacement blocks in the flash memory, and one of the spare blocks is used as a replacement block. 3. The nonvolatile memory device according to claim 1, further comprising a nonvolatile storage unit configured to store, when being used, address information indicating an address assigned to a defective block replaced by the defective block in the storage location corresponding to the spare block. A flash memory system as described . 5. The flash memory system according to claim 4, wherein each of said storage locations stores first status information indicating an empty state when said spare block corresponding thereto is not used as a substitute block. 6. The flash memory system according to claim 4 , wherein each storage location stores second status information indicating whether the corresponding spare block is normal or defective . 5. The block replacement information registration memory includes address generation means for obtaining an address of a replacement block replacing each of the defective blocks based on an address of the storage location where address information corresponding to the defective block is stored. 3. A flash memory system according to claim 1. 8. The method according to claim 7, wherein the address generation means obtains an address of a substitute block replacing the defective block by adding a predetermined offset value to an address of the storage location where address information corresponding to the defective block is stored. A flash memory system as described. 8. The flash memory system according to claim 4, wherein said nonvolatile storage means comprises a NOR type flash memory .

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