JP3583458B2 - Hall element - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a so-called horizontal Hall element for applying a magnetic field in a direction perpendicular to a semiconductor surface.
[0002]
[Prior art]
FIG. 7 is a diagram showing a configuration of a conventional general Hall element, in which current supply electrodes C ₁ and C ₂ are provided on one opposed side surface 1 a of the semiconductor 1, respectively, and the other opposed side surface 1 b is provided. , 1b are provided with sensor electrodes S ₁ , S ₂ , respectively, to form a Hall element. The magnetic field B is applied in a direction perpendicular to the main surface 1c of the semiconductor 1.
[0003]
In the above-described Hall element, in order to obtain a Hall voltage, the ratio L / W of the distance L between the current supply electrodes C ₁ and C ₂ and the distance W between the sensor electrodes S ₁ and S ₂ is required. It needs to be large to some extent. In addition, the sensitivity becomes highest when the sensor electrodes S ₁ and S ₂ are located substantially in the middle between the current supply electrodes C ₁ and C ₂ , respectively. On the other hand, factors that determine the performance of the Hall element include an offset voltage generated when no magnetic field is applied, in addition to the sensitivity. The geometric offset voltage is caused by the displacement of the sensor electrodes S ₁ and S ₂ . In addition, the stress acting on the semiconductor 1 causes a change in electron mobility due to the piezo effect. This also causes an offset voltage. Since such an offset voltage causes an error when the Hall element is used, for example, as a watt-hour meter, various measures have been taken to reduce the offset voltage.
[0004]
For example, JP-A-63-55227, as shown in FIG. 8, thereby forming a n-type semiconductor layer surface three current supply electrode _C 1 of 2, _{C 2,} these current supply electrodes _C 1, A so-called vertical Hall element is described in which sensor electrodes S ₁ and S ₂ are formed in the middle between C ₂ , respectively, and the current I has a distribution extending in a direction perpendicular to the surface of the n-type semiconductor layer 2. Have been. The magnetic field B is applied horizontally to the surface of the n-type semiconductor layer 2.
[0005]
According to such a vertical Hall element, since stress due to crystal defects and the like is concentrated near the surface of the n-type semiconductor layer 2, by distributing the current I in a direction perpendicular to the surface, the piezo effect is generated. The offset voltage can be reduced. In the vertical Hall element, terminals can be formed only on the surface of the n-type semiconductor layer 2, and the planar technology, which is a method for manufacturing an integrated circuit, can be used. Can be planned.
[0006]
However, in the above-described vertical Hall element, in order to reduce the offset voltage and to improve the sensitivity by increasing the L / W ratio, the current I from the current supply electrode 3 is applied to the n-type semiconductor layer 2. Since it is necessary to make the current flow as perpendicular to the surface as possible, the size of the current supply electrode C must be increased. On the other hand, since there is a limit in flowing the current I deep in the n-type semiconductor layer 2, the distance between the current supply electrodes 3 must be increased to some extent in order to increase the L / W ratio. For these reasons, the above-described vertical Hall element has a drawback that the element shape is easily increased in size, and there is a limit in reducing the offset voltage and the like. Further, in the above-described vertical Hall element, since the magnetic field B must be applied horizontally to the surface of the n-type semiconductor layer 2, the Hall element is provided in the opening of the magnetic field applying means such as a ferromagnetic core. In this case, it was difficult to reduce the gap between the openings. Since the Hall voltage is obtained in inverse proportion to the gap interval between the openings, the vertical Hall element also has a problem that it is difficult to improve the element sensitivity from this point.
[0007]
[Problems to be solved by the invention]
As described above, the vertical Hall element to which the conventional planar technology is applied is configured so that the current I flows in a direction perpendicular to the surface of the semiconductor layer. It is difficult to reduce the offset voltage and improve the device sensitivity based on the L / W ratio, and the magnetic field B must be applied horizontally to the surface of the semiconductor layer. Therefore, there is a problem that it is difficult to improve the device sensitivity from this point. Further, there has been a problem that a measure against the geometric offset voltage has not been sufficiently taken.
[0008]
The present invention has been made in order to address such a problem, and provides a Hall element capable of improving the element sensitivity by enabling a magnetic field to be applied in a direction perpendicular to a semiconductor surface. It is another object of the present invention to provide a Hall element capable of easily achieving a reduction in offset voltage and an improvement in element sensitivity based on an L / W ratio while reducing the size of the element.
[0009]
[Means for Solving the Problems]
That is, the first Hall element in the present invention is a semiconductor substrate, a first conductive type semiconductor layer provided on the semiconductor substrate and having an upper surface and side surfaces, and an insulating layer having side surfaces in contact with the side surfaces of the semiconductor layer. A first current supply electrode portion of a first conductivity type disposed adjacent to a side surface of the insulating portion in contact with the semiconductor layer; and a first conductive electrode disposed adjacent to a side surface of the insulating portion in contact with the semiconductor layer. comprising a second current supply electrode portions of the pair of dies, and said insulating portion of said semiconductor layer in contact sides and a pair of sensor electrodes of the Hall voltage measurement of the first conductivity type disposed adjacent said The first current supply electrode portion is disposed between the pair of sensor electrode portions, and the first current supply electrode portion and the pair of sensor electrode portions are disposed between the pair of second current supply electrode portions. Hall element arranged in the When the current flows between the first and second current supply electrode portions, is characterized in that it comprises a means for inducing a Hall voltage between the sensor electrode unit by a magnetic field in a direction perpendicular to the current .
[0010]
The second Hall element is provided on the semiconductor substrate, the first conductivity type semiconductor layer provided on the semiconductor substrate and having an upper surface and side surfaces, and is in contact with a side surface of the semiconductor layer. An insulating portion having a side surface perpendicular to the insulating portion, a first current supply portion of a first conductivity type provided in the semiconductor layer so as to be disposed adjacent to the side surface of the insulating portion; A pair of second current supply units of the first conductivity type provided in the semiconductor layer so as to be disposed adjacent to the side surface of the semiconductor device, and to be disposed adjacent to the side surface of the insulating unit. during the and a first conductivity type of the pair of sensor portions provided in the semiconductor layer, the pair of sensor portions that current flows between the first and second current supply portions, the semiconductor Hall voltage between the sensor portion by the vertical magnetic flux to the upper surface of the layer It is characterized in that it is arranged to be caused.
[0012]
[Action]
In the first Hall element of the present invention, the current supply electrode portion and the sensor electrode portion are formed along the insulating portion surrounding at least the side surface portion of the active layer (semiconductor layer). The magnetic field flows in a direction horizontal to the surface of the layer, so that a magnetic field can be applied in a direction perpendicular to the surface of the active layer. Therefore, the gap interval between the openings of the magnetic field applying means can be reduced, and the element sensitivity can be improved.
[0013]
Further, in the second Hall element, since the current supply electrode portion and the sensor electrode portion are provided in the depth direction of the active layer (semiconductor layer) , the current in the direction parallel to the surface of the active layer is applied to the active layer. Can be uniformly flowed to the deep part of the surface. Accordingly, in addition to the improvement of the device sensitivity similar to the first Hall device, the current does not flow through the surface of the active layer, so that the piezoresistance caused by stress such as crystal defects can be reduced, thereby reducing the piezo effect. , It is possible to reduce the offset voltage.
[0014]
Furthermore, by curving the current flow in the direction parallel to the surface of the active layer, the current path can be easily lengthened without changing the distance between the electrodes. Therefore, the L / W ratio can be adjusted without changing the size of the element, and the sensitivity of the element can be improved. Further, with respect to the geometric offset voltage, the offset voltage due to the asymmetry of the electrode position can be easily offset by changing the current flow path and changing the resistance.
[0015]
【Example】
Hereinafter, examples of the present invention will be described.
[0016]
FIG. 1 is a diagram schematically showing a structure of a Hall element according to a first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a p-type semiconductor substrate, on which an active layer 13 made of an n-type semiconductor is provided via an intermediate insulating layer 12, for example, an insulating oxide layer. As a semiconductor substrate provided with an active layer via such an intermediate insulating layer, for example, an SOI (Silicon on Insulator) substrate can be used. Then, by using the semiconductor substrate 11 having the intermediate insulating layer 12, the flow path of the current can be restricted, and the element can be electrically insulated from other elements. When the active layer 13 is made of a semiconductor having a conductivity type opposite to the conductivity type of the semiconductor substrate 11 as described above, the intermediate insulating layer 12 can be omitted. The same effect as in the case of using is obtained.
[0017]
The periphery including the side surface of the active layer 13 is surrounded by a first trench 14 in which an insulating oxide is embedded, and a central portion of the active layer 13 is a second trench in which the insulating oxide is embedded. A trench 15 is provided. That is, the active layer 13 is divided by the second trench 15, and the two active layers 13 a and 13 b substantially surrounded in the lateral direction by the first and second trenches 14 and 15 are formed by the second trench 15. It is provided with the trench 15 interposed.
[0018]
On both sides of the central second trench 15, three current supply electrode portions 16a, 16b and 16c are formed along the second trench 15, respectively. The current I flows through the supply electrode portions 16b and 16c. Then, these current supply electrode portions 16a, 16b, between 16c, that is, between the electrode portions 16a and 16b and between the electrode portions 16 a and 16c, the sensor electrode unit along the second trenches 15 in the substantially middle 17a, 17 b are formed respectively. Each of the current supply electrode portion 16 and the sensor electrode portion 17 diffuses in the depth direction of the active layer 13 so as to reach the intermediate insulating layer 12 from the electrode 18 provided on the surface of the active layer 13. And a high-concentration n-type contact region 19 formed.
[0019]
Further, between the current supply electrode section 16 and the sensor electrode section 17, current control electrode sections 20a and 20b are provided along both sides of the second trench 15, respectively. These current control electrode portions 20 include an electrode 21 provided on the surface of the active layer 13 and a p-type contact formed by diffusion in the depth direction of the active layer 13 so as to reach the intermediate insulating layer 12 from the electrode 21. And an area 22. Further, a gate electrode 24 is formed on the surface of the active layer 13 via a gate oxide film 23 except for the regions where the electrodes 18 and 21 are formed. The Hall element 25 is configured.
[0020]
In the Hall element 25 of this embodiment, a magnetic field B is applied in a direction perpendicular to the surface of the active layer 13. That is, the Hall element 25 of this embodiment is a so-called horizontal Hall element. FIG. 1A is a plan view excluding the gate oxide film 23 and the gate electrode 24, and the same applies to the drawings showing other embodiments described below.
[0021]
In the Hall element 25 of the above structure, since the high-concentration n-type contact region 19 of the current supply electrode 16 and the sensor electrode unit 17 is provided so as to respectively reach the intermediate insulating layer 12, and the surface of the active layer 13 The currents I ₁ and I ₂ that are curved in the horizontal direction can be uniformly flowed to the deep portion of the active layer 13. A gate electrode 24 is provided on the surface of the active layer 13 via a gate oxide film 23 to prevent the current I from flowing near the surface of the active layer 13. Accordingly, the piezoresistance generated due to the stress due to the crystal defect or the like near the surface of the active layer 13 can be reduced, so that the offset voltage can be reduced.
[0022]
A similar effect can be obtained by providing a p-type semiconductor layer near the surface of active layer 13 instead of gate oxide film 23 and gate electrode 24.
[0023]
Further, since the current control electrode portion 20 has a p-type contact region 22 having a conductivity type opposite to that of the active layer 13, the current supply electrode portion 16, and the high-concentration contact region 19 of the sensor electrode portion 17, The currents I ₁ and I ₂ flowing between the current supply electrode portions 16 flow around the p-type contact region 22. For this reason, the flow path length L of the currents I ₁ and I ₂ can be set long without changing the distance between the current supply electrode portions 16. Therefore, it is possible to improve the device sensitivity by adjusting the L / W ratio without changing the size of the device.
[0024]
Further, current control electrode section 20a, by applying a reverse bias between 20b, by changing the current flow path I ₁ and the current I _2, the resistance can be changed easily. Accordingly, the offset voltage due to the asymmetry of the positions of the sensor electrode portions 17a and 17b can be offset.
[0025]
Next, a second embodiment of the Hall element of the present invention will be described with reference to FIG. In the Hall element 26 of this embodiment, the current supply electrode portions 16 are provided along a pair of opposing sides of the trench 14 provided with the insulating oxide and provided around the active layer 13 made of the n-type semiconductor. , A sensor electrode section 17 and a current control electrode section 20 are formed. The other configurations are the same as those of the first embodiment except that the current control electrode portion 20 is formed between the current supply electrode portions 16b and 16c and the sensor electrode portions 17a and 17b on both sides. It has the same structure.
[0026]
In the Hall element 26 having such a configuration, in addition to the effect of the first embodiment, since the current supply electrode sections 16 are disposed facing each other, the offset voltage generated due to the geometric symmetry can be canceled. Becomes possible.
[0027]
Next, a third embodiment of the Hall element of the present invention will be described with reference to FIG. As in the second embodiment, the Hall element 27 of this embodiment includes a current supply electrode along a pair of opposing sides of a trench 14 provided around an active layer 13 made of an n-type semiconductor. The portion 16, the sensor electrode portion 17, and the current control electrode portion 20 are formed respectively, and the area thereof is large so that the p-type contact region 22 of the conductivity type opposite to that of the active layer 13 projects in the center direction. Is set. Further, the high-concentration n-type contact region 19 of the sensor electrode portion 17 has the same shape as the p-type contact region 22 of the current control electrode portion 20. The other structure is the same as that of the first embodiment.
[0028]
In the Hall element 27 of this embodiment, since the area of the p-type contact region 22 is set large, the currents I ₁ and I ₂ flow largely bypassing the p-type contact region 22. Therefore, in addition to the effects of the first and second embodiments, the L / W ratio can be set larger, and the element sensitivity can be further improved.
[0029]
Next, a fourth embodiment of the Hall element of the present invention will be described with reference to FIG. The Hall element 28 of this embodiment includes a current supply electrode section 16, a sensor electrode section 17, and a current control electrode section along each side of a trench 14 provided around an active layer 13 made of an n-type semiconductor. 20 are formed. The other structure is the same as that of the third embodiment.
[0030]
Here, when the crystal orientation of silicon to be the active layer 13 is the (100) plane, the piezo resistance changes at a cycle of 90 °. By arranging the current supply electrode portions 16a, 16b, 16c while rotating them by 90 °, the piezoresistors can be canceled each other. Thus, the offset voltage can be significantly reduced.
[0031]
FIG. 5 is a view showing a modification of the fourth embodiment. In the Hall element 29 shown in FIG. 5, a part of the current I forms a 1/4 arc with one corner of the trench 14 interposed therebetween. As shown, the current supply electrode section 16 is provided. Also in the Hall element 29 having such a configuration, the piezo resistances can be canceled each other, and the offset voltage can be greatly reduced.
[0032]
Each of the Hall elements 25, 26, 27, 28, and 29 in each of the above-described embodiments can be manufactured by applying the planar technology, which is a method of manufacturing an integrated circuit. For example, when using an SOI substrate, a trench 14 is formed so as to surround the active layer 13, and an insulating oxide is buried in the trench 14 to form an insulating layer. Next, a desired impurity is diffused into the active layer 13 according to the shape of each of the contact regions 19 and 22, and then a step of forming the electrodes 18 and 21 and a step of forming the gate oxide film 23 and the gate electrode 24 are performed. The same applies when the active layer 13 is formed by epitaxially growing an n-type semiconductor layer on the p-type semiconductor substrate 11.
[0033]
FIG. 6 is a diagram showing a configuration example when the Hall elements (25, 26, 27, 28, 29) according to the above-described embodiments are used as a watt-hour meter. In the figure, reference numeral 31 denotes a ferromagnetic core, and an opening 31a is provided in a part of the ferromagnetic core 31. The Hall element 32 is installed horizontally in the opening 31 a of the ferromagnetic core 31. A lamp wire 33 is wound around the ferromagnetic core 31. When a current flows through the lamp wire 33, a magnetic field proportional to the current is formed in the opening 31a.
[0034]
Here, the Hall voltage is inversely proportional to the distance (gap interval) t of the opening 31a of the ferromagnetic core 31. Each of the Hall elements according to the above-described embodiments is a horizontal Hall element in which a magnetic field can be applied in a direction perpendicular to the surface of the semiconductor substrate 11 (active layer 13). In comparison, the gap interval t can be reduced. Therefore, the Hall voltage, that is, the element sensitivity can be improved.
[0035]
【The invention's effect】
As described above, according to the first Hall element of the present invention, since it is possible to apply a magnetic field in a direction perpendicular to the semiconductor surface, the element sensitivity can be improved by increasing the magnetic field strength. Can be. According to the second Hall element, in addition to the above effects, it is possible to reduce the offset voltage and easily improve the element sensitivity based on the L / W ratio while reducing the element size. It becomes.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams schematically showing a structure of a horizontal Hall element according to a first embodiment of the present invention, wherein FIG. 1A is a front view with a partial configuration omitted, and FIG. Is a cross-sectional view taken along the line BB 'of FIG.
FIGS. 2A and 2B are diagrams schematically showing a structure of a horizontal Hall element according to a second embodiment of the present invention, wherein FIG. 2A is a front view with a partial configuration omitted, and FIG. FIG.
FIGS. 3A and 3B are diagrams schematically showing the structure of a horizontal Hall element according to a third embodiment of the present invention, wherein FIG. 3A is a front view with a partial configuration omitted, and FIG. FIG.
FIGS. 4A and 4B are diagrams schematically showing a structure of a horizontal Hall element according to a fourth embodiment of the present invention, wherein FIG. 4A is a front view with a partial configuration omitted, and FIG. FIG.
FIG. 5 is a diagram showing a modification of the fourth embodiment shown in FIG.
FIG. 6 is a diagram showing a configuration example of a watt hour meter using a horizontal Hall element according to the present invention.
FIG. 7 is a cross-sectional view showing a configuration of a conventional general Hall element.
FIG. 8 is a view schematically showing the structure of a conventional vertical Hall element.
[Explanation of symbols]
11 p-type semiconductor substrate 12 intermediate insulating oxide layer 13 n-type semiconductor active layers 14 and 15 trenches 16a, 16b and 16c in which insulating oxide is buried current supply electrode portions 17a and 17b ... Sensor electrode portions 18 and 21... Electrode 19... High-concentration n-type contact regions 20 a and 20 b... Current control electrode portions 22... P-type contact regions 25, 26, 27, 28, 29 and 31. Hall element

Claims (9)

A semiconductor substrate;
A first conductivity type semiconductor layer provided on the semiconductor substrate and having an upper surface and side surfaces;
An insulating portion having a side surface in contact with the side surface of the semiconductor layer,
A first conductivity type first current supply electrode portion disposed adjacent to a side surface of the insulating portion in contact with the semiconductor layer;
A pair of first conductivity type second current supply electrode portions disposed adjacent to a side surface of the insulating portion in contact with the semiconductor layer;
A first conductive type Hall voltage measurement pair of sensor electrodes disposed adjacent to a side surface of the insulating portion that contacts the semiconductor layer,
The first current supply electrode portion is disposed between the pair of sensor electrode portions, and the first current supply electrode portion and the pair of sensor electrode portions are formed of the pair of second current supply electrode portions. A Hall element disposed therebetween,
When a current flows between the first and second current supply electrode portions, a means for inducing a Hall voltage between the sensor electrode portions by a magnetic field in a direction perpendicular to the current is provided. Hall element. The Hall element according to claim 1,
A Hall element, further comprising an intermediate insulating layer provided between the semiconductor layer and the semiconductor substrate, wherein the intermediate insulating layer is in contact with the insulating portion. The Hall element according to claim 2,
The Hall element, wherein the first and second current supply electrode portions and the sensor electrode portion are in contact with the intermediate insulating layer. The Hall element according to any one of claims 1 to 3,
A Hall element comprising: a gate insulating film formed on the semiconductor layer; and a gate electrode formed on the gate insulating film. The Hall element according to claim 1,
The semiconductor layer is separated into two sections by the insulating section, and a set of the first and second current supply electrode sections and the sensor electrode section are arranged in the semiconductor layer in each section. A Hall element characterized by the above-mentioned. The Hall element according to any one of claims 1 to 5,
Further, the first to increase the length of the current flow path between the second current supply electrode portions and the current supply electrode portion, the first current supply electrode portion and the second current A Hall element comprising a current control means between the Hall element and a supply electrode unit. The Hall element according to claim 6,
Hall element and the current control means, characterized in that it comprises a current control electrode of the second conductivity type provided between said second current supply electrode portion and the first current supply electrode portion. A semiconductor substrate;
A first conductivity type semiconductor layer provided on the semiconductor substrate and having an upper surface and side surfaces;
An insulating portion that is in contact with the side surface of the semiconductor layer and has a side surface perpendicular to the surface of the semiconductor substrate;
A first current supply unit of a first conductivity type provided in the semiconductor layer so as to be disposed adjacent to the side surface of the insulating unit;
A pair of first conductivity type second current supply units provided in the semiconductor layer so as to be arranged adjacent to the side surface of the insulating unit;
A pair of first conductivity type sensor units provided in the semiconductor layer so as to be disposed adjacent to the side surface of the insulating unit,
The pair of sensor units may be configured such that a Hall voltage is induced between the sensor units by a magnetic flux perpendicular to an upper surface of the semiconductor layer while a current flows between the first and second current supply units. A Hall element, wherein the Hall element is arranged in a hall. A semiconductor substrate having an insulating surface;
A first conductivity type semiconductor layer disposed on an insulating surface of the semiconductor substrate and having an upper surface and side surfaces;
An insulating portion having a side surface in contact with the side surface of the semiconductor layer,
First and second current supply units of the first conductivity type disposed adjacent to each other on the side surface of the semiconductor layer so that current can flow therebetween;
A pair of first conductivity type sensor units disposed adjacent to side surfaces of the semiconductor layer,
The Hall element, wherein the pair of sensor units are arranged such that a Hall voltage due to a magnetic flux perpendicular to an upper surface of the semiconductor layer is induced between the sensor units.

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