JP3224872B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a BiCMOS transistor in which a secondary breakdown phenomenon is prevented from occurring.

[0002]

2. Description of the Related Art FIG. 16 is a sectional view showing a conventional BiCMOS type semiconductor device. On the surface of P-type silicon substrate 1, a bipolar transistor region 10 and a CMOS transistor region (not shown) are provided. In the bipolar transistor region 10, buried N ⁺ A diffusion layer 2 is provided, and the buried N ⁺ An N-type epitaxial layer 3 is provided on diffusion layer 2 and P-type silicon substrate 1. On the surface of the N-type epitaxial layer 3, first to third field oxide films 4a to 4c are provided. The N-type epitaxial layer 3 has the first and second field oxide films 4a and 4a.
b and the embedded N ⁺ De located on the diffusion layer 2
epN ⁺ Layer 5 is provided and the DeepN ⁺ Layer 5 has N ⁺ as a base region contact. A diffusion layer 6 is provided. The N-type epitaxial layer 3 has first and second P ⁺ portions of a collector region located between the second and third field oxide films 4b and 4c. Type diffusion layers 7 and 8 and P ⁺ A mold diffusion layer 9 is formed. These P ⁺ The type diffusion layers 7, 8, and 9 are shallow diffusion layers.

The diffusion layers 6, 7, 8, and 9 in the conventional BiCMOS transistor are formed by implanting impurities into the N-type epitaxial layer 3 and then performing a heat treatment for diffusing the impurities. On this occasion,
If the BiCMOS transistor is sufficiently miniaturized, only a shallow diffusion layer can be formed as a source / drain region diffusion layer of the CMOS transistor. This is because the gate length of the CMOS transistor is shortened because the BiCMOS transistor is sufficiently miniaturized, and the diffusion speed of impurities is substantially constant in any direction. . That is, if a deep diffusion layer is formed in the source / drain region, the diffusion layer in the source region is connected to the diffusion layer in the drain region. Therefore, only a shallow diffusion layer is formed in the source / drain region. It cannot be formed. At the same time, the P ⁺ Type diffusion layers 7, 8, 9
It is formed using the same step as the step of forming the diffusion layer of the drain region, that is, the step of implanting impurities and performing a heat treatment for diffusing the impurities. Therefore, the P ⁺ The type diffusion layers 7, 8, 9 can also form only shallow diffusion layers.

FIG. 17 is a sectional view showing the flow of holes and electrons between the emitter region and the collector region in the bipolar transistor shown in FIG. Arrow 11
Indicates the flow of holes. That is, holes are
P ^{+ of} emitter region The N-type epitaxial layer 3 enters the N-type epitaxial layer 3 from the edge portion 9a of the N-type diffusion layer 9, and the first P ⁺ Some may enter the edge portion 7a of the mold diffusion layer 7. Also, the P ⁺ The N-type epitaxial layer 3 enters the N-type epitaxial layer 3 from the edge portion 9b of the N-type diffusion layer 9, and the second P ⁺ Some may enter the edge portion 8a of the mold diffusion layer 8.

The arrow 12 indicates the flow of electrons. That is, the electrons are supplied to the P ^{+ of} the first collector region. The N-type epitaxial layer 3 enters the N-type epitaxial layer 3 from the edge 7a of the N-type diffusion layer 7, and the N-type epitaxial layer 3
⁺ Some may enter the edge 9 a of the mold diffusion layer 9. Also,
P ^{+ of} the second collector region The N-type epitaxial layer 3 enters the N-type epitaxial layer 3 from the edge portion 8a of the N-type diffusion layer 8, and the P ⁺ Some may enter the edge portion 9b of the mold diffusion layer 9.

[0006]

By the way, the above conventional art
Holes and electrons flow in bipolar transistors
As shown in FIG. 17, the portion to be
1, the second P⁺ -Type diffusion layers 7 and 8 and P of emitter region
⁺ Edge portions 7a, 8a, 9a, 9 of respective mold diffusion layers 9
b. The P⁺ Type diffusion layers 7 to 9 are shallow diffusion layers
Therefore, the radius of curvature of the edge portions 7a, 8a, 9a, 9b
Is getting smaller. As a result, the bipolar transistor
When a large current flows during the operation of the star, holes and electrons
Intensively passes through the edge portions 7a, 8a, 9a, 9b
I do. Therefore, the emitter region P⁺ Edge of the diffusion layer 9
The secondary breakdown phenomenon may occur due to heat generation at the joints 9a and 9b.
is there. This secondary breakdown phenomenon is the primary breakdown due to the avalanche phenomenon.
When the current is further increased from the surface area,
It suddenly changes to the low resistance state, and the transistor characteristics deteriorate.
Or destruction.

The present invention has been made in view of the above circumstances, and an object of the present invention is to increase the radius of curvature of the edge portion in each of the diffusion layers of the emitter region and the collector region, thereby achieving a bipolar transistor. It is an object of the present invention to provide a semiconductor device in which occurrence of a secondary breakdown phenomenon in a transistor and a method for manufacturing the same are provided.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate, a first diffusion layer for each of an emitter region and a collector region provided on the semiconductor substrate, A second diffusion layer provided in the first diffusion layer of each of the collector regions and having an edge overlapping the edge of the first diffusion layer.

A step of depositing an insulating layer on the semiconductor substrate; a step of providing a mask film on the insulating layer; a step of etching the insulating layer using the mask film as a mask; Providing side wall material on both side surfaces,
Implanting a first impurity into the semiconductor substrate in a self-aligned manner using the mask film and the sidewall material as a mask;
A step of removing the mask film and the side wall material, and a first heat treatment for diffusing the first impurity,
Forming a first diffusion layer of each of an emitter region and a collector region in the semiconductor substrate; implanting a second impurity into the semiconductor substrate in a self-aligned manner using the insulating layer as a mask; By a second heat treatment for diffusing a second impurity, the first diffusion layer in each of the emitter region and the collector region has
Forming a second diffusion layer having an edge portion where the edge portion of the first diffusion layer overlaps.

A step of providing an insulating layer on the semiconductor substrate; a step of providing sidewall materials on both side surfaces of the insulating layer; and a step of self-aligning with the semiconductor substrate using the insulating layer and the sidewall material as a mask. Implanting one impurity, removing the sidewall material, and performing a first heat treatment for diffusing the first impurity, the first diffusion layer of each of the emitter region and the collector region in the semiconductor substrate. Forming a self-aligned second impurity into the semiconductor substrate using the insulating layer as a mask; and performing a second heat treatment for diffusing the first and second impurities. Forming a second diffusion layer in the first diffusion layer of each of the emitter region and the collector region, the second diffusion layer having an edge portion at which an edge portion of the first diffusion layer overlaps; It is characterized by comprising. The first diffusion layer has a higher resistance than the second diffusion layer.

[0011]

According to the present invention, a first impurity is implanted in a semiconductor substrate in a self-aligned manner using a mask film and a side wall material as a mask.
Thereafter, the first impurity is diffused by a first heat treatment. Thus, the first diffusion layers of the emitter region and the collector region are formed on the semiconductor substrate. Next, the mask film and the side wall material are removed, and the second layer is self-aligned with the semiconductor substrate using the insulating layer as a mask.
Is implanted, and then the first and second impurities are diffused by a second heat treatment. Accordingly, the size of the first diffusion layer is further increased, and a second diffusion layer made of the second impurity is formed in the first diffusion layer. At this time, the edge portion of the first diffusion layer and the edge portion of the second diffusion layer are formed so as to overlap. For this reason, the radius of curvature of the edge portion in each of the first and second diffusion layers of the emitter region and the collector region can be made larger than that of the related art.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is a sectional view showing an iCMOS type semiconductor device, and FIG.
FIG. 2 is an enlarged sectional view showing a collector region and an emitter region in the BiCMOS type semiconductor device of FIG. Embedded N ⁺ is embedded in the surface of the P-type silicon substrate 15. A diffusion layer 16 is formed, and the buried N ⁺ On the diffusion layer 16 and the P-type silicon substrate 15, an N-type epitaxial layer 17 is provided. On the surface of the N-type epitaxial layer 17, first to third field oxide films 18a to 18c are provided. The N-type epitaxial layer 17 is provided between the first and second field oxide films 18a and 18b and the buried N ⁺ De located on the diffusion layer 16
epN ⁺ A layer 19 is provided. This DeepN ⁺ In the layer 19, N ⁺ is used as a base region contact portion. A diffusion layer 20 is provided.

[0014] The N-type epitaxial layer 17 of the second and third Fi - field oxide film 18b, a first collector region located between the 18c, a second P ^- Diffusion layer 2
1, 22 are provided. These first, second P ^- The first and second P ⁺ are formed in the diffusion layers 21 and 22. Diffusion layer 2
3,24 is provided, the P ^- Diffusion layer 21, 2
Edge portion 21a in the 2, 22a is the P ⁺ The edge portions 23a and 24a of the mold diffusion layers 23 and 24 overlap with each other. P ⁺ The resistance of the diffusion layers 23 and 24 is P
^- It is lower than that of the mold diffusion layers 21 and 22. The N-type epitaxial layer 17 includes the first and second P ⁻ P emitter region located between the diffusion layers 21 and 22 ^- A mold diffusion layer 25 is formed. The P ^- P ⁺ in the diffusion layer 25 -Type diffusion layer 26 is provided, the P ^- Edge portion 25a of the diffusion layers 25, 25b is the P ⁺ It overlaps with the edge portions 26a and 26b in the mold diffusion layer 26. This P ⁺ Resistance of the diffusion layer 26 is the P ^- It is lower than that of the mold diffusion layer 25.

FIGS. 3 to 8 are sectional views showing a method of manufacturing the BiCMOS type semiconductor device according to the first embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals. On the surface of a P-type silicon substrate (not shown), a bipolar transistor region 30 and a CMOS transistor region (not shown) are provided. In the bipolar transistor region 30, an N-type impurity is ion-implanted on the surface of the P-type silicon substrate to thereby form a buried N ^{+ (not} shown). A diffusion layer is formed. This embedded N ⁺ N ⁻ is formed on the diffusion layer and the P-type silicon substrate. -Type epitaxial layer 17 is provided, the N ^- The first and second field oxide films 18b and 18c are formed on the surface of the type epitaxial layer 17 by LOCOS (Local Oxidation of Silicon).
Is provided. These field oxide films 18b and 18c
And N ^- Polycrystalline silicon layer 33 is deposited on type epitaxial layer 17. On this polycrystalline silicon layer 33, there is provided a first resist film 34 cured by ultraviolet rays, an organic solvent, plasma excitation or the like. This first
RIE (ReactiveIon) using the resist film 34 as a mask
Etching) etches the polycrystalline silicon layer 33.

[0016] Thereafter, as shown in FIG. 4, the N ^- -Type epitaxial layer 17, first and second field oxide films 1
8b, 18c, the first resist film 34 and the CMO
A second resist film 35 is applied on the S transistor region.

Next, as shown in FIG. 5, by selectively etching the second resist film 35, a side wall material is provided on both side surfaces of the polycrystalline silicon layer 33 and the first resist film 34. 35 are formed. Thereafter, the first, second Fi - field oxide film 18b, 18c, a self-aligned manner with said N first resist film 34 and the sidewall member 35 as a mask ^- A P type impurity 38 is implanted into the type epitaxial layer 17.

Thereafter, as shown in FIG. 6, the first resist film 34 and the side wall material 35 are removed. Next, a first heat treatment for diffusing the impurity 38 is performed, whereby the N ⁻ Type epitaxial layer 17 has first and second P ⁻ -Type diffusion layers 21 and 22 and P ^{− of the} emitter region A mold diffusion layer 25 is formed.

Next, as shown in FIG.
On the field oxide films 18b and 18c and the CM
A third resist film 29 is provided in the OS transistor region. Using the third resist film 29 and the polycrystalline silicon layer 33 as a mask, the N ⁻ A P-type impurity 39 is implanted into the type epitaxial layer 17. At this time, the impurity 39 is also implanted into a source / drain region (not shown) of the CMOS transistor region.

Thereafter, as shown in FIG.
The dist film 29 is removed. Next, the impurity 39 is expanded.
By performing the second heat treatment for dispersing,
Note P^- In each of the mold diffusion layers 21, 22 and 25,
First and second P in the⁺ Type diffusion layers 23, 24 and
Emitter region P⁺ A mold diffusion layer 26 is formed. these
P⁺ Edge 23 of each of the mold diffusion layers 23, 24, 26
a, 24a, 26a, 26b are the P^- Type diffusion layer 21,
Edge portions 21a, 22a, 25 of respective 22, 25
a, 25b. The P⁺ Diffusion layer 2
3, 24 and 26 are shallow diffusion layers,^- Type
The diffusion layers 21, 22, 25 are deep diffusion layers.

According to the above embodiment, the first and second fields
Using the oxide films 18b and 18c, the first resist film 34, and the side wall material 35 as a mask, the N ⁻ A P type impurity 38 is implanted into the type epitaxial layer 17. Thereafter, the impurity 38 is diffused by a first heat treatment. Accordingly, the N ^- The first and second P ⁻ of the collector region are formed in the epitaxial layer 17. -Type diffusion layers 21 and 22 and P ^{− of the} emitter region The mold diffusion layer 25 is formed. Next, a third resist film 29 and a polycrystalline silicon layer 33 are formed.
Self-aligning manner said as a mask N ^- A P type impurity 39 is implanted into the type epitaxial layer 17. Thereafter, the impurities 38 and 39 are diffused by a second heat treatment.
As a result, the P ^- The size of the diffusion layers 21, 22 and 25 is further increased, and these P ⁻ Diffusion layer 21, 2
The first and second P of the collector region in each of 2 and 25
⁺ -Type diffusion layers 23 and 24 and P ⁺ The mold diffusion layer 26 is formed. At this time, the P ⁺ Diffusion layer 2
3,24,26 said respective edges P ^- The mold diffusion layers 21, 22, and 25 are formed so as to overlap with respective edge portions. For this reason, the radius of curvature of the edge portions 21a to 26b in the first and second diffusion layers 21 to 26 of the emitter region and the collector region can be made larger than that of the related art. As a result, the withstand voltage at the edge portions 21a to 26b can be improved. Therefore, the secondary breakdown phenomenon does not occur even when a large current flows during the operation of the bipolar transistor and holes and electrons pass through the edge portions 21a to 26b intensively.

[0022] In addition, the P ^- Mold diffusion layers 21, 22, 25
Is formed by implanting an impurity 38 in a self-aligned manner using the first resist film 34 and the side wall material 35 as a mask. P ⁺ Type diffusion layers 23, 24, 26
Is formed by implanting impurities 39 in a self-aligned manner using the polycrystalline silicon layer 33 as a mask.
For this reason, the distance between the emitter region and the collector region does not vary. Therefore, it is possible to prevent the occurrence of variation in the current amplification factor of the bipolar transistor.

FIGS. 9 to 15 show a method of manufacturing a BiCMOS type semiconductor device according to a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and different parts. Will be described only.

On the polycrystalline silicon layer 33, there is provided a first resist film (not shown) which is hardened by ultraviolet rays, an organic solvent, plasma excitation or the like. Using the first resist film as a mask, the polycrystalline silicon layer 33 is etched by RIE (Reactive Ion Etching). next,
The first resist film is removed.

[0025] Thereafter, as shown in FIG. 10, the polycrystalline silicon layer 33, N ^- On the first epitaxial layer 17 and the first and second field oxide films 18b and 18c.
Insulation layer 41 by VD (Chemical Vapor Deposition) method
Is deposited.

Next, as shown in FIG.
1 is anisotropically etched by RIE, so that sidewall insulating films 42 are formed on both side surfaces of the polycrystalline silicon layer 33.

Thereafter, as shown in FIG.
The second resist film 3 is formed on the second field oxide films 18b and 18c and in a CMOS transistor region (not shown).
5 is deposited. Using the second resist film 35, the polycrystalline silicon layer 33 and the sidewall insulating film 42 as a mask, the N ⁻ A P type impurity 38 is implanted into the type epitaxial layer 17.

Next, as shown in FIG. 13, the side wall insulating film 42 and the second resist film 37 are removed. Thereafter, a heat treatment for diffusing the impurity 38 is performed, whereby the N ⁻ Type epitaxial layer 17 has first and second P ⁻ -Type diffusion layers 21 and 22 and P ^{− of the} emitter region A mold diffusion layer 25 is formed.

Thereafter, as shown in FIG.
Second field oxide films 18b and 18c and the CM
A third resist film 29 is deposited in the OS transistor region. Using third resist film 29 and polycrystalline silicon layer 33 as a mask, P-type impurities 39 are self-aligned.
Is implanted.

Next, as shown in FIG. 15, the third resist film 29 is removed. Thereafter, a heat treatment for diffusing the impurity 39 is performed, whereby the P
^- In each of the diffusion layers 21, 22, 25, the first and second P ⁺ -Type diffusion layers 23 and 24 and P ⁺ A mold diffusion layer 26 is formed. In the second embodiment, the same effects as in the first embodiment can be obtained. Incidentally, the semiconductor device of the present invention is not limited to the above embodiment, but can be used for an NPN transistor or a diode.

[0031]

As explained above, according to the present invention,
A first impurity is implanted using the mask film and the side wall material as a mask, a first diffusion layer is formed in the semiconductor substrate by a first heat treatment, and a second impurity is implanted using the insulating layer as a mask. Then, a second diffusion layer is formed in the first diffusion layer by a second heat treatment. Therefore, the radius of curvature of the edge portion in each of the diffusion layers in the emitter region and the collector region can be increased, and the occurrence of the secondary breakdown phenomenon in the bipolar transistor can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a BiCMOS type semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view showing a collector region and an emitter region in the BiCMOS type semiconductor device of FIG. 1 of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the BiCMOS type semiconductor device according to the first embodiment of the present invention, showing a step of etching the polycrystalline silicon layer by RIE using the first resist film as a mask.

FIG. 4 shows a method of manufacturing a BiCMOS type semiconductor device according to the first embodiment of the present invention, wherein N ⁻ -Type epitaxial layer, first and second field oxide films, and first
Sectional drawing which shows the process of apply | coating a 2nd resist film on the resist film of FIG.

FIG. 5 shows a method of manufacturing a BiCMOS type semiconductor device according to the first embodiment of the present invention, in which a first and second field oxide films and first and second resist films are used as masks to form a P-type semiconductor device. Sectional drawing which shows the process of implanting the impurity of a type | mold.

FIG. 6 illustrates a method of manufacturing a BiCMOS type semiconductor device according to the first embodiment of the present invention, wherein N ⁻ The first and second P ⁻ of the collector region are added to the p-type epitaxial layer. -Type diffusion layer and the emitter region P ^- Sectional drawing which shows the process of forming a type | mold diffusion layer.

FIG. 7 shows a method of manufacturing the BiCMOS type semiconductor device according to the first embodiment of the present invention, and shows a step of implanting a P-type impurity using the third resist film and the polycrystalline silicon layer as a mask. FIG.

FIG. 8 shows a method of manufacturing a BiCMOS type semiconductor device according to the first embodiment of the present invention, wherein N ⁻ The first and second P ⁺ P ^{+ of the} diffusion region and the emitter region Sectional drawing which shows the process of forming a type | mold diffusion layer.

FIG. 9 shows a method of manufacturing a BiCMOS type semiconductor device according to a second embodiment of the present invention,
Sectional drawing which shows the process of etching a polycrystalline silicon layer by RIE using the said resist film as a mask.

FIG. 10 shows a BiCMOS according to a second embodiment of the present invention.
3A to 3C show a method of manufacturing a semiconductor device in which a CV is formed on a polycrystalline silicon layer and first and second field oxide films.
Sectional drawing which shows the process of depositing an insulating layer by the D method.

FIG. 11 shows a BiCMOS according to a second embodiment of the present invention;
FIG. 4 is a cross-sectional view illustrating the step of forming the sidewall insulating film on both side surfaces of the polycrystalline silicon layer, illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 12 shows a BiCMOS according to a second embodiment of the present invention;
FIG. 9 is a cross-sectional view illustrating the step of implanting a P-type impurity using the second resist film, the polycrystalline silicon layer, and the sidewall insulating film as a mask, illustrating the method for manufacturing the semiconductor device of FIG.

FIG. 13 shows a BiCMOS according to a second embodiment of the present invention;
FIG. 4 shows a method of manufacturing a semiconductor device of the type, wherein N ⁻ The first and second P ⁻ of the collector region are added to the p-type epitaxial layer. -Type diffusion layer and the emitter region P ^- Sectional drawing which shows the process of forming a type | mold diffusion layer.

FIG. 14 shows a BiCMOS according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view illustrating the step of implanting a P-type impurity using the third resist film and the polycrystalline silicon layer as a mask, illustrating the method of manufacturing the semiconductor device of FIG.

FIG. 15 shows a BiCMOS according to a second embodiment of the present invention;
FIG. 4 shows a method of manufacturing a semiconductor device of the type, wherein N ⁻ The first and second P ⁺ P ^{+ of the} diffusion region and the emitter region Sectional drawing which shows the process of forming a type | mold diffusion layer.

FIG. 16 is a sectional view showing a conventional BiCMOS type semiconductor device.

FIG. 17 is a cross-sectional view showing the flow of holes and electrons between the emitter region and the collector region in the conventional bipolar transistor shown in FIG.

[Explanation of symbols]

15: P-type silicon substrate, 16: embedded N ⁺ Diffusion layer, 17 ... N
-Type epitaxial layer, 18a ... first field oxide film,
18b ... second field oxide film, 18c ... third field oxide film, 19 ... Deep N ⁺ Layers, 20... N ⁺ as base region contact Diffusion layer, 21. First of collector region
Of P ^- Type diffusion layer, 22... Second P ^{− in} collector region Type diffusion layer, 23... First P ^{+ of} collector region Type diffusion layer, 24... Second P ^{+ in} collector region Type diffusion layer, 25 ... P in the emitter region
^- Type diffusion layer, 26 ... P ^{+ of} emitter region Type diffusion layer, 29: third resist film, 30: bipolar transistor region,
31 ... N ^- Type epitaxial layer, 33 ... polycrystalline silicon layer,
34: first resist film, 35: second resist film (sidewall material), 38, 39: P-type impurity, 41: insulating layer, 42: sidewall insulating film.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8249 H01L 21/331 H01L 27/06 H01L 29/73

Claims (3)

(57) [Claims] 1. Depositing a first mask layer on a semiconductor substrate
And providing a second mask layer on the first mask layer
And the first mask layer using the second mask layer as a mask.
Etching , forming a sidewall material on both side surfaces of the first mask layer, and using the second mask layer and the sidewall material as a mask.
A step of implanting the first impurity into the semiconductor substrate in a self-aligned manner.
And extent, removing the second mask layer and said side wall member
And a first heat treatment for diffusing the first impurity.
And an emitter region and a collector region in the semiconductor substrate.
Forming each of the first diffusion layers; and using the first mask layer as a mask to attach the first diffusion layer to the semiconductor substrate.
Implanting a second impurity in a self-aligned manner, and implanting a second impurity for diffusing the first and second impurities.
By the heat treatment, the emitter region and the collector region
In each of the first diffusion layers, the first diffusion layer
A second extension having edges overlapping the edges in the second
Forming a diffused layer . A method for manufacturing a semiconductor device, comprising: 2. A step of providing a mask layer on a semiconductor substrate.
When the semiconductor comprising the steps of providing a side wall material on both sides of the mask layer, the mask layer and said side wall member as a mask
A step of implanting a first impurity in a body substrate in a self-aligned manner, a step of removing the side wall material, and a first heat treatment for diffusing the first impurity.
And an emitter region and a collector region in the semiconductor substrate.
Forming respective first diffusion layers; and self-aligning with the semiconductor substrate using the mask layer as a mask.
Implanting a second impurity, and a second impurity for diffusing the first and second impurities.
By the heat treatment, the emitter region and the collector region
In each of the first diffusion layers, the first diffusion layer
A second extension having edges overlapping the edges in the second
Forming a diffused layer . A method for manufacturing a semiconductor device, comprising: 3. The semiconductor device according to claim 2, wherein the first diffusion layer is closer to the second diffusion layer.
3. The method according to claim 1, wherein the resistance is higher.
A method for manufacturing a semiconductor device according to any one of the above.