JP2968269B2 - Manufacturing method of liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly to a method of manufacturing an active matrix type liquid crystal display using thin film transistors or the like.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active method has a better contrast than the so-called simple matrix method that employs the time-division driving method, and is particularly lacking in color. It is becoming a technology that can not be done. A typical switching element is a thin film transistor (TFT).

In a conventional active matrix type liquid crystal display device, a transparent pixel electrode is used as one electrode,
A storage capacitor element is formed in which a scanning signal line formed of an adjacent opaque metal film is used as the other electrode, and a film of the same layer as an insulating film used as a gate insulating film of the thin film transistor is used as a dielectric film.

In this liquid crystal display device, since a storage capacitor element is provided, the value of the DC component applied to the liquid crystal can be reduced, so that the life of the liquid crystal is improved, and the liquid crystal display screen is switched to the previous one. It is possible to reduce the so-called burn-in in which an image remains, and to increase the discharge time of the storage capacitor element, so that video information after the thin film transistor is turned off can be accumulated for a long time.

Incidentally, an active matrix type liquid crystal display device using thin film transistors is described in, for example, "12.5-type active matrix type color liquid crystal display employing a redundant structure", Nikkei Electronics,
Pages 193-210, published December 15, 1986, published by Nikkei McGraw-Hill.

Known examples of forming a pixel electrode on a protective film covering a channel portion of a thin film transistor include JP-A-61-15625, JP-A-62-27837, JP-A-63-170682, and JP-A-63-170682. -208896,
JP-A-1-86113, JP-A-1-501100, JP-A-59-22209, JP-A-1-76036 and JP-A-1-1131731 disclose the source and drain electrodes of a thin film transistor in any of the known examples. There is no description of a configuration in which one electrode is formed of the same transparent conductive film as the pixel electrode, and the one electrode is electrically connected to the pixel electrode in a portion not overlapping with the gate electrode of the thin film transistor.

A known example in which a data line and a pixel electrode are formed of ITO and the data line and the pixel electrode are directly connected to a semiconductor layer of a thin film transistor is disclosed in JP-A-63-1218.
No. 86, but the above-mentioned known example differs from the present invention in that the layer relationship between the gate electrode and the source / drain electrode is opposite to that of the liquid crystal display device to which the present invention is applied.

Further, Japanese Patent Application Laid-Open No. 2-48639 discloses a prior art for connecting a drain electrode and a pixel electrode in a portion where a drain electrode and a gate electrode do not overlap with each other. There is no description of forming with a transparent electrode.

[0009]

In the conventional liquid crystal display device, since the pixel electrode is provided under the protective film covering the thin film transistor, the electric field acting on the liquid crystal cannot be increased. Could not be lowered.

Even if a pixel electrode is provided on the protective film, a through hole must be formed in the protective film at a connection portion between the source or drain electrode of the thin film transistor and the pixel electrode. However, there is a problem that a connection failure occurs, and that an aperture ratio must be sacrificed for connection between the thin film transistor and the pixel electrode.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. By providing a pixel electrode on a protective film, driving of a liquid crystal display device is facilitated, and a thin film transistor and a pixel electrode are formed without lowering an aperture ratio. It is an object of the present invention to improve the yield of manufacturing a liquid crystal display device by improving the connection with the liquid crystal display device.

[0012]

To achieve this object, the present invention provides a method for forming a first electrode on a glass substrate, a step of forming a first insulating film covering the first electrode, Providing a semiconductor layer forming a channel portion of the thin film transistor on the first insulating film; and forming a second and third electrodes facing each other with a gap in a region where the first electrode exists on the semiconductor layer. Forming and patterning the second electrode so as to have a first region overlapping the first electrode and a second region not overlapping the first electrode; Forming a second insulating film covering the third electrode, providing an opening in the second insulating film in the second region to connect the second electrode and the pixel electrode, 2 provided on the insulating film, the second electrode And a step of forming a transparent pixel electrode part overlap, and the second electrode is characterized by forming a transparent conductive film.

[0013]

In the method for manufacturing a liquid crystal display device provided by the present invention, since the pixel electrode is formed on the protective film, the electric field formed by the pixel electrode is not weakened by the protective film. Therefore, the electric field acting on the liquid crystal layer can be increased.

In addition, one of the source and drain electrodes is patterned so as to extend to a region where the gate electrode does not exist, and a through hole of a protective film is formed on the extending portion of the one electrode to form a pixel. Since the electrode is electrically connected to the one electrode, a large through hole can be formed, and there is no defective opening of the through hole, so that the pixel electrode and the thin film transistor can be reliably connected.

Further, since the one electrode is formed of a transparent conductive film, the aperture ratio of the pixel electrode does not decrease even if the one electrode is enlarged to increase the through hole.

Further, since the one electrode is formed of the same transparent conductive film as the pixel electrode, there is no problem that the contact resistance between the pixel electrode and the one electrode is increased.

When the protective film and the gate insulating film are formed of a silicon compound, the through hole is formed only on the region where the one electrode is present. It serves to protect the insulating film.

When the source / drain electrodes are formed of a transparent conductive film, external light easily hits the semiconductor layer of the thin film transistor, which causes a malfunction of the thin film transistor. By providing the light-shielding film, the influence of external light caused by forming the source / drain electrodes by the transparent conductive film does not matter.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the structure of the present invention will be described.
A description will be given together with an embodiment in which the present invention is applied to an active matrix type color liquid crystal display device.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 shows an active system to which the present invention is applied.
FIG. 2 is a plan view showing one pixel of a matrix type color liquid crystal display device and its periphery, FIG. 2 is a partially enlarged view of FIG.
FIG. 4 is a cross-sectional view taken along the line AA of FIG. 2 and a cross section near the seal portion of the display panel. FIG. 4 is a cross-sectional view taken along the line BB of FIG. 1. FIG. 6 is a plan view illustrating only the first conductive film d1 in FIG.

<< Pixel Arrangement >> As shown in FIG. 1, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or The vertical signal lines) are arranged in an intersecting region with the DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1b, and a storage capacitor Cadd. The scanning signal lines GL extend in the column direction, and a plurality of the scanning signal lines GL are arranged in the row direction. Video signal line D
L extends in the row direction and a plurality of Ls are arranged in the column direction.

<< Overall Structure of Display Section >> As shown in FIG. 3, the thin film transistor TFT and the transparent pixel electrode ITO1 are disposed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal LC.
The color filter FIL and a light shielding film BM for forming a light shielding black matrix pattern are formed on the upper transparent glass substrate SUB2 side. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 mm.

The center of FIG. 3 shows a cross section of one pixel portion, while the left side shows a cross section of a left edge portion of the transparent glass substrates SUB1 and SUB2 where external lead-out wiring exists, and the right side shows a transparent portion. The cross section of the right edge portion of the glass substrates SUB1 and SUB2 where no external lead-out wiring exists is shown.

The sealing materials SL shown on the left and right sides of FIG. 3 are configured to seal the liquid crystal LC, and the transparent glass substrate SU excluding the liquid crystal filling port (not shown).
B1 and SUB2 are formed along the entire periphery.
The sealing material SL is formed of, for example, an epoxy resin.

The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected at least at one location to an external lead wire formed on the lower transparent glass substrate SUB1 side by a silver paste material SIL. This external lead-out wiring is formed in the same manufacturing process as each of the gate electrode GT, the source electrode SD1, and the drain electrode SD2.

Alignment films ORI1, ORI2, transparent pixel electrode ITO1b, common transparent pixel electrode ITO2, protective film PSV
Each of the layers 1, 1, PSV2, and the insulating film GI is formed inside the sealing material SL. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.

The liquid crystal LC is sealed between a lower alignment film ORI1 for setting the direction of liquid crystal molecules and an upper alignment film ORI2, and is sealed by a seal portion SL.

The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side.

A light shielding film BM and a color filter FI are provided on the inner surface (the liquid crystal LC side) of the upper transparent glass substrate SUB2.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and an upper alignment film ORI2 are sequentially laminated.

This liquid crystal display device has a lower transparent glass substrate S
The layers on the UB1 side and the upper transparent glass substrate SUB2 side are separately formed, and then the upper and lower transparent glass substrates SUB are formed.
1. Assembly is performed by superposing SUB2 and sealing a liquid crystal LC between them.

<< Thin Film Transistor TFT >> The thin film transistor TFT operates so that the channel resistance between the source and the drain decreases when a positive bias is applied to the gate electrode GT, and the channel resistance increases when the bias is set to zero.

The thin film transistor TFT of each pixel is divided into three (a plurality) in the pixel, and the thin film transistors (divided thin film transistors) TFT1, TFT2 and T
FT3. Thin film transistors TFT1
Each of the TFTs 3 has substantially the same size (the same channel length and width). Each of the divided thin film transistors TFT1 to TFT3 mainly includes a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic, intrinsic).
c, an i-type semiconductor layer AS made of amorphous silicon (Si) not doped with a conductivity type determining impurity, and a pair of a source electrode SD1 and a drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are interchanged during the operation. However, also in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.

<< Gate Electrode GT >> The gate electrode GT is shown in FIG.
As shown in detail in FIG. 1 (a plan view depicting only the first conductive film g1, the second conductive film g2, and the i-type semiconductor layer AS),
It is configured so as to protrude vertically (upward in FIGS. 1 and 7) from the scanning signal line GL (branched into a T-shape). The gate electrode GT is configured to protrude to the respective formation regions of the thin film transistors TFT1 to TFT3. Thin film transistors TFT1 to T
Each gate electrode GT of the FT3 is integrally formed (as a common gate electrode), and is formed continuously with the scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film g1 so that a large step is not formed in a region where the thin film transistor TFT is formed. The first conductive film g1 is formed, for example, using a chromium (Cr) film formed by sputtering and having a thickness of about 1000 °.

As shown in FIGS. 1, 3 and 7, this gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below).
Therefore, when the backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque chrome becomes a shadow, and the backlight does not shine on the i-type semiconductor layer AS. In addition, the conductive phenomenon due to light irradiation, that is, the deterioration of the off characteristic of the thin film transistor TFT is less likely to occur. Note that the original size of the gate electrode GT is the minimum necessary to extend between the source electrode SD1 and the drain electrode SD2 (including the margin for positioning between the gate electrode GT, the source electrode SD1, and the drain electrode SD2). ) Has a width, and the depth length that determines the channel width W is determined by the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W / L that determines the transconductance gm. It depends on what you do.

The gate electrode GT in this liquid crystal display device
Of course, is made larger than the original size described above.

If only the gate electrode GT and the light-shielding functional surface are considered, the gate electrode GT and the scanning signal line GL may be integrally formed in a single layer. In this case, silicon is used as an opaque conductive material. Containing aluminum (Al), pure aluminum, palladium (Pd)
Can be selected.

<< Scanning Signal Line GL >> The scanning signal line GL is
The conductive film g1 and the second conductive film g2 provided thereon
It consists of a composite membrane consisting of This scanning signal line GL
The first conductive film g1 is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally formed.
The second conductive film g2 is formed, for example, using an aluminum film formed by sputtering and having a thickness of about 1000 to 5500 °. The second conductive film g2 is configured to reduce the resistance value of the scanning signal line GL and to increase the signal transmission speed (improve the writing characteristics of pixel information).

The width of the second conductive film g2 of the scanning signal line GL is smaller than the width of the first conductive film g1. In other words, the scanning signal line GL has a gentle step on the side wall.

<< Insulating Film GI >> The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 to TFT3. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. The insulating film GI is formed with a thickness of about 3000 ° using a silicon nitride film formed by, for example, plasma CVD.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
Is used as a channel forming region of each of a plurality of divided thin film transistors TFT1 to TFT3, as shown in FIG. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film and has a thickness of about 1800 °.

The i-type semiconductor layer AS is formed in the same plasma CVD apparatus by changing the composition of the supply gas and continuously forming an insulating film GI used as a gate insulating film made of Si ₃ N ₄ using the same plasma CVD apparatus. It is formed without being exposed to the outside from the CVD apparatus. Similarly, an N ⁺ -type semiconductor layer d0 doped with P for ohmic contact (FIG. 3) is formed continuously to a thickness of about 400 °. Thereafter, the lower transparent glass substrate SUB1 is taken out of the CVD apparatus, and the N ⁺ -type semiconductor layers d0 and i
The type semiconductor layer AS is patterned in an independent island shape as shown in FIGS.

As shown in detail in FIGS. 1 and 7, the i-type semiconductor layer AS is also provided between both intersections (crossover portions) between the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection is configured to reduce a short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Protective Film PSV1 >> Thin Film Transistor TF
On T, a protective film PSV1 is provided. Protective film PS
V1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a material having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD device, and has a thickness of about 8000 °.

<< Source electrode SD1, Drain electrode SD
2 >> Thin-film transistors TFT1 to TF divided into a plurality
Each source electrode SD1 and drain electrode SD of T3
2 means on the i-type semiconductor layer AS as shown in detail in FIGS. 1, 2, 3, and 8 (a plan view showing only the second conductive film d2 to the fourth conductive film d4 in FIG. 1). Are provided separately from each other.

The source electrode SD1 is connected to the N ⁺ type semiconductor layer d0.
And a fourth conductive film d4 connected to the first conductive film d1 via a through-hole CONT provided in the protective film PSV1, and the drain electrode SD2 is The first conductive film d1 and the first conductive film d1 via the through hole CONT provided in the protective film PSV1.
And a second conductive film d2 and a third conductive film d3 which are superimposed on the fourth conductive film d4.

The first conductive film d1 and the fourth conductive film d4 are transparent conductive films (Induim-Tin-Oxide) formed by sputtering.
It is formed of an ITO (Nesa film) and has a thickness of 1000 to 2000 Å (about 1200 で は in this liquid crystal display device). The first conductive film d1 is connected to the source electrode SD1,
A drain electrode SD2 is formed, and a lattice-shaped transparent auxiliary electrode ITO1a as shown in FIG. 6 is formed. The fourth conductive film d4 forms a source electrode SD1, a drain electrode SD2, and a video signal line DL. , The transparent pixel electrode ITO1b. The second conductive film d2 uses a chromium film formed by sputtering,
In this liquid crystal display device, the film is formed to have a thickness of about 2,000 mm. The chromium film is formed in a range not exceeding about 2000 ° because the stress increases when the chromium film is formed thick. In addition, as the second conductive film d2, a high melting point metal (Mo, Ti, Ta,
W) film, refractory metal silicide (MoSi ₂ , TiS)
_{i 2, TaSi 2, WSi 2} ) may be formed of a film. Further, the third conductive film d3 is made of aluminum formed by sputtering, and has a thickness of 3000 to 5500 ° (about 3500 ° in this liquid crystal display device). The aluminum film has a smaller stress than the chromium film and can be formed to have a large thickness.
It is configured to reduce the resistance values of D2 and the video signal line DL. The third conductive film d3 may be formed of an aluminum film containing silicon or copper (Cu) as an additive in addition to the aluminum film.

After patterning the first conductive film d1 by photographic processing, the first conductive film d1 is patterned using the same photographic processing mask.
Using the conductive film d1 as a mask, the N ⁺ type semiconductor layer d0 is removed. That is, the N ⁺ remaining on the i-type semiconductor layer AS
The portion of the type semiconductor layer d0 other than the first conductive film d1 is removed by self-alignment. At this time, since the N ⁺ -type semiconductor layer d0 is etched so as to remove the entire thickness, the i-type semiconductor layer AS is also slightly etched at its surface, but the degree is controlled by the etching time. Good.

The source electrode SD1 is a transparent pixel electrode ITO1.
b. The source electrode SD1 has a stepped shape of the i-type semiconductor layer AS (a step corresponding to the sum of the thickness of the first conductive film g1, the thickness of the N ⁺ -type semiconductor layer d0, and the thickness of the i-type semiconductor layer AS). ).

<< Transparent Pixel Electrode ITO1b >> The transparent pixel electrode ITO1b is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITO1b is composed of thin-film transistors TFT1-T1 divided into a plurality of pixels.
Three divided transparent pixel electrodes E corresponding to each of FT3
1, E2 and E3. Divided transparent pixel electrode E
1 to E3 are source electrodes S of the thin film transistor TFT, respectively.
D1.

Each of the divided transparent pixel electrodes E1 to E3 is patterned so as to have substantially the same area.

As described above, the thin film transistor T of one pixel
The FT is divided into a plurality of thin film transistors TFT1 to TFT3, and the plurality of divided thin film transistors TFT1
To each of the divided transparent pixel electrodes E1 to E3, even if the divided part (for example, the thin film transistor TFT1) becomes a point defect, it is not a point defect in the whole pixel (the thin film transistor TFT2). And the thin film transistor TFT3 is not defective), so that the probability of point defects can be reduced and defects can be hardly seen.

Further, by forming each of the divided transparent pixel electrodes E1 to E3 with substantially the same area, each of the divided transparent pixel electrodes E1 to E3 and the common transparent pixel electrode I
Each liquid crystal capacitance Cpix constituted by TO2 can be made uniform.

<< Light shielding film BM >> Upper transparent glass substrate SUB
On the second side, a light-shielding film BM is provided so that external light (light from above in FIG. 3) does not enter the i-type semiconductor layer AS used as a channel formation region.
The pattern shown in FIG. FIG. 9 shows the fourth conductive film d made of the ITO film in FIG.
FIG. 4 is a plan view illustrating only a color filter FIL and a light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property. In this liquid crystal display device, the chromium film is formed to a thickness of about 1300 ° by sputtering.

Therefore, the thin film transistors TFT1 to TFT1
The i-type semiconductor layer AS of the TFT 3 is sandwiched between the upper and lower light shielding films BM and the large gate electrode GT, and the portion is not exposed to external natural light or backlight. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. 9, that is, the light-shielding film BM is formed in a lattice shape (black matrix), and an effective display area of one pixel is partitioned by the lattice. . Therefore, the outline of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light shielding film BM is the i-type semiconductor layer A
It has two functions of light shielding for S and a black matrix.

The backlight can be attached to the upper transparent glass substrate SUB2, and the lower transparent glass substrate SUB1 can be used as the observation side (exposed side).

<< Common Transparent Pixel Electrode ITO2 >> The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1b provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is determined by each transparent pixel electrode. It changes in response to a potential difference (electric field) between ITO1b and the common transparent pixel electrode ITO2. The common transparent pixel electrode ITO2 is configured to apply a common voltage Vcom. The common voltage Vcom is an intermediate potential between the low-level drive voltage Vdmin and the high-level drive voltage Vdmax applied to the video signal line DL.

<< Color Filter FIL >> The color filter FIL is formed by coloring a dye base material formed of a resin material such as an acrylic resin with a dye. Color filter F
The IL is formed in a dot shape for each pixel at a position facing the pixel (FIG. 10) and is dyed separately (FIG. 10 illustrates only the fourth conductive film layer d4 and the color filter FIL in FIG. Each of the color filters FIL of R, G, and B is cross hatched at 45 ° and 135 °). The color filter FIL is formed to be large so as to cover all of the transparent pixel electrodes ITO1b (E1 to E3) as shown in FIG. It is formed inside the peripheral edge of the electrode ITO1b.

The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process.

<< Protective Film PSV2 >> The protective film PSV2 is composed of a liquid crystal L which is a dye obtained by dyeing the color filter FIL into different colors.
It is provided to prevent leakage to C. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin.

<< Pixel Arrangement >> Each pixel of the liquid crystal display section is shown in FIG.
10, as shown in FIG. 10, a plurality of pixel columns X1, X2,
X3, X4,... Each pixel row X
Each of the pixels 1, X2, X3, X4,... Has the same arrangement position of the thin film transistors TFT1 to TFT3 and the divided transparent pixel electrodes E1 to E3. That is,
Each pixel of the odd-numbered pixel rows X1, X3,... Has the thin film transistors TFT1 to TFT3 arranged on the left and the divided transparent pixel electrodes E1 to E3 arranged on the right. Each of the adjacent even-numbered pixel columns X2, X4,... In the row direction of each of the odd-numbered pixel columns X1, X3,. It is composed of pixels turned upside down in line symmetry with respect to the direction. That is, the pixel columns X2, X4,.
Each pixel is a thin film transistor TFT1 to TF
The arrangement position of T3 is configured on the right side, and the arrangement position of the transparent pixel electrodes E1 to E3 is configured on the left side. Then, the pixel rows X2, X
, Are arranged (shifted) by a half pixel interval in the column direction with respect to each pixel of the pixel columns X1, X3,. That is, assuming that each pixel interval of the pixel row X is 1.0 (1.0 pitch), the pixel row X of the next stage has the pixel interval of 1.0 and is arranged in the column direction with respect to the preceding pixel row X. It is shifted by 0.5 pixel intervals (0.5 pitch). The video signal lines DL extending in the row direction between the pixels are half pixel intervals (0.5 pitch) between the pixel columns X.
It is configured to extend in the column direction.

As a result, as shown in FIG. 10, the pixels (for example,
1.5 pixels of the pixel row X3 on which the red filter R is formed) and 1.5 pixels of the next pixel row X on which the same color filter is formed (for example, pixels of the pixel row X4 on which the red filter R is formed). Separated by pixel interval (1.5 pitch)
The B color filters FIL have a triangular arrangement. The RGB triangular arrangement structure of the color filter FIL can improve the color mixture of each color, so that the resolution of a color image can be improved.

Further, since the video signal lines DL extend in the column direction only by half pixel intervals between the pixel columns X, they do not intersect with the adjacent video signal lines DL. Therefore,
Eliminating the video signal line DL and reducing its occupied area can be eliminated, and detour of the video signal line DL can be eliminated,
The multilayer wiring structure can be eliminated.

<< Equivalent Circuit of Entire Display Device >> FIG. 11 shows an equivalent circuit of this liquid crystal display device. XiG, Xi + 1G, ...
Is a video signal line DL connected to the pixel on which the green filter G is formed. XiB, Xi + 1B,... Are video signal lines DL connected to the pixels where the blue filter B is formed.
It is. Xi + 1R, Xi + 2R,... Are video signal lines DL connected to pixels on which the red filter R is formed. These video signal lines DL are selected by a video signal drive circuit. Yi is a scanning signal line GL that selects the pixel column X1 shown in FIGS. Similarly, Yi + 1, Y
Each of i + 2,... is a scanning signal line GL for selecting each of the pixel columns X2, X3,. These scanning signal lines GL are connected to a vertical scanning circuit.

<< Structure of Storage Capacitance Element Cadd >> Each of the divided transparent pixel electrodes E1 to E3 is a thin film transistor TF.
At the end opposite to the end connected to T, the insulating film G
It is bent in an L shape so as to overlap with the transparent auxiliary electrode ITO1a formed on I. As is apparent from FIG. 4, this superposition is performed by the divided transparent pixel electrode E1.
To E3 constitute one electrode PL2 and the transparent auxiliary electrode ITO1a constitutes the other electrode PL1 to form a storage capacitor (capacitance element) Cadd. The transparent auxiliary electrode ITO1a is connected to the common transparent pixel electrode ITO2 (Vcom) via the silver paste material SL, and the dielectric film of the storage capacitor Cadd is formed of the same layer as the protective film PSV1. Thus, the electrode PL of the storage capacitance element Cadd
1 and PL2 are composed of the transparent auxiliary electrode ITO1a and the divided transparent pixel electrodes E1 to E3.
Even if the storage capacity of add is increased, the aperture ratio does not decrease, so that the screen becomes brighter, and the transparent auxiliary electrode ITO1a is connected to the common transparent pixel electrode ITO2 (Vco
m), and is not connected to the scanning signal line GL, so that a large load does not act on the gate drive device, so that there is no need to increase the gate drive voltage. Further, since the transparent auxiliary electrode ITO1a has a lattice shape, the resistance of the transparent auxiliary electrode ITO1a is reduced.
The function of the storage capacitor Cadd is assured. Further, since the transparent auxiliary electrode ITO1a and the conductive film forming the source electrode SD1 and the drain electrode SD2 are formed of the same first conductive film d1, the manufacturing process is simple, so that the manufacturing cost is low and protection is achieved. Through hole C in film PSV1
When the ONT is provided, it is possible to prevent the N ⁺ type semiconductor layer d0 from being removed together with the protective film PSV1.
That is, when the first conductive film d1 is not provided on the N ⁺ type semiconductor layer d0, the protection film PSV1 and the N ⁺ type semiconductor layer d0
(Selective etching of the silicon nitride of the protective film PSV1 also dissolves amorphous silicon. The selectivity is not good.) When the through hole CONT is provided in the protective film PSV1, protective film PSV1 with N ⁺ -type semiconductor layer d0 from being removed but, when the first conductive film d1 formed on the N ⁺ -type semiconductor layer d0 is possible to prevent the N ⁺ -type semiconductor layer d0 is removed Can be. Further, since the dielectric film of the storage capacitor Cadd is formed of the same film as the protective film PSV1, the manufacturing process is simple, and the manufacturing cost is low. further,
The divided transparent pixel electrodes E1 to E3 are connected to the source electrode SD1 via the through holes CONT provided in the protective film PSV1 to connect the divided transparent pixel electrodes E1 to E3 to the protective film PS.
V1 so that the divided transparent pixel electrodes E1 to E3
Since the protective film PSV1 does not exist between the liquid crystal LC and the common transparent pixel electrode ITO2, the electric field acting on the liquid crystal LC can be increased. In other words, the gate drive voltage can be reduced.

Since the formation of the through-holes CONT can be performed simultaneously with the step of exposing the external connection terminals around the display matrix, the number of steps and the number of photomasks do not need to be increased.

As shown in FIGS. 1 and 3, the first conductive film d1 of the source electrode SD1 extends to a region where the gate electrode GT does not exist, and the first conductive film d1 of the source electrode SD1 is connected to the gate electrode GT. Protective film PS even on parts that do not overlap
V1 through-hole CONT is provided and transparent pixel electrode IT
Since O1b (d4) is electrically connected to the first conductive film d1 of the source electrode SD1, a large through hole CONT can be formed, and the transparent pixel electrode ITO1b (d
4) and the first conductive film d1 of the source electrode SD1 can be reliably connected. Therefore, the through hole CON
Pixel defects due to poor opening of T can be eliminated.

Further, the first conductive film d of the source electrode SD1
1 is made of a transparent conductive film, and as shown in FIGS. 1 and 3, the first conductive film d1 of the source electrode SD1 extends to a portion where the i-type semiconductor layer AS does not exist, in order to enlarge the through hole CONT. However, the transparent pixel electrode ITO1b (d
4) The aperture ratio is not reduced.

Further, the first conductive film d1 of the source electrode SD1
Is formed of the same transparent conductive film as the transparent pixel electrode ITO1b (d4), there is no problem that the contact resistance between the transparent pixel electrode ITO1b (d4) and the first conductive film d1 of the source electrode SD1 increases.

In this embodiment, the protective film PSV1 and the gate insulating film GI are formed of a silicon compound. However, as shown in FIG. 1 and FIG.
Since T is provided only on the region of the source electrode SD1 where the first conductive film d1 exists, the through hole C is formed in the protective film PSV1.
When the ONT is formed, the first conductive film d1 of the source electrode SD1 made of a transparent conductive film protects the gate insulating film GI, so that the gate insulating film GI is not removed at the portion of the through hole CONT.

When the source electrode SD1 and the drain electrode SD2 are formed of a transparent conductive film, external light easily hits the i-type semiconductor layer AS of the thin film transistor TFT, which causes a malfunction of the thin film transistor TFT.
As shown in FIGS. 1 and 3, a light-shielding film BM that covers the i-type semiconductor layer AS is provided on the source electrode SD1 and the drain electrode SD2, so that the source electrode SD1 and the drain electrode SD2 are transparent in this embodiment. There is no problem with the influence of external light due to the formation of the conductive film.

<< Equivalent Circuit of Storage Capacitor Cadd and Its Operation >> FIG. 12 shows an equivalent circuit of the pixel shown in FIG. In FIG. 12, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film of the parasitic capacitance Cgs is the insulating film GI. Cpix is a liquid crystal capacitance formed between the transparent pixel electrode ITO1b (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitor Cpix is the liquid crystal LC and the alignment films ORI1 and ORI2. Vlc is a midpoint potential.

The storage capacitor Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation.

[0074]

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔVlc represents a change in the midpoint potential due to ΔVg. The change ΔVlc causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance Cadd is increased. Further, the holding capacitance element C
The add function has a function of prolonging the discharge time, and stores video information after the thin film transistor TFT is turned off for a long time. The reduction of the DC component applied to the liquid crystal LC improves the life of the liquid crystal LC, and can reduce so-called burn-in in which a previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. The midpoint potential Vlc has an adverse effect of being easily affected by the gate (scan) signal Vg. However, the storage capacitor Cadd
This disadvantage can also be eliminated by providing.

The storage capacitance of the storage capacitor Cadd is 4 to 8 times (4 ×) the liquid crystal capacitance Cpix due to the writing characteristics of the pixel.
Cpix <Cadd <8 · Cpix), 8 for the parasitic capacitance Cgs
The value is set to about 32 times (8 · Cgs <Cadd <32 · Cgs).

Next, referring to FIGS. 13 and 14, FIGS.
A method for manufacturing the liquid crystal display device shown in FIG. 2 will be described.

First, as shown in FIG.
Lower transparent glass substrate SUB1 made of glass (trade name)
A first conductive film g1 made of chromium having a thickness of 1100 °
Is provided by sputtering. Next, after performing a first photo (photo processing such as photoresist coating and exposure), the first conductive film g1 is selectively etched by using a ceric ammonium nitrate solution as an etchant. The first layer of the scanning signal line GL and the gate electrode GT are patterned. Next, after removing the resist with a stripper S502 (trade name), O ₂ asher is performed for 1 minute. Next, a second conductive film g2 having a thickness of 1000 ° made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, or the like is provided by sputtering. Next, after performing the second photo, the second conductive film g2 is selectively etched using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etchant, thereby forming the second layer of the scanning signal line GL. Is patterned. Next, SF ₆ gas is introduced into a dry etching apparatus to remove residues such as silicon, and then the resist is removed.

Next, as shown in FIG. 13B, an ammonia gas, a silane gas and a nitrogen gas are introduced into the plasma CVD apparatus to provide a silicon nitride film GI having a thickness of 3500 °, and the silane gas is introduced into the plasma CVD apparatus. Hydrogen gas is introduced to make the i-type amorphous silicon film AS having a thickness of 2100 °
Is provided, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to continuously grow an N ⁺ type silicon film d0 having a thickness of 300 °.

Next, as shown in FIG. 13C, after performing a third photo, SF is used as a dry etching gas.
₆ , the N ⁺ type silicon film and the i type amorphous silicon film are selectively etched using CCl ₄ to pattern the i type semiconductor layer AS. Next, after the resist is removed and a fourth photo is performed, a silicon nitride film such as an external connection terminal (gate terminal) around the matrix is selectively etched using SF ₆ as a dry etching gas. Thereby, the insulating film GI is patterned.

Next, as shown in FIG. 13D, after removing the resist, a first conductive film d1 made of an ITO film having a thickness of 1200 ° is provided by sputtering. Next, after performing a fifth photo, the first conductive film d1 is selectively etched using a mixed acid of hydrochloric acid and nitric acid as an etchant, thereby forming the first layer of the source electrode SD1 and the drain electrode SD2. And transparent auxiliary electrode ITO1a
Is patterned. At this time, as shown in FIG. 13D, the first conductive film d1 serving as the source electrode SD1 is extended to a region on the gate insulating film GI where the gate electrode GT does not exist.
It is provided to extend. Next, before the resist is removed, CCl ₄ and SF ₆ are introduced into a dry etching apparatus, and N ⁺
By selectively etching the type silicon film, N
^{The +} type semiconductor layer d0 is patterned.

Next, as shown in FIG. 14E, after removing the resist, an ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to provide a silicon nitride film PSV1 having a thickness of 1 μm. Next, after performing the sixth photo, the protection film PSV1 is patterned by selectively etching the silicon nitride film using SF ₆ as a dry etching gas, and a through hole CONT is formed in the protection film PSV1. Provide.
At this time, since the N ⁺ type amorphous silicon layer is protected by the transparent conductive film d1, it is not etched. As shown in FIG. 14E, the first conductive film d1 serving as the source electrode SD1 is formed on the gate insulating film GI by the gate electrode G1.
Since it is provided to extend to a region where T does not exist, even if the through-hole CONT is provided on the gate insulating film GI, the portion where the first conductive film d1 made of the transparent conductive film is provided has silicon nitride. The gate insulating film GI made of a film is not etched.

Therefore, by forming the source electrode large, the through hole CONT can be enlarged, and the protective film PSV1 at the portion of the through hole CONT can be surely removed.

Next, as shown in FIG. 14F, after removing the resist, a fourth conductive film d4 made of an ITO film having a thickness of 1200 ° is provided by sputtering. Next, after performing the seventh photo, the fourth conductive film d4 is selectively etched using a mixed acid of hydrochloric acid and nitric acid as an etchant, thereby forming the first of the video signal lines DL.
The layer, the second layer of the source electrode SD1, the drain electrode SD2, and the transparent pixel electrode ITO1b are patterned.

Next, as shown in FIG. 14 (g), after removing the resist, a second conductive film d2 made of chromium having a thickness of 600 ° is formed by sputtering. Next, after performing an eighth photo, the second conductive film d2 is selectively etched using a ceric ammonium nitrate solution as an etchant, thereby forming a second layer of the video signal line DL and a drain electrode. The third layer of SD2 is patterned. Next, after removing the resist, an O ₂ asher is performed for one minute.

Next, as shown in FIG. 14H, a third conductive film d3 having a thickness of 3500 ° made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, or the like is sputtered. Is formed. Next, after performing the ninth photo, the third conductive film d3 is selectively etched using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etchant, thereby forming the third layer of the video signal line DL. Then, the fourth layer of the source electrode SD1 is patterned. Next, after removing the resist, an O ₂ asher is performed for one minute.

FIG. 15 is a plan view showing one pixel of an active matrix type color liquid crystal display device to which the present invention is applied and its periphery, and FIG. 16 is a partially enlarged view of FIG. In this liquid crystal display device, the scanning signal line GL is composed of only the first conductive film g1. Further, the source electrode SD1 and the drain electrode SD2 are composed of a protective film PSV1, a second conductive film d2 connected to the N ⁺ type semiconductor layer d0 via a through hole CONT provided in the first conductive film d1,
The third conductive film d3 and the fourth conductive film d4 are superposed on the second conductive film d2.

Next, a method of manufacturing the liquid crystal display device shown in FIGS. 15 and 16 will be described with reference to FIGS. First, as shown in FIG. 17A, a first conductive film g1 is provided on a lower transparent glass substrate SUB1 by sputtering. Next, after performing a first photo, the scanning signal line GL and the gate electrode GT are patterned by selectively etching the first conductive film g1. Next, as shown in FIG. 17B, a silicon nitride film, an i-type amorphous silicon film, and an N ⁺ -type silicon film are successively provided by a plasma CVD apparatus. Next, as shown in FIG. 17C, after performing a second photo, an N ⁺ type silicon film is formed.
The i-type semiconductor layer AS is patterned by selectively etching the i-type amorphous silicon film. Next,
After performing the third photo, the insulating film GI is patterned by selectively etching the silicon nitride film. Next, as shown in FIG. 17D, a first conductive film d1 is provided by sputtering. Next, after performing the fourth photo, the transparent auxiliary electrode ITO1a is patterned by selectively etching the first conductive film d1, and the first conductive film d1 is connected to the source electrode SD1.
1. Patterning is performed so as to remain on the drain electrode SD2. Next, before removing the resist, the N ⁺ -type silicon layer is selectively etched to pattern the N ⁺ -type semiconductor layer d0. Next, as shown in FIG. 18E, a silicon nitride film is provided by a plasma CVD apparatus. Next, after performing the fifth photo, the silicon nitride film is selectively etched to form the protective film P.
The SV1 is patterned, a through-hole CONT is provided in the protective film PSV1, and the first conductive film d1 is selectively etched using the pattern of the protective film PSV1 as a mask, thereby forming the first conductive film d1 in the through-hole portion CONT. Is removed. Next, as shown in FIG. 18F, a second conductive film d2 is formed by sputtering. Next, after performing the sixth photo, the second conductive film d
2 is selectively etched, so that the video signal lines D
L, the first layer of the source electrode SD1 and the drain electrode SD2 is patterned. Next, as shown in FIG.
The third conductive film d3 is provided by sputtering. Next, after performing the seventh photo, the second layer of the video signal line DL, the source electrode SD1, and the drain electrode SD2 is patterned by selectively etching the third conductive film d3. Next, as shown in FIG. 18H, a fourth conductive film d4 is provided by sputtering. Next, after performing an eighth photo, the fourth conductive film d4 is selectively etched, so that the video signal line DL and the source electrode SD are formed.
1. Third layer of drain electrode SD2 and transparent pixel electrode I
The TO1b is patterned.

As described above, the invention made by the present inventor is:
Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the embodiments of the present invention, and it is needless to say that various changes can be made without departing from the gist of the present invention. .

[0090]

As described above, in the method for manufacturing a liquid crystal display device provided by the present invention, since the pixel electrode is formed on the protective film, the electric field generated by the pixel electrode can be increased. The driving of the liquid crystal display device can be facilitated.

The source electrode is patterned so as to extend to a region where the gate electrode does not exist, and a through-hole of a protective film is formed on the extension of the source electrode to electrically connect the pixel electrode and the source electrode. Therefore, the through-hole can be formed large, there is no defective opening of the through-hole, and the pixel electrode and the thin film transistor can be reliably connected.

Further, since the source electrode is formed of the same transparent conductive film as the pixel electrode, there is no problem that the connection resistance between the pixel electrode and the source electrode is increased.

Therefore, according to the present invention, the production yield of the liquid crystal display device can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a main part plan view showing one pixel of a liquid crystal display section of an active matrix type color liquid crystal display device to which the present invention is applied.

FIG. 2 is a partially enlarged view of FIG.

FIG. 3 is a cross-sectional view of a portion cut along a line AA in FIGS. 1 and 2 and a peripheral portion of a seal portion.

FIG. 4 is a sectional view taken along line BB of FIG. 1;

5 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 1 are arranged.

FIG. 6 is a plan view illustrating only a first conductive film d1 of FIG. 1;

FIG. 7 is a plan view illustrating only predetermined layers of the pixel illustrated in FIG. 1;

FIG. 8 is a plan view illustrating only a predetermined layer of the pixel illustrated in FIG. 1;

FIG. 9 is a plan view illustrating only predetermined layers of the pixel illustrated in FIG. 1;

FIG. 10 is a plan view of an essential part depicting only the pixel electrode layer and the color filter layer shown in FIG. 5;

FIG. 11 is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device.

FIG. 12 is an equivalent circuit diagram of the pixel shown in FIG.

FIG. 13 is an explanatory diagram of a method for manufacturing the liquid crystal display device shown in FIGS.

FIG. 14 is an explanatory diagram of a method of manufacturing the liquid crystal display device shown in FIGS.

FIG. 15 is a main part plan view showing one pixel of a liquid crystal display section of another active matrix type color liquid crystal display device to which the present invention is applied.

16 is a partially enlarged view of FIG.

FIG. 17 is an explanatory view (a CC cross section of FIGS. 15 and 16 and a DD cross section of FIG. 15) of the method for manufacturing the liquid crystal display device shown in FIGS.

18 is an explanatory diagram (a CC cross section of FIGS. 15 and 16 and a DD cross section of FIG. 15) of the method for manufacturing the liquid crystal display device shown in FIGS.

[Explanation of symbols]

 SUB: transparent glass substrate GL: scanning signal line DL: video signal line GI: insulating film GT: gate electrode AS: i-type semiconductor layer SD: source electrode or drain electrode PSV: protective film BM: light shielding film LC: liquid crystal TFT: thin film transistor ITO: transparent pixel electrode g, d: conductive film Cadd: storage capacitance element Cgs: parasitic capacitance Cpix: liquid crystal capacitance

Claims (1)

(57) [Claims] A step of forming a first electrode on a glass substrate; a step of forming a first insulating film covering the first electrode; and a semiconductor layer forming a channel portion of a thin film transistor on the first insulating film. Forming a second and a third electrode facing each other with a gap in a region where the first electrode is present on the semiconductor layer;
A step of patterning the second electrode so as to have a first region overlapping the first electrode and a second region not overlapping the first electrode; the first insulating film and the second and third electrodes; Forming a second insulating film covering the second electrode; providing an opening in the second insulating film in the second region to connect the second electrode and the pixel electrode; and forming the second insulating film. Forming a transparent pixel electrode provided on the second electrode and partially overlapping the second electrode, wherein the second electrode is formed of a transparent conductive film. .