JP2586729B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for a read-only memory.

[Conventional technology]

FIG. 4 shows an example of a read-only memory (ROM) which is one of the conventional semiconductor memory devices of this kind.

In FIG. 4, the conventional semiconductor memory device includes an address buffer circuit 1, an X decoder circuit 2, a Y decoder circuit 3, a memory cell array unit 4, a Y selector 5 for selecting a digit line, and a sense amplifier 6. , And the output buffer circuit 7.

The memory cell array unit 4 is configured by arranging a plurality of memory cells in a matrix, but here, for convenience of explanation, only one selected memory cell M1 is shown.

Here, the read voltage V _G is applied to the gate of a selected memory cell M1, also, the drain is connected to the digit line Y1. This digit line is connected to the input of the sense amplifier 6.

At the time of the storage operation, the memory cell M1 selectively sets the threshold voltage V _T to either V _TL at the low level “L” or V _TH at the high level “H”, whereby “ 1 "
Alternatively, information of “0” can be stored.

Here, the threshold voltage V _TL, V _TH of the memory cell M1, and sets the gate voltage V _G at the time of reading, as follows.

That is, _{V TL <V G <V TH} .

If the threshold voltage of the selected memory cell M1 is V
If _TL, from V _TL <V _G, the memory cell M1 is conductive and by flowing current to the digit line Y1, the voltage of the digit line Y1 drops. Therefore, the output becomes low level “L”.

As described above, a memory cell that is turned on is called an on-bit.

On the other hand, when reading, the threshold voltage of the selected memory cell M1 is V
If _TH, than V _TH> V _G, the memory cell M1 is non-conducting, no current flows through the digit line Y1, the voltage of the digit line Y1 is raised. Therefore, the output becomes high level “H”.

As described above, a memory cell that is turned off is called an off bit.

Since the voltage difference between the digit lines generated when the on-bit is selected and when the off-bit is selected is very small, it is well known that this voltage difference is amplified by the sense amplifier circuit unit 6 so as to obtain an output O1 of a required level. It is.

As described above, by selectively setting one of the high and low binary threshold voltages of the memory cell at the time of storage, 1-bit data consisting of “L” or “H” can be stored. Can store and read.

Recently, with the progress of semiconductor technology, it has become possible to arbitrarily set a large number, for example, four threshold voltages in one transistor.

With such an element, a 2-bit cell in which a threshold value is set to four values can be considered as one memory cell.

Then, even if it is simply considered, the mounting density of the memory is 2
Therefore, a semiconductor memory device having a large capacity and a high degree of integration can be easily provided.

However, even if such a 2-bit cell is formed, there is no specific readout circuit, and thus such a semiconductor memory device has not been put to practical use.

[Problems to be solved by the invention]

Since the conventional semiconductor memory device described above does not yet have a specific read circuit for a multi-bit cell of 2 bits or more,
Such a large-capacity, high-integration memory using, for example, 2-bit cells has a disadvantage that it is still at the idea stage and has not been commercialized.

[Means for solving the problem]

The semiconductor memory device according to the present invention is a semiconductor memory device comprising a multi-bit cell storing two or more bits of data corresponding to each potential level of at least four threshold voltages in one memory cell. A reference read voltage output circuit that outputs a reference read voltage that is an intermediate voltage, a voltage of a read output read from the memory cell by the reference read voltage and the reference read voltage, and a threshold voltage A threshold voltage determination circuit for determining whether the reference read voltage is a high threshold voltage or a low threshold voltage; and high and low read voltages corresponding to the high and low threshold voltages, respectively. And a high and low read voltage output circuit for outputting the same.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, the semiconductor memory device of the present invention comprises an address buffer circuit 1, an X decoder circuit 2, a Y decoder circuit 3, a memory cell array unit 4, a Y selector 5 for selecting a digit line, and a sense amplifier 6 , Two output buffer circuits 7 and 10, a word control section 8, and a data latch circuit 9.

The data latch circuit 9 has a function of holding data until the next address switching by controlling the data latch signal DL.

The word control unit 8 controls the word control signal SW to
A circuit which receives an output signal S1 from the data latch 9 and selectively controls a read voltage applied to a memory cell to either a low-level read voltage _VGL or a high-level read voltage _VGH .

The components other than those described above are the same as those described in the above-described conventional technique except for the memory cell array section described below.

The memory cell array unit 4 is configured by arranging a plurality of memory cells in a matrix, but here, for convenience of explanation, only one selected memory cell M1 is shown.

The memory cell M1 is a so-called 2-bit cell that stores 2-bit data, one of “LL”, “LH”, “HL”, and “HH”.

This type of 2-bit cell can be realized by setting four threshold voltages of transistors.

For example, taking a read-only memory (ROM) as an example, in a memory cell for a general mask ROM, desired four thresholds are set by two well-known ion implantation methods,
It can be set as follows by mixing two types of impurities.

The memory cell has a configuration in which an N-type diffusion layer is formed on a P-type substrate.

First, in a first step, a Group 5 element such as phosphorus is mixed using a first mask.

Next, a Group 3 element such as boron is mixed with the second mask.

Depending on the presence or absence of impurities, two threshold values can be set in each step. By performing two steps, four threshold values can be set.

The four threshold values thus set, V _TLL , V _TLH , V _THL , V
An example of _THH is as follows.

That is, V _TLL = −3V <V _TLH = 1V <V _THL = 3V <V _THH =
7V.

Next, the read voltage V _G, can of course arbitrarily set within the range of the ground potential GND and the power supply voltage VC.

In this embodiment, the following three read voltages are used: a reference read voltage V _GM , a low-level read voltage V _GL , and a high-level read voltage V
Set _GH respectively.

The relationship between the threshold voltage and the read voltage is as follows. That is, V _TLL <V _GL <V _TLH <V _GM <V _THL
<V _GH <V _THH .

FIG. 2 shows a truth table in the case where data of a 2-bit memory cell having the above four threshold voltages is read with the above three read voltages.

 Next, the operation of the present embodiment will be described.

FIG. 3 is a time chart of the circuit of the present embodiment shown in FIG.

First, threshold V _TLL or V _TLH of the selected memory cell M1
For the relative reference read voltage V _GM, a _{V TLL, V TL <V GM} . Therefore, the memory cell M1 is turned on, the output signal S1 becomes low level "L", and the output buffer circuit 7 outputs "L" as the output O1.

Here, the data latch circuit 9 holds this data "L" until the next address switching under the control of the data latch signal DL, and continues to output the output signal S1.

Subsequently, after it is determined from the level of the output signal S1 that the output of the selected memory cell M1 is “L”, the word control signal SW receives the level information and the word control unit 8 causes the low-level read voltage V _{GL to be} output. Is applied to the gate of the memory cell M1.

As a result, since V _TLL <V _GL <V _TLH , the memory cell M
When the threshold voltage of 1 is _VTLL , the memory cell M1 is turned on, the output signal S2 becomes “L”, and the output buffer circuit 10 outputs “L” as the output O2.

When the threshold voltage of the memory cell M1 is _VTLH , the memory cell M1 becomes an off bit, the output signal S2 becomes "H", and the output buffer circuit 10 outputs "H".

Next, the threshold voltages of the selected memory cell M1 are V _THL and V _THH
In the case of, V _GM <V _THL , V _THH with respect to the reference read voltage V _GM . Therefore, the memory cell M1 becomes an off bit,
The output signal S1 becomes high level “H” and the output buffer circuit 7
Outputs a high level "H" as the output O1.

As in the case described above, the data latch circuit 9
This data “H” is held until the next address switching.

Subsequently, after it is determined from the level of the output signal S1 that the output of the selected memory cell M1 is "H", the word control unit 8 sends the high-level read voltage _VGH to the gate of the memory cell M1 based on this level information. Is applied.

As a result, since V _THL <V _GH <V _THH , the memory cell M
When the threshold voltage of 1 is V _THL , the memory cell M1 is turned on, the output signal S2 becomes “L”, and the output buffer circuit 10 outputs “L” as the output O2.

When the threshold voltage of the memory cell M1 is V _THH , the memory cell M1 becomes an off bit, the output signal S2 becomes “H”, and the output buffer circuit 10 outputs “H” as the output O2.

The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments, and various modifications can be made.

〔The invention's effect〕

As described above, the present invention has an effect of realizing a read circuit of a multi-bit memory cell.

Therefore, there is an effect that a large-capacity and high-integration semiconductor memory device using a multi-bit cell can be put to practical use.

[Brief description of the drawings]

1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing truth values of the circuit shown in FIG. 1, FIG. 3 is an operation time chart of the circuit shown in FIG. FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device. 1 ... address buffer circuit, 2 ... X decoder circuit,
3... Y decoder circuit, 4... Memory cell array section, 5
... Y selector, 6 sense amplifier, 7, 10 output buffer circuit, 8 word control unit, 9 data latch circuit.

Claims (1)

(57) [Claims] 1. A semiconductor memory device comprising a multi-bit cell storing two or more bits of data corresponding to each potential level of at least four threshold voltages in one memory cell, wherein the intermediate value of the threshold voltage A reference read voltage output circuit for outputting a reference read voltage, which is a voltage of the reference read voltage, comparing a voltage of a read output read from the memory cell with the reference read voltage and the reference read voltage; A threshold voltage determination circuit for determining whether the read voltage is a high threshold voltage or a low threshold voltage; and outputting a high and low read voltage corresponding to the high and low threshold voltages. A semiconductor memory device having high and low read voltage output circuits.