JP2553665B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2553665B2
JP2553665B2 JP63241350A JP24135088A JP2553665B2 JP 2553665 B2 JP2553665 B2 JP 2553665B2 JP 63241350 A JP63241350 A JP 63241350A JP 24135088 A JP24135088 A JP 24135088A JP 2553665 B2 JP2553665 B2 JP 2553665B2
Authority
JP
Japan
Prior art keywords
container
conductor wiring
wiring layer
semiconductor element
concave portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63241350A
Other languages
Japanese (ja)
Other versions
JPH0289348A (en
Inventor
久 中岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP63241350A priority Critical patent/JP2553665B2/en
Publication of JPH0289348A publication Critical patent/JPH0289348A/en
Application granted granted Critical
Publication of JP2553665B2 publication Critical patent/JP2553665B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/701Tape-automated bond [TAB] connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明はフィルムキャリア方式半導体素子のプリント
基板への実装に用いる半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for mounting a film carrier type semiconductor element on a printed board.

従来の技術 従来、フィルムキャリア実装方式における半導体素子
のプリント基板上への実装方法としては、フィルム状態
でのアウターリードボンディングが行なわれていた。以
下第3図により従来例を説明する。
2. Description of the Related Art Conventionally, as a method of mounting a semiconductor element on a printed board in a film carrier mounting method, outer lead bonding in a film state has been performed. A conventional example will be described below with reference to FIG.

第3図において、21は半導体素子、22はバンプ、23は
フィルムキャリア、24はインナーリード、25はアウター
リード、26はプリント基板上導体配線層、27はプリント
基板、28は封止剤、29は外被材である。まず、半導体素
子21をインナーリード24に接合した後、半導体素子21お
よびインナーリード24を封止剤28により封止した一連の
フィルムキャリアより一素子分のフィルムキャリアを打
ち抜き、プリント基板27上の導体配線層26上に移送す
る。この後、加熱圧着等によりフィルムキャリア23のア
ウターリード25とプリント基板上導体配線層26とを接合
して、外被材29により覆う。
In FIG. 3, 21 is a semiconductor element, 22 is a bump, 23 is a film carrier, 24 is an inner lead, 25 is an outer lead, 26 is a conductor wiring layer on a printed circuit board, 27 is a printed circuit board, 28 is a sealant, and 29 is a sealant. Is a jacket material. First, after bonding the semiconductor element 21 to the inner lead 24, a film carrier for one element is punched out from a series of film carriers in which the semiconductor element 21 and the inner lead 24 are sealed with a sealant 28, and a conductor on the printed circuit board 27. Transfer to the wiring layer 26. After that, the outer leads 25 of the film carrier 23 and the conductor wiring layer 26 on the printed circuit board are joined by thermocompression bonding or the like, and the outer cover material 29 is covered.

発明が解決しようとする課題 しかしながら上記の従来の構成では、アウターリード
ボンディング装置がその工程専用であるため、実施にあ
たり、組立設備に経費がかさむという難点を有してい
た。さらに、アウターリードの本数およびピッチが一定
せず、製品によって異なるため、アウターリードボンデ
ィング工程は個別対応となり、接合条件等に経験を要
し、これもフィルムキャリア実装技術の普及の妨げにな
っていた。なお、半導体素子をフィルムキャリアに実装
したままの状態では、素子としての信頼性を保証するこ
とも難しかった。
However, in the above-described conventional configuration, the outer lead bonding apparatus is dedicated to the process, and therefore, there is a problem in that the cost of assembling equipment is high during implementation. Furthermore, since the number and pitch of outer leads are not constant and vary depending on the product, the outer lead bonding process is individually tailored and requires experience in joining conditions, etc., which also hinders the spread of film carrier mounting technology. . It is difficult to guarantee the reliability as an element when the semiconductor element is mounted on the film carrier.

本発明は上記従来の問題点を解決するもので、プリン
ト基板上への実装時の取り扱いが容易であり、実装も従
来の表面実装素子に用いられたのと同様な方法により行
なうことが可能な半導体素子の装置を提供することを目
的とする。
The present invention solves the above-mentioned conventional problems, is easy to handle when mounted on a printed circuit board, and can be mounted by a method similar to that used for a conventional surface mount device. An object of the present invention is to provide a semiconductor device device.

課題を解決するための手段 この目的を達成するために、本発明の半導体装置は、
導体配線層を有し、半導体素子を収納しうる凹部を有す
る容器にアウターリードボンディングし、凹部を封止す
ることによって成型する構成を有している。また、この
とき、凹部に貫通孔を設けておけば、容器凹部の反対側
から樹脂等を封入することができ、気泡の発生等のな
い、より良好な封止が可能である。また、この貫通孔を
放熱板取りつけ孔として用いることもできる。さらに、
容器凹部側壁に傾斜を有するようにすれば、導体配線層
と容器表面との接着状態をより良好とすることができ
る。この上、容器凹部周辺凸部上の導体配線層相互の間
に溝部を設ければ、パッケージをプリント基板導体配線
上に実装する際にはんだが流れて隣り合う導体配線と短
絡する等のトラブルをなくすことができる。なお、容器
や封止部に凹部または凸部または表示を設けておけば端
子番号の識別に使用したり、パッケージをプリント基板
上に実装する際の目印にできる。
In order to achieve this object, the semiconductor device of the present invention,
The structure is such that outer lead bonding is performed on a container having a conductor wiring layer and having a recess for accommodating a semiconductor element, and the recess is sealed to mold. Further, at this time, if a through hole is provided in the concave portion, the resin or the like can be sealed from the side opposite to the concave portion of the container, and better sealing without generation of bubbles or the like is possible. Further, this through hole can also be used as a heat sink mounting hole. further,
If the side wall of the concave portion of the container is inclined, the state of adhesion between the conductor wiring layer and the surface of the container can be improved. In addition, if a groove is provided between the conductor wiring layers on the convex portion around the concave portion of the container, solder may flow when the package is mounted on the conductor wiring of the printed circuit board, resulting in a short circuit with an adjacent conductor wiring. It can be lost. If the container or the sealing portion is provided with a concave portion, a convex portion, or an indication, it can be used for identifying the terminal number or can be used as a mark when the package is mounted on the printed board.

作用 この構成によって、フィルムキャリアに実装された半
導体素子は剛性をもつ基板内に実装され、取り扱いが極
めて容易になる。プリント基板導体配線上への実装もフ
ラットパッケージ等の従来の面実装パッケージと同様に
リフローソルダリング法やベーパーフェイズソルダリン
グ法により行なうことができる。
Action With this configuration, the semiconductor element mounted on the film carrier is mounted on the rigid substrate, and the handling becomes extremely easy. Mounting on the printed circuit board conductor wiring can also be performed by the reflow soldering method or the vapor phase soldering method as in the case of the conventional surface mounting package such as a flat package.

実施例 以下本発明の一実施例について、図面を参照しながら
説明する。
Embodiment An embodiment of the present invention will be described below with reference to the drawings.

第1図aは本発明の第1の実施例における半導体装置
の構成を、第1図bは断面図を示すものである。第1図
において、1は半導体素子、2はバンプ、3はフィルム
キャリア、4は容器、5は導体配線層、6は封止剤、7
は貫通孔、8は容器4凹部周辺凸部上に設けられた溝
部、9は切り欠き部、10は容器凹部側壁である。
FIG. 1a shows the structure of a semiconductor device according to the first embodiment of the present invention, and FIG. 1b shows a sectional view. In FIG. 1, 1 is a semiconductor element, 2 is a bump, 3 is a film carrier, 4 is a container, 5 is a conductor wiring layer, 6 is a sealant, and 7 is a sealant.
Is a through hole, 8 is a groove provided on the convex portion around the concave portion of the container 4, 9 is a notch, and 10 is a side wall of the concave portion of the container.

まず、半導体素子1をインナーリードボンディングし
たフィルムキャリア3を容器4の凹部導体配線層5にア
ウターリードボンディングする。この容器4の材質は剛
性を有し、はんだ付け温度に数秒間さらされても反り・
ひずみ等を生じない耐熱性をもつものであればよく、た
とえばエポキシ系樹脂やセラミックスでよい。また凹部
側壁を第1図に示すように傾斜を有するようにしておけ
ば、容器と導体配線層の接着を良好にできる。この後封
止剤6により凹部の封止を行なう。封止剤6はたとえば
エポキシ系ポッティング樹脂でよい。なお、封止の際、
凹部に設けた貫通孔7からも封止剤6を封入することに
より、封止剤のまわりを良くし、気泡の発生等の無いよ
り良好な封止を行なうことが可能である。また容器4の
凹部周辺凸部表面の導体配線層5相互の間に溝部8を設
けておけば、本半導体パッケージをプリント基板面、導
体配線層上に実装するときに隣り合う導体配線層同志が
短絡するといったトラブルを回避できる。また切り欠き
部9を設けることにより端子番号の識別が行なえる。さ
らに容器凹部側壁10に傾斜を有するようにすることによ
り、容器4と導体配線層5との隅部における接着を良好
にすることができる。
First, the film carrier 3 to which the semiconductor element 1 is inner lead bonded is outer lead bonded to the recessed conductor wiring layer 5 of the container 4. The material of this container 4 is rigid and warps even when exposed to the soldering temperature for several seconds.
Any material may be used as long as it has heat resistance that does not cause distortion, and may be, for example, an epoxy resin or ceramics. If the side wall of the recess is inclined as shown in FIG. 1, the container and the conductor wiring layer can be bonded well. After this, the recess is sealed with the sealant 6. The sealant 6 may be, for example, an epoxy potting resin. In addition, at the time of sealing,
By encapsulating the encapsulant 6 also through the through-hole 7 provided in the recess, it is possible to improve the surroundings of the encapsulant and perform better encapsulation without generation of bubbles or the like. Further, if the groove portion 8 is provided between the conductor wiring layers 5 on the surface of the convex portion around the concave portion of the container 4, the conductor wiring layers adjacent to each other when the semiconductor package is mounted on the printed circuit board surface or the conductor wiring layer. You can avoid troubles such as short circuit. Further, by providing the cutout portion 9, the terminal number can be identified. Furthermore, by making the side wall 10 of the recess of the container inclined, the adhesion between the container 4 and the conductor wiring layer 5 at the corner can be improved.

以下本発明の第2の実施例について図面を参照しなが
ら説明する。
A second embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明の第2の実施例における半導体装置の
構成を示すものである。第2図において、11は容器、12
は放熱板、13は容器11側面に設けられた凹部、14はプリ
ント基板、15はプリント基板14上に形成された導体配線
層、16は切り欠き部である。
FIG. 2 shows the configuration of a semiconductor device according to the second embodiment of the present invention. In FIG. 2, 11 is a container and 12
Is a heat sink, 13 is a recess provided on the side surface of the container 11, 14 is a printed circuit board, 15 is a conductor wiring layer formed on the printed circuit board 14, and 16 is a notch.

まず、第1の実施例と同様な方法によって容器11に半
導体素子を接合し、凹部を封止した後、凹部貫通孔より
封止する際に放熱板12を取りつけたものである。この放
熱板上に表示を施し、半導体素子の識別に用いてもよ
い。また、容器11の側面に凹部13を設けることにより、
プリント基板14上の導体配線層15上に本半導体パッケー
ジを実装する際の位置あわせの目印に用いることができ
る。切り欠き部16は第1の実施例と同様に、端子番号を
識別するために用いている。
First, the semiconductor element is joined to the container 11 by the same method as in the first embodiment, the recess is sealed, and then the heat dissipation plate 12 is attached when sealing through the recess through hole. You may display on this heat sink and use it for identification of a semiconductor element. Further, by providing the concave portion 13 on the side surface of the container 11,
It can be used as a positioning mark when the present semiconductor package is mounted on the conductor wiring layer 15 on the printed board 14. The notch 16 is used to identify the terminal number, as in the first embodiment.

なお、実施例においては、双方とも導体配線層を容器
凹部面上のみに形成したが、両面に形成した構成であっ
てもよい。また半導体素子と容器凹部導体配線層との接
合方法はフィルムキャリア方式でなくてもよく、たとえ
ばワイヤボンディングによってもよい。
In each of the embodiments, the conductor wiring layer is formed only on the concave surface of the container, but it may be formed on both surfaces. The method of joining the semiconductor element and the container recessed conductor wiring layer may not be the film carrier method, but may be wire bonding, for example.

発明の効果 以上のように本発明は凹部を有する容器表面上に導体
配線層を形成し、半導体素子を実装したフィルムキャリ
アを接合した後凹部を封止して成型した半導体パッケー
ジとすることにより、取扱いが容易で、他の表面実装パ
ッケージと同様な方法でプリント基板上への実装を行な
うことができるものとするものである。
Effects of the Invention As described above, the present invention forms a conductor wiring layer on the surface of a container having a recess, and after bonding a film carrier on which a semiconductor element is mounted, the recess is sealed to form a semiconductor package, It is easy to handle and can be mounted on a printed circuit board in the same manner as other surface mount packages.

この際、容器凹部に貫通孔を設けることにより封止剤
のまわりを良くし、より良好な封止を行なえる。また、
容器凹部側壁に傾斜を持たせることにより、容器表面と
その上に形成された導体配線層との接着を良好にするこ
とができる。さらに、プリント基板上導体配線層と接着
する側の容器上導体配線層の相互間に溝部を設けること
により、はんだづけ時の短絡をなくすことができる。そ
して、容器または封止部に凹部または凸部または切り欠
き部または表示を設けることにより端子番号の識別の目
印またはプリント基板上実装時の位置あわせの目印とす
ることができる。
At this time, by providing a through hole in the concave portion of the container, the circumference of the sealant can be improved, and better sealing can be performed. Also,
By providing the side wall of the concave portion of the container with an inclination, it is possible to improve the adhesion between the surface of the container and the conductor wiring layer formed thereon. Furthermore, by providing a groove between the conductor wiring layers on the container, which are bonded to the conductor wiring layers on the printed circuit board, it is possible to eliminate a short circuit during soldering. By providing a concave portion, a convex portion, a cutout portion, or an indication on the container or the sealing portion, it can be used as a mark for identifying the terminal number or a mark for alignment when mounting on the printed board.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の第1の実施例における半導体装置の構
成図、第2図は本発明の第2の実施例における半導体装
置の構成図、第3図は従来のアウターリードボンディン
グの構成図である。 1……半導体素子、2……バンプ、3……フィルムキャ
リア、4……容器、5……導体配線層、6……封止剤、
7……貫通孔、8……溝部、9……切り欠き部、10……
容器凹部側壁、13……容器側面凹部。
FIG. 1 is a configuration diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a configuration diagram of a conventional outer lead bonding. Is. 1 ... Semiconductor element, 2 ... Bump, 3 ... Film carrier, 4 ... Container, 5 ... Conductor wiring layer, 6 ... Sealant,
7 ... through hole, 8 ... groove, 9 ... notch, 10 ...
Side wall of the concave part of the container, 13 ...

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体素子を収納しうる凹部を備え、上記
凹部から周辺の凸部にわたる導体配線層を表面上に形成
した剛性容器により、上記凹部に上記半導体素子を配
し、その電極と上記導体配線層とを接続し、上記凹部を
封止剤で埋めた半導体装置であって、上記凹部周辺の凸
部表面上に形成した導体配線層で、互いに隣接した導体
配線層相互の間に溝部を有することを特徴とする半導体
装置。
1. A rigid container having a concave portion capable of accommodating a semiconductor element and having a conductor wiring layer extending from the concave portion to a peripheral convex portion on a surface thereof is arranged with the semiconductor element in the concave portion, and the electrode and the electrode are provided. A semiconductor device in which a conductor wiring layer is connected and the recess is filled with a sealant, wherein the conductor wiring layer is formed on the surface of the protrusion around the recess, and a groove portion is formed between adjacent conductor wiring layers. A semiconductor device comprising:
JP63241350A 1988-09-27 1988-09-27 Semiconductor device Expired - Lifetime JP2553665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63241350A JP2553665B2 (en) 1988-09-27 1988-09-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63241350A JP2553665B2 (en) 1988-09-27 1988-09-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0289348A JPH0289348A (en) 1990-03-29
JP2553665B2 true JP2553665B2 (en) 1996-11-13

Family

ID=17072990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63241350A Expired - Lifetime JP2553665B2 (en) 1988-09-27 1988-09-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2553665B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2677242B2 (en) * 1995-04-27 1997-11-17 日本電気株式会社 Semiconductor device and manufacturing method thereof
KR100240748B1 (en) * 1996-12-30 2000-01-15 윤종용 Semiconductor chip package having substrate and manufacturing method thereof, and stack package
KR100447226B1 (en) * 2001-10-24 2004-09-04 앰코 테크놀로지 코리아 주식회사 Semiconductor Package contained chip

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5481454U (en) * 1977-11-19 1979-06-09
JPS57178449U (en) * 1981-05-06 1982-11-11
JPS60216571A (en) * 1984-04-11 1985-10-30 Mitsubishi Electric Corp Semiconductor device
JPS619849U (en) * 1984-06-25 1986-01-21 カシオ計算機株式会社 circuit board

Also Published As

Publication number Publication date
JPH0289348A (en) 1990-03-29

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