JP2502406Y2 - Line error counting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a line error counting device.

[Conventional technology]

In the conventional line error counting device, the line error counting circuit stops counting line errors only during the time when the input signal loss detection circuit generates an input disconnection signal and prohibits erroneous counting.

[Problems to be solved by the device]

In the above-mentioned conventional line error counting device, the miscounting of line errors is prohibited only during the time when the input signal detection signal is generated. Therefore, chattering that occurs when the connector connected to the input signal line is inserted and removed. However, there is a disadvantage that the line is erroneously counted as a line error.

[Means for solving the problem]

The line error counting device of the present invention comprises an input disconnection detection circuit for detecting disconnection of an input signal from an external digital line, a line error detection circuit for detecting an error signal of the digital line, and an output of the line error detection circuit. In a line error counting device having a line error counting circuit for counting signals, a delay circuit delaying each output signal of the input disconnection detection circuit and the line error detection circuit for a predetermined time, and each output signal of the delay circuit A logical product circuit for receiving a direct output signal of the input break detection circuit and outputting a logical signal, and supplying the output signal of the logical product circuit to the line counting circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. First
In the illustrated embodiment, a connector 101 for connecting the input signal line 100, a B / U converter 102 for converting a bipolar input signal into a unipolar signal, a line error detection circuit 103 for detecting a line error of the converted unipolar signal, and a line error Line error counting circuit 104 for counting the number of input signals, input disconnection detection circuit 105 for detecting input signal disconnection, line error detection circuit 1
The delay circuit 106 and 107 delay the output signal of 03 and the output signal of the input disconnection detection circuit 105, respectively, and an AND circuit 108 that prohibits the counting of line errors under the conditions described later.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. It is now assumed that an input signal 201 from the outside has an error pulse due to chattering due to the extraction of the connector 101 at the portion a and an error pulse due to chattering due to the insertion of the connector 101 at the portion b. Input disconnection detection circuit 105 input disconnection detection alarm signal 202
Outputs "H" during normal operation and outputs "L" when an input disconnection is detected.
However, the detection circuit itself delays t ₁ time before outputting “L”. Therefore, at the time of disconnecting the connector 101, after a delay of t ₁ time, that is, a _{1 in} FIG.
At the time of, "L" is output. A signal obtained by further delaying the signal at the time point a1 by the delay circuit 107 for t ₂ time is used as a delay signal 203. In the error pulse signal 204 detected by the line error detection circuit 103, error pulses a3 and b3 due to chattering at the time of extraction and insertion of the connector 101 are detected. Delay circuit 106 for error pulse signal 204
When the signal delayed by t ₃ by
The error pulse is delayed to the positions of a4 and b4. Since the delay circuits 106 and 107 and the AND circuit 108 do not exist in the conventional circuit, they naturally appear at the same positions as a and b of the input signal 201 like the conventional error pulse signal 206. In this case, since the erroneous counting prohibition time region is T ', erroneous counting may occur at the end of this T'. In the circuit of this embodiment, even one of the two signals, the delay signal 203 delayed by the delay time t ₂ from the input disconnection detection alarm signal 202 and the input disconnection detection alarm signal 202 from the input disconnection detection circuit 105, is “L”. The AND circuit 108 is arranged so as to prohibit erroneous counting of the line error counting circuit 104 at the time of outputting. Therefore, as compared with the conventional circuit, the erroneous counting prohibition time region is expanded. The error pulse signal 204 detected by the line error detection circuit 103 is also delayed by the delay circuit 106. That is, since the error count is finally expanded to the false count prohibition time region T, chattering that occurs when the connector is inserted or removed falls within this prohibition time region T, and the count signal 207 of the line counting circuit 104 is not mistakenly counted as a line error.

[Effect of device]

As described above, according to the present invention, by providing the circuit for delaying the input disconnection detection signal and the line error detection signal and the logical product circuit, chattering that occurs at the time of inserting and removing the connector for connecting the input signal line is performed. Incorrect counting of line errors can be prohibited. Therefore, there is an effect that the reliability of the line error count value is increased and the reliability of the host network performance monitoring device or the like that uses this count value is increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of this embodiment. 100 …… input signal line, 101 …… connector, 102 …… B / U converter, 103 …… line error detection circuit, 104 …… line error counting circuit, 105 …… input disconnection detection circuit, 106,107 ……
Delay circuit, 108 ... AND circuit, 201 ... Input signal,
202 …… Input disconnection detection alarm signal, 203,205 …… Delay signal, 204 …… Error pulse signal, 206 …… Error pulse signal of conventional circuit, 207 …… Count signal.

Claims (1)

(57) [Scope of utility model registration request] 1. An input disconnection detection circuit for detecting disconnection of an input signal from an external digital line, a line error detection circuit for detecting an error signal of the digital line, and an output signal of the line error detection circuit. In a line error counting device having a line error counting circuit,
A delay circuit that delays each output signal of the input disconnection detection circuit and the line error detection circuit by a predetermined time;
An AND circuit for inputting each output signal of the delay circuit and a direct output signal of the input disconnection detection circuit to output a logical signal, and supplying the output signal of the AND circuit to the line counting circuit A line error counting device characterized by: