JP2024502641A - Power converter control with snooze mode - Google Patents

Abstract

In one example, apparatus (110) includes a control signal generator (202) and a snooze mode controller (204). The control signal generator includes an error amplifier (208) having a first output, a first input, a second input, and a first snooze input; a first comparator (210) having three inputs, and a fourth input, and a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input. a second comparator (212) having a second comparator (212). The control signal generator also has a fourth output and a logic circuit input, a logic circuit (218) having a first input of the logic circuit input coupled to a second output, a fifth output and a seventh output. a pulse generator (220) having a seventh input coupled to the fourth output. The snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

Description

A switched mode power supply (SMPS) is one or more energy storage elements (such as inductors, transformer inductances, and/or capacitors) coupled via switch nodes/terminals to enable coupling to a load. Power is transferred from the input power source to the load by switching the power transistor or other switching element. The power transistor may be included in a power converter, which may include or be coupled to an energy storage element. The SMPS may include an SMPS controller for providing one or more gate drive signals to the power transistors.

The input voltage to the converter can be greater than, less than, or equal to the output voltage. If the input voltage is greater than the output voltage, the converter may be called a "step-down" converter/regulator or a "buck converter." If the input voltage is less than the output voltage, the converter/regulator may be called a "step-up" converter/regulator or a "boost converter." If a converter/regulator can perform both step-up and step-down functions, it may be referred to as a "buck-boost converter."

In one example, an apparatus includes a control signal generator and a snooze mode controller. The control signal generator includes an error amplifier having a first output, a first input, a second input, and a first snooze input. The control signal generator also includes a first comparator having a second output, a third input coupled to the first output, and a fourth input. The control signal generator also includes a second comparator having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input. The control signal generator also includes a logic circuit having a fourth output and a logic circuit input, the first input of the logic circuit input being coupled to the second output. The control signal generator also includes a pulse generator having a fifth output and a seventh input, the seventh input being coupled to the fourth output. The snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

In one example, an apparatus includes a control signal generator and a snooze mode controller. The control signal generator determines by an error amplifier an error signal indicative of a difference between the reference signal and a feedback signal representative of the output voltage of the power converter, the value of the error signal being greater than the signal representative of the current of the power converter. The power converter is configured to determine whether the power converter is the same, provide a comparison result, and provide a control signal for controlling the power converter based on the comparison result. The snooze mode controller is configured to disable at least a portion of the error amplifier in response to determining that the value of the reference voltage scaled by the scaling factor is greater than the feedback signal.

In one example, a system includes a load, a power converter, and a controller. A power converter is coupled to a load. A power converter is configured to switch power from a power source to a load. A controller is coupled to the power converter. The controller is configured to implement control via the power converter. The controller includes a control signal generator that includes an error amplifier. The control signal generator determines, by means of an error amplifier, an error signal indicative of the difference between the reference signal and a feedback signal representative of the output voltage of the power converter, and determines whether the value of the error signal is greater than a signal representative of the current of the power converter. The power converter is configured to provide a comparison result, and provide a control signal for controlling the power converter based on the comparison result. The snooze mode controller is configured to disable at least a portion of the error amplifier in response to determining that the value of the reference voltage scaled by the scaling factor is greater than the feedback signal.

FIG. 1 is a block diagram of an example system.

FIG. 2 is a block diagram of an example controller.

FIG. 2 is a schematic diagram of an example error amplifier.

FIG. 2 is a schematic diagram of an example fast drop detection circuit.

FIG. 2 is a diagram of example signal waveforms.

FIG. 2 is a diagram of example signal waveforms.

FIG. 3 is a diagram of example signal waveforms.

FIG. 2 is a diagram of example signal waveforms.

FIG. 2 is a diagram of example signal waveforms.

FIG. 2 is a diagram of example signal waveforms.

Switched mode power supply (SMPS) controllers switch power transistors to form circuit arrangements with energy storage elements and provide load current to the load and/or output capacitor to maintain a regulated output voltage. Alternatively, although not shown herein, at least some of the power transistors are implemented as passive switches, such as diodes. A power transistor may be coupled to the energy storage inductor via a switch node/terminal during charging or discharging switching states of the power converter. In at least some examples, the energy storage inductor is switched between a charging switching state and a discharging switching state by the SMPS controller to provide inductor current (e.g., current through the energy storage inductor) to the load and the output capacitor. , maintain a regulated output voltage. As mentioned above, in at least some examples, one or more power transistors are replaced by passive switches, which react based on characteristics of the received input signal and are not switched by the SMPS controller. In some examples, an SMPS may be configured to operate as a constant current source with an energy storage element but no output capacitor. Power converters periodically repeat sequences of switching states (such as "on" and "off" states). A single on/off cycle may be called a switching cycle.

The power transistor may be implemented as a field effect transistor (FET), such as a metal oxide field effect transistor (MOSFET), or any other suitable solid state transistor device, such as a bipolar junction transistor (BJT), etc. Power converters can have a variety of architectures, each with specific functions such as buck, boost, and buck-boost. A boost topology power converter is described herein. However, the present disclosure is equally applicable to power converters of buck and/or buck-boost (inverting and/or non-inverting) topology. This specification may also relate to other circuit architectures that provide a regulated output voltage (VOUT).

To control the power converter, the SMPS controller provides control signals based on the control mode in which the SMPS controller is implemented. The control mode may be current mode control, voltage mode control, valley control, peak control, average control, etc. Valet control is described herein. However, this specification is equally applicable to other control modes. The SMPS controller may provide control signals to the driver or logic circuitry coupled to the driver, and the driver may provide gate control signals to the gates of the power transistors to control the mode of operation of the power converter. The gate control signal received by the power transistor controls the switching state of the power transistor, such as whether the power transistor is conducting (eg, on) or non-conducting (eg, off). Each state of the power converter relates to a particular combination of conducting and non-conducting power transistors. To change the mode of operation of the power converter, the SMPS controller modifies the sequence of switching states that it commands the power transistors to assume. In at least some examples, the SMPS controller includes a hardware component arrangement such that the values of the control signals are determined based on these hardware component arrangements.

Some use cases for SMPS benefit from quiescent current reduction. Quiescent current is the current consumed by the SMPS itself, independent of the current provided by the SMPS to the load. For example, quiescent current may be the current consumed by the SMPS in no-load or light (eg, low) load current conditions. If the power source from which the SMPS draws current is a consumable power source, such as a battery, reducing the quiescent current of the SMPS reduces the power drawn from the power source and reduces the utilization of the power source until recharging or replacement. Possible lifespan can be extended. The quiescent current of the SMPS is By reducing the energy consumption of the SMPS, the costs associated with using the SMPS may be reduced.

Certain aspects herein relate to an SMPS that implements a sleep mode. Sleep mode may reduce the clock signal (SNOOZE_CLK) on which VOUT monitoring is based. For example, in response to VOUT remaining within regulation for a programmed number of cycles or periods of an oscillator signal (CLK), the SMPS determines that the rate of decrease in the value of VOUT is such that SNOOZE_CLK may be slower. It can be determined that it is the same as . By slowing SNOOZE_CLK, the quiescent current of the SMPS may be reduced compared to applications that do not slow SNOOZE_CLK.

In at least some examples, SNOOZE_CLK may be determined as a combination of multiple signals. For example, SNOOZE_CLK may be determined by performing a logical OR operation between multiple signals. The signals may include a zero crossing detection signal (ZCD), CLK, and a fast drop detection signal (FDD). In at least some examples, the voltage representing the inductor current of the power converter reaches the value of the error signal (Vea) provided by the error amplifier based on the reference signal (Vref) and the feedback signal (Vfb) based on VOUT. In response to reaching zero before zero, ZCD is asserted in the valley mode control system. CLK may be provided by an oscillator with a programmed adjustable period according to the SMPS application or use. In at least some examples, FDD may be provided by a circuit that monitors the value of VOUT and provides a periodic signal having a frequency proportional to the rate at which the value of VOUT decreases. Conversely, in some systems, FDD may be provided by a circuit that monitors the value of VOUT and provides a periodic signal with a frequency proportional to the rate at which the value of VOUT increases. In such an example, FDD may be renamed as a fast rising detection signal. In response to SNOOZE_CLK being asserted, the SMPS may enter snooze or sleep mode.

In some examples, the error amplifier is configured to cause the SMPS to provide a pulse of current in response to the error amplifier receiving a signal to exit snooze mode. The error amplifier may further include a compensating signal path and a non-compensating signal path, the non-compensating signal path responding more quickly to transient changes in the value of the signal than the compensating signal path.

FIG. 1 is a block diagram of an example system 100. In at least some examples, system 100 represents any electronic device that includes an SMPS 102 configured to switch power from a power source 104 to a load 106. For example, system 100 may be an Internet of Things (IoT) device, a sensor, or any other suitable electronic device. In at least some examples, power source 104 is a battery. In some examples, SMPS 102 includes a power converter 108 and a controller 110. Controller 110 is configured to control power converter 108 to switch power provided by power source 104 to load 106 . For example, controller 110 may receive Vref and control power converter 108 to provide VOUT to load 106. While VOUT is within regulation, VOUT has a value approximately equal to Vref.

In one example of system 100, power source 104 is coupled to power converter 108, and power converter 108 is coupled to load 106 and controller 110. Power converter 108 is configured to receive VIN from power source 104 and provide VOUT to load 106 based on the VIN, and to implement control by controller 110 on power converter 108 . Controller 110 may receive Vref and provide a control signal to power converter 108 that may adjust VOUT to have a value approximately equal to Vref. In some examples, controller 110 provides control signals to power converter 108. In other examples, controller 110 provides control signals to a driver (not shown) that drives power converter 108 based on the control signals.

Controller 110 may include a snooze mode. In at least some examples, the snooze mode may reduce the quiescent current draw from the power source 104 of the SMPS 102 compared to the SMPS 102 while the snooze mode is not active. Snooze mode causes the SMPS 102 to determine that VOUT remains within regulation for a programmed number of cycles of CLK, which is a threshold amount greater than a target voltage (e.g., such as represented by Vref). In response, it may be activated. In at least some examples, while SMPS 102 is in snooze mode, controller 110 does not monitor VOUT to determine the value of VOUT or monitor signals representative of VOUT, such as Vfb relative to Vref. In response to expiration of SNOOZE_CLK, controller 110 may determine the value of VOUT (or Vfb) relative to Vref and control power converter 108 based on that determination. In at least some examples, SNOOZE_CLK has a value based on the rate of change of VOUT (e.g., a frequency proportional to the rate of change of VOUT), a fixed frequency, or the value of an inductor current in an inductor (not shown) of power converter 108. It is programmable to have As discussed above, SNOOZE_CLK may be controlled to have a lower frequency in response to VOUT remaining within regulation for a programmed number of CLK cycles. VOUT remaining within regulation for a programmed number of CLK cycles may indicate, at least in some instances, that the value of VOUT is changing slowly. In response to the value of VOUT changing at a rate that exceeds the programmed rate of change, SNOOZE_CLK may be controlled to have a higher frequency. In at least some examples, reducing the frequency of SNOOZE_CLK in response to VOUT remaining within regulation for a programmed number of CLK cycles reduces the quiescent current draw of the SMPS 102.

FIG. 2 is a block diagram of an example controller 110. Although shown as a component of SMPS 102, in various other examples controller 110 may be a component of another device, circuit, or system. In at least some examples, controller 110 includes a control signal generator 202, a snooze mode controller 204, and an FDD circuit 206. In at least some examples, controller 110 receives signals representative of Vref, Vfb, and current in power converter 108 (IL), and generates a control signal (CONTROL) based at least in part on Vref, Vfb, and IL. provide. In at least some examples, other control signals are obtained based on the value of CONTROL, such as a logical inverse of the value of CONTROL. In at least some examples, control signal generator 202 includes error amplifier 208, comparator 210, comparator 212, timer 214, timer 216, logic circuit 218, and pulse generator 220. In at least some examples, snooze mode controller 204 includes a clock combiner 222, a comparator 224, logic circuit 226, and logic circuit 228.

In at least some example architectures of control signal generator 202, error amplifier 208 receives Vref at a first input (e.g., a positive or non-inverting input) and receives Vref at a second input (e.g., a negative or inverting input). is configured to receive Vfb at. In some examples, Vfb has a value determined based on VOUT (eg, so that Vfb is the output signal of a voltage divider that has VOUT as an input signal). In other examples, Vfb is substantially the same value as VOUT (eg, in some implementations VOUT is used as Vfb). The output of error amplifier 208 is coupled to a first input (eg, a positive or non-inverting input) of comparator 210. In some examples, error amplifier 208 receives a snooze control signal (SNOOZE) and, in response to SNOOZE being asserted, configures the snooze input to be turned off (e.g., non-functional). have Comparator 210 is configured to receive IL at a second input (eg, a negative or inverting input). Comparator 212 receives IL at a first input (e.g., a positive or non-inverting input) and receives a signal having a value of approximately 0 volts (V) at a second input (e.g., a negative or inverting input). configured to do so. In some examples, comparator 212 is a gated comparator that receives SNOOZE and has a snooze input configured to be turned off (e.g., non-functional) in response to SNOOZE being asserted. It is. In at least some examples, one or both of error amplifier 208 and/or comparator 212 receives the inverse of SNOOZE (denoted as SNOOZE_Z). SNOOZE_Z may be provided according to any suitable process or hardware architecture. Although not illustrated herein, in at least one example, SNOOZE_Z is provided by an inverter circuit 230 that receives SNOOZE as an input. In such an example, an inverter circuit may be coupled between the output of logic circuit 228 and the snooze input of error amplifier 208. In at least some examples, timer 214 is configured to provide a signal TOFF and timer 216 is configured to provide a signal TOFF_MAX. In at least some examples, TOFF is asserted in response to expiration of the sum of the off-time of power converter 108 and the programmed gap or delay time between control of the power transistors of power converter 108. In at least some examples, TOFF_MAX is asserted in response to expiration of a maximum off-time for power converter 108. Timer 214 has an input coupled to the second output of error amplifier 208. For example, in response to timer 214 receiving a ZCD with an asserted value, timer 214 may begin counting and continue counting for a programmed period of time (some number of In an example, TOFF may be provided with an asserted value after about 10 μs, for example. Similarly, in response to timer 216 receiving a ZCD with an asserted value, timer 216 may begin counting after a programmed period of time after receiving a ZCD with an asserted value. TOFF_MAX may be provided with an asserted value. In at least some examples, providing TOFF is also based on Vea provided by error amplifier 208, such as inversely proportional to signal Vpfm, as described hereinafter. Comparator 210, timer 214, and timer 216 each have an output coupled to an input of logic circuit 218. Logic circuit 218 has an output coupled to an input of pulse generator 220, which has an output where CONTROL is provided. In at least some examples, logic circuit 218 performs a logical OR function between its input signals to assert the logic circuit 218 in response to any one or more input signals of logic circuit 218 being asserted. provides an output signal.

In at least some example architectures of snooze mode controller 204, clock combiner 222 has a first input coupled to the output of comparator 212 to receive ZCD and an oscillator (FIG. (not shown) and a third input coupled to the output of FDD circuit 206. The output of snooze mode controller 204, where SNOOZE_CLK is provided, is coupled to comparator 224. Comparator 224 is configured to receive Vref multiplied by a scaling factor at a first input (eg, a positive or non-inverting input) and Vfb at a second input (eg, a negative or inverting input). In at least some examples, the scaling factor is 1.01. In other examples, the scaling factor is any suitable value. The output of comparator 224 is coupled to the input of logic circuit 226. An output of logic circuit 226 is coupled to an input of logic circuit 228 , which has another input coupled to the output of timer 216 and an output coupled to error amplifier 208 provided with SNOOZE. In at least some examples, logic circuit 226 is an inverter, its logical inverse. In at least some examples, logic circuit 228 performs a logical AND function between its input signals to generate an output signal that is asserted in response to each of the input signals of logic circuit 228 being asserted. provide.

In one example of operation of controller 110, error amplifier 208 amplifies the difference between the value of Vref and the value of Vfb to provide Vea. Comparator 210 compares Vea and IL and provides an output signal COMP having an asserted value in response to the value of IL being less than Vea. In response to the assertion of COMP, logic circuit 218 provides an asserted signal that causes pulse generator 220 to control CONTROL with an asserted value for the programmed on-time determined by pulse generator 220. I will provide a. In at least some examples, in response to assertion of CONTROL, a high side power transistor (not shown) of power converter 108 is controlled to turn off and a low side power transistor (not shown) of power converter 108 is controlled to turn off. is controlled so that it is turned on. In at least some examples, comparator 212 asserts ZCD in response to IL decreasing to zero before increasing to reach Vea. In at least some examples, in response to assertion of ZCD, the high side power transistor of power converter 108 is controlled to turn off, such as via assertion of TOFF or TOFF_MAX. In response to the value of ZCD increasing to zero before reaching Vea, controller 110 controls the off-time of power converter 108 based on Vea. ) controls power converter 108 to operate according to.

While power converter 108 is operating according to the PFM, the off-time of power converter 108 may be a function of Vea. Timer 214 may determine the off time and provide TOFF according to any suitable process or using any suitable hardware architecture based on Vea and/or any other suitable signal or consideration. , the scope of which is not limited herein. In at least some examples, timer 214 determines the amount of time (e.g., a gap time) that the low side power transistor of power converter 108 waits after Vea and the high side power transistor of power converter 108 are turned off. The off time may be determined based on the gap time that defines the off time. In response to expiration of the total off time determined based on the gap time and Vea, timer 214 may provide TOFF with an asserted value. In at least some examples, the off time has a value less than or equal to about 10 microseconds. In at least some examples, timer 216 may determine a maximum off time based at least in part on VIN and VOUT. In response to expiration of the maximum off time, timer 216 may provide TOFF_MAX with an asserted value. In at least one example, the maximum off-time is approximately equal to VIN/L x T_HS x T_LS/I_OUT, where L is the inductance of the inductor of power converter 108 and T_HS is the high side power transistor of power converter 108 turned on. time, T_LS is the time that the low side power transistor of power converter 108 is turned on, and I_OUT is the load current of power converter 108. In at least some examples, in response to assertion of either TOFF_MAX, TOFF, or COMP, logic circuit 218 controls pulse generator 220 to provide CONTROL with an asserted value.

In at least some examples, under heavy load conditions, controller 110 may control power converter 108 according to constant on-time valley current control using pulse width modulation (PWM). As used herein, a heavy load condition may exist when load 106 draws more than 100 milliamps (mA) of current from power converter 108. Under medium load conditions, controller 110 may control power converter 108 according to a constant on-time PFM with variable off-time. As used herein, a medium load condition may exist when load 106 draws a current of about 15 mA to about 100 mA from power converter 108. Under light load conditions, controller 110 may control power converter 108 to operate in burst mode with the snooze mode described herein being active during bursts. As used herein, a light load condition may exist when load 106 draws less than about 15 mA of current from power converter 108.

In one example of the operation of snooze mode controller 204, clock combiner 222 provides SNOOZE_CLK with an asserted value in response to an asserted value on ZCD, CLK, or FDD. For example, in at least one implementation, clock combiner 222 performs a clock combination between ZCD, CLK, and FDD in response to any one or more of ZCD, CLK, or FDD having an asserted value. Perform a logical OR operation and provide SNOOZE_CLK with an asserted value. In another example, clock combiner 222 provides SNOOZE_CLK with an asserted pulse whenever a rising edge is detected on ZCD, CLK, or FDD. Comparator 224 may be clocked by SNOOZE_CLK such that comparator 224 may compare its input signals and provide an output signal only while SNOOZE_CLK is asserted. While SNOOZE_CLK is deasserted, comparator 224 may be turned off and disabled, at least in some instances. In at least some examples, comparator 224 may be referred to as a clock dynamic comparator.

In response to SNOOZE_CLK becoming asserted, comparator 224 may compare its input signals (eg, scaled Vref and Vfb) and provide an output signal. In some examples, Vref is scaled to provide hysteresis to snooze mode controller 204 to prevent controller 110 from entering or leaving the snooze mode frequency due to transient signal noise, etc. . In at least some examples, the asserted output signal provided by comparator 224 indicates that the value of VOUT has decreased to within about 1 percent of the programmed value for VOUT, and controller 110 indicates that power converter 108 to provide a burst of current to the load 106. In at least some examples, in response to the output signal provided by comparator 224 being asserted, SNOOZE may be deasserted and SMPS 102 may be removed from snooze mode. Conversely, in response to the output signal provided by comparator 224 being deasserted and TOFF_MAX asserted, SNOOZE may be asserted and SMPS 102 may be placed or maintained in snooze mode. In response to deassertion of SNOOZE, error amplifier 208 and comparator 212 may turn on and become functional, causing controller 110 to control power converter 108 to provide current to load 106.

In one example of the operation of FDD circuit 206, the rate of change of VOUT is monitored and FDD is provided based on that monitoring. For example, FDD circuit 206 may provide FDD as a clock signal having a frequency proportional to the rate of change of VOUT. In response to the rate of change of VOUT increasing, the frequency of the FDD may increase, and in response to the rate of change of VOUT decreasing, the frequency of the FDD may increase until the rate of change of VOUT is too small and the FDD circuit 206 can be reduced until it becomes undetectable. In various examples, FDD circuit 206 may be implemented according to any suitable FDD circuit architecture, the scope of which is not limited herein.

FIG. 3 is a schematic diagram of an example error amplifier 208. Although error amplifier 208 is shown as a component of controller 110, it may be a component of another device, circuit, or system in various other examples. In at least some examples, error amplifier 208 includes amplifier 302, resistor 304, switch 306, capacitor 308, transistor 310, transistor 312, current source 313, switch 314, transistor 316, resistor 317, transistor 318, resistor 319, current source 320, transistor 321, transistor 322, transistor 324, transistor 326, transistor 328, current source 329, resistor 330, capacitor 332, resistor 334, transistor 336, transistor 338, transistor 340, resistor 342, current source 344, transistor 346, resistor 348, comparator 350, offset voltage source 352, switch 354, and pulse generator 356.

In the example architecture of error amplifier 208, amplifier 302 has a first input (e.g., a positive or noninverting input) configured to receive Vref and a second input (e.g., a positive or noninverting input) configured to receive Vfb. for example, a negative or inverting input). Amplifier 302 further has first and second outputs. In at least some examples, amplifier 302 is a differential amplifier. Resistor 304 is coupled at a first terminal to the first output of amplifier 302 and at a second terminal to the top plate of capacitor 308 via switch 306 . In at least some examples, switch 306 is a normally open switch configured to receive and be controlled by SNOOZE_Z. In other examples, switch 306 may be a normally closed switch configured to receive and be controlled by SNOOZE. The bottom plate of capacitor 308 is adapted to be coupled to ground 358. Transistor 310 has a source coupled to the top plate of capacitor 308, a drain adapted to be coupled to voltage source 360, and a gate. Transistor 312 has a gate coupled to the top plate of capacitor 308, a source adapted to be coupled to ground 358, and a drain coupled to the gate of transistor 310. Current source 313 is adapted to be coupled between voltage source 360 and the gate of transistor 310. Switch 314 has a first terminal coupled to the first output of amplifier 302 and a second terminal. In at least some examples, switch 314 is a normally open switch configured to receive and be controlled by SNOOZE_Z. In other examples, switch 314 may be a normally closed switch configured to receive and be controlled by SNOOZE. Transistor 316 has a gate coupled to the second terminal of switch 314, a source coupled to ground 358 through resistor 317, and a drain. Transistor 318 has a gate coupled to the second terminal of switch 314, a source coupled to ground 358 through resistor 319, and a drain provided with Vea. Current source 320 is adapted to be coupled between voltage source 360 and the drain of transistor 316.

Transistor 321 has a gate coupled to the drain of transistor 316, a source coupled to the gate of transistor 316, and a drain. Transistor 322 has a drain, a gate coupled to the drain of transistor 321, and a source adapted to be coupled to voltage source 360. Transistor 324 has a gate coupled to the gate of transistor 322, a source adapted to be coupled to voltage source 360, and a drain. Transistor 326 has a drain, a gate coupled to the drain of transistor 324, and a source adapted to be coupled to ground 358. Transistor 328 has a gate coupled to the gate of transistor 326, a source adapted to be coupled to ground 358, and a drain. Current source 329 is adapted to be coupled between voltage source 360 and the drain of transistor 328. A resistor 330 is coupled between the drain of transistor 328 and the top plate of capacitor 332. The bottom plate of capacitor 332 is adapted to be coupled to ground 358. A resistor 334 is coupled between the drain of transistor 328 and the drain of transistor 336. Transistor 336 further has a source adapted to be coupled to ground 358 and a gate. Transistor 338 has a source coupled to the drain of transistor 328, a drain adapted to be coupled to voltage source 360, and a gate. Transistor 340 has a gate coupled to the drain of transistor 328, a source adapted to be coupled to ground 358 via resistor 342, and a drain adapted to be coupled to the gate of transistor 338. has. Current source 344 is adapted to be coupled between voltage source 360 and the drain of transistor 340. Transistor 346 has a gate coupled to the drain of transistor 328, a source adapted to be coupled to ground 358 via resistor 348, and a drain to which the output of error amplifier 208 is provided. Comparator 350 has a first input (eg, a positive or non-inverting input) configured to receive Vref, a second input (eg, a negative or inverting input), and an output. Offset voltage source 352 is coupled to a second input of comparator 350 and provides a voltage offset to Vfb. Switch 354 is adapted to be coupled between voltage source 360 and the drain of transistor 328. In at least some examples, switch 354 is a normally open switch configured to receive and be controlled by the output signal of comparator 350. Pulse generator 356 has an input configured to receive SNOOZE and an output coupled to the gate of transistor 336.

In one example of the operation of error amplifier 208, amplifier 302, which may be any suitable transconductance amplifier, receives Vref and Vfb, amplifies the difference in value between Vref and Vfb, and provides an output signal COMP_PWM. do. Resistor 304 and capacitor 308 provide compensation to maintain stability in the PWM loop portion of error amplifier 208. Amplifier 302 drives transistor 318 to provide Vea at the drain of transistor 318. transistors 322, 324, 326, where a clamp including transistor 316, resistor 317, current source 320, and transistor 321 maintains the value of COMP_PWM at a minimum or clamped voltage, regardless of the value of Vref or Vfb; and 328 both mirror the current from the source of transistor 321 to the drain of transistor 328 to provide COMP_PFM while the aforementioned clamp is engaged (e.g., COMP_PWM in the absence of the clamp otherwise). may have a smaller value than the clamped voltage). Resistor 330 and capacitor 332 provide compensation to maintain stability of the PFM loop portion of error amplifier 208. A clamp including transistor 338, transistor 340, resistor 342, and current source 344 maintains the value of COMP_PFM at a minimum or clamped voltage regardless of the value of Vref or Vfb. Transistor 346 is driven based on the value of COMP_PFM to provide an output signal Vpfm at the drain of transistor 346. While error amplifier 208 is not in snooze mode, capacitor 308, which may be a compensation capacitor, charges based on COMP_PWM. In at least some examples, in response to error amplifier 208 entering snooze mode, switch 306 opens so that a voltage is maintained on capacitor 308 during snooze mode. A clamp formed by transistor 310, transistor 312, and current source 313 may maintain the voltage held on capacitor 308 at a minimum or clamped voltage while in snooze mode. Also, in response to error amplifier 208 entering snooze mode, switch 314 opens, thereby electrically disconnecting the output of amplifier 302 from the gates of transistors 316, 318 and the source of transistor 321.

In at least some examples, pulse generator 356 is configured to receive SNOOZE and provide a voltage pulse (SNOOZE_EXIT_PULSE) with a programmed width in response to a falling edge of SNOOZE. In at least some examples, the programmed width is about 3 microseconds. In response to the assertion of SNOOZE_EXIT_PULSE for the pulse duration, and while SNOOZE_EXIT_PULSE is asserted, transistor 336 may become conductive, pulling down the gate of transistor 340, thereby reducing the signal COMP_PFM provided at the gate of transistor 340. is approximately equal to the voltage provided at ground 358. In at least some examples, in response to the gate of transistor 340 being pulled down, error amplifier 208 causes controller 110 to control power converter 108 according to PFM control. In at least some examples, a single discontinuous conduction mode (DCM) pulse may be provided to power converter 108 as a gate control signal by transistor 336 pulling down the gate of transistor 340. In some examples, the value of VOUT_COMP_LOW may determine whether error amplifier 208 begins operating in PWM mode or PFM mode after assertion of SNOOZE_EXIT_PULSE. For example, in response to comparator 350 determining that the value of Vref is less than Vfb plus the offset provided by offset voltage source 352, comparator 350 causes VOUT_COMP_LOW to have an asserted value. I will provide a. In at least some examples, the offset is about 1 percent of Vref (eg, if Vfb decreases to less than 99 percent of Vref as a result, VOUT_COMP_LOW is asserted). In response to VOUT_COMP_LOW having an asserted value, switch 354 may close, pulling up the gate of transistor 340 such that the signal COMP_PFM provided at the gate of transistor 340 is pulled up at voltage source 360. Approximately equal to the voltage provided, error amplifier 208 provides Vea based on PWM control (eg, enters a high current mode where PFM mode control is skipped). In other examples, such as when the value of Vref is not less than Vfb plus the offset provided by offset voltage source 352, the DCM pulse may receive the output of controller 110 and/or SNOOZE. , may be provided by other circuits, such as the logic circuits described above, that may provide gate control signals for use in driving the power transistors of power converter 108. For example, in some implementations, the logic circuit may provide a DCM pulse in response to the logic circuit detecting a falling edge transition on SNOOZE, regardless of the output of the error amplifier 208 or the controller 110.

FIG. 4 is a schematic diagram of an example FDD circuit 206. Although shown as a component of controller 110, in various other examples FDD circuit 206 may be a component of another device, circuit, or system. Also, although shown having a particular architecture, in various examples FDD circuit 206 may have any architecture suitable for implementing the functions described herein. In at least some examples, FDD circuit 206 includes current source 402, transistor 404, transistor 406, transistor 408, capacitor 410, switch 412, capacitor 414, transistor 416, transistor 418, resistor 420, capacitor 422, switch 424, It includes a logic circuit 426 and a delay circuit 428.

In the exemplary architecture of FDD circuit 206, current source 402 is adapted to be coupled between the output of power converter 108 and the drain of transistor 404. Transistor 404 has a gate coupled to the drain of transistor 404 and a source adapted to be coupled to ground 358. Transistor 406 has a gate coupled to the gate of transistor 404, a source adapted to be coupled to ground 358, and a drain. Transistor 408 has a drain, a gate coupled to the drain of transistor 406, and a source adapted to be coupled to the output of power converter 108. Capacitor 410 is adapted to be coupled between the output of power converter 108 and the gate of transistor 408. Switch 412 is coupled between the gate of transistor 408 and the gate of transistor 416. Capacitor 414 is adapted to be coupled between the gate of transistor 416 and ground 358. Transistor 416 has a source adapted to be coupled to the output of power converter 108 and a drain. Transistor 418 has a drain coupled to the drain of transistor 416 , a gate coupled to the gate of transistor 404 , and a source adapted to be coupled to ground 358 via resistor 420 . Capacitor 422 is adapted to be coupled between the output of power converter 108 and the source of transistor 418. Switch 424 is adapted to be coupled between the source of transistor 418 and ground 358. Logic circuit 426 has an input coupled to the drain of transistor 418 and an output. Delay circuit 428 has an input coupled to the output of logic circuit 426 and an output. In at least some examples, the output of delay circuit 428 is coupled to switch 412 and switch 424 such that the output signal of delay circuit 428 is provided to switch 412 and switch 424 to control switch 412 and switch 424. It is configured as follows.

In one example of operation of FDD circuit 206, VOUT is capacitively coupled to transistor 416 by capacitors 410 and 414 and capacitively coupled to transistor 418 by capacitor 422. The default output of FDD circuit 206, in at least some instances, is a logic low or deasserted signal. As the value of VOUT decreases, more current flows through transistor 418 than through transistor 416. For example, the gate of transistor 416 is held at ground 358 by capacitor 414. As the value of VOUT received at the source of transistor 416 decreases, the current through transistor 416 decreases. The source of transistor 418 is held at VOUT via capacitor 422. Therefore, as the value of VOUT decreases, the voltage provided at the source of transistor 418 also decreases and the gate-to-source voltage (Vgs) of transistor 418 increases. In response to the Vgs of transistor 418 increasing, the current through transistor 418 also increases, causing the value of the voltage provided at the input of logic circuit 426 to go from approximately VOUT to the value of the signal provided at ground 358. It starts to decrease towards approximately equal values. In response to the current through transistor 418, which is also the current provided at the input of logic circuit 426, reaching a threshold of logic circuit 426, logic circuit 426 trips. In at least some examples, logic circuit 426 implements logic inversion. Accordingly, logic circuit 426 may provide a logic high signal in response to tripping based on the current sunk through transistor 418. In at least some examples, the output signal of logic circuit 426 is FDD. Thus, in at least some examples, the output of logic circuit 426 is coupled to the input of clock combiner 222. Delay circuit 428 may be any suitable delay circuit that receives FDD at an input of delay circuit 428 and provides a reset signal (RST) at an output of delay circuit 428 after a programmed amount of time. In at least some examples, RST has substantially the same value as FDD and is configured to control switch 412 and switch 424 to close to reset FDD circuit 206. Thus, FDD is provided as a PWM signal having a frequency proportional to the rate of change of VOUT while the rate of change of VOUT is within the sensitivity of the FDD circuit 206. In at least some examples, FDD circuit 206 provides an FDD having a frequency that is proportional to the rate of change of VOUT when the rate of change of VOUT is greater than approximately 100 microvolts (μV) per microsecond (μs). Get suitable for. In other examples, FDD circuit 206 may be modified to provide an FDD with a frequency proportional to the rate of change of VOUT if the rate of change of VOUT is somewhat less than about 100 μV/μs.

FIG. 5A is a diagram 505 of an exemplary signal waveform. In at least some examples, graphic 505 illustrates a signal that may be provided at SMPS 102, as described in connection with various figures herein. Plot 505 illustrates VOUT, FDD, and CLK for SMPS 102 under a heavy load subset of light load conditions (eg, less than about 15 mA), as described above. Assuming that the inductance of the inductor of power converter 108 is approximately 10 microhenries (μH), the value of VOUT may decrease at a rate greater than approximately 100 μV/μs. As shown by diagram 505, as the value of VOUT decreases under heavy load conditions, FDD is asserted in repetitive pulses with a frequency proportional to the rate of change of VOUT.

FIG. 5B is a diagram 510 of an exemplary signal waveform. In at least some examples, graphic 510 depicts a signal that may be provided at SMPS 102, as described in connection with various figures herein. Plot 510 illustrates VOUT, FDD, and CLK for SMPS 102 under a medium load subset of light load conditions (eg, less than about 15 mA), as described above. Assuming that the inductance of the power converter 108 inductor is approximately 10 μH, the value of VOUT may decrease at a rate greater than approximately 10 μV/μs but less than 100 μV/us. As shown by diagram 510, when the value of VOUT decreases under moderate load conditions, the rate of change of VOUT is insufficient to trigger FDD, and FDD has a logic low or deasserted value, which maintain. Controller 110 receives CLK from an oscillator to provide a clock signal to controller 110 to instruct controller 110 to compare the value of Vfb to the value of Vref. In at least some examples, CLK has a period of about 50 μs. In various examples, the period of CLK may be programmed to any value that provides a suitable amount of accuracy in detecting Vref to Vfb variations.

FIG. 5C is a diagram 515 of an exemplary signal waveform. In at least some examples, graphic 515 illustrates a signal that may be provided at SMPS 102, as described in connection with various figures herein. Plot 515 illustrates VOUT, FDD, and CLK for SMPS 102 under a light load subset of light load conditions (eg, less than about 15 mA), as described above. Assuming that the inductance of the inductor of power converter 108 is approximately 10 μH, the value of VOUT may decrease at a rate of less than approximately 10 μV/μs. As shown by diagram 515, when the value of VOUT decreases under light load conditions, the rate of change of VOUT is insufficient to trigger FDD, and FDD has a logic low or deasserted value; keep it up. Controller 110 receives CLK from an oscillator to provide a clock signal to controller 110 to instruct controller 110 to compare the value of Vfb to the value of Vref. In at least some examples, CLK has a period of about 50 μs. However, if VOUT remains within regulation for the programmed number of cycles of CLK (e.g., about 32, or any other number suitable for the SMPS 102 application), the period of CLK may be increased. . For example, the period of CLK may be increased from about 50 μs to about 200 μs. In various examples, the period of CLK may be programmed to any value that provides a suitable amount of accuracy in detecting Vref to Vfb variations. In at least some examples, a component providing CLK may track the number of cycles that VOUT remains in regulation and provide CLK at a frequency determined based on that tracking.

FIG. 6 is a diagram 600 of an exemplary signal waveform. In at least some examples, graphic 600 illustrates signals that may be provided at SMPS 102, as described in connection with various figures herein. Plot 600 shows the frequency of VOUT, SNOOZE_CLK, SNOOZE_CLK (shown as SNOOZE_CLK FREQ in plot 600), the output of comparator 224 (shown as SNOOZE_COMP in plot 600), and the current in the inductor of power converter 108 (shown as SNOOZE_COMP in plot 600). (denoted as I). VOUT, SNOOZE_CLK, and SNOOZE_COMP are each shown with vertical axes representing voltage in units of volts (V). SNOOZE_CLK FREQ is shown with a vertical axis representing frequency in kilohertz (kHz). I is shown with a vertical axis representing current in units of mA. Each signal shown has a horizontal axis in units of milliseconds (ms).

As shown by diagram 600, power converter 108 is operating under light load conditions where the load current of power converter 108 is approximately equal to 10 microamperes (μA). Under light load conditions, SNOOZE_CLK is controlled according to CLK. As further illustrated by diagram 600, in response to SNOOZE_COMP not being asserted for a programmed number of periods (e.g., 32, etc.) of CLK, the frequency of CLK decreases from about 20 kHz to about 3.3 kHz. . In various examples, other frequencies may be used, as described above. As further illustrated by diagram 600, while CLK, and thus SNOOZE_CLK, has a frequency of approximately 20 kHz, the quiescent current (IQ) of SMPS 102 may be approximately equal to 400 nanoamps (nA). However, after decreasing the frequency of CLK, and thus SNOOZE_CLK, the IQ of SMPS 102 may be reduced to less than about 100 nA. As further illustrated by diagram 600, in response to assertion of SNOOZE_COMP, SMPS 102 exits snooze mode and provides a current pulse through power converter 108. In at least some examples, SNOOZE_COMP is asserted in response to the value of Vfb becoming greater than the scaled Vref, as described above. Following assertion of SNOOZE_COMP, CLK returns to the originally programmed frequency until the programmed number of CLK cycles have elapsed again without assertion of SNOOZE_COMP, after which the frequency of CLK may be decreased again to reduce IQ. reduce

FIG. 7 is a diagram 700 of an exemplary signal waveform. In at least some examples, graphic 700 illustrates signals that may be provided at SMPS 102, as described in connection with various figures herein. Diagram 700 shows VOUT, CLK, FDD, ZCD, SNOOZE_CLK, the output of comparator 224 (denoted as SNOOZE_COMP in diagram 700), the current provided by load 106 (denoted as I_out in diagram 700), and the power converter 108 (shown as I in diagram 700). VOUT, CLK, FDD, SNOOZE_CLK, and SNOOZE_COMP are each shown with a vertical axis representing voltage in units of volts. I_out and I are shown with vertical axes representing current, with I_out in units of mA and I in units of amperes (A). Each signal shown has a horizontal axis in units of ms.

As shown by diagram 700, for each rising edge of either CLK, FDD, or ZCD, a corresponding pulse appears on SNOOZE_CLK. When the value of I_out increases suddenly, the value of VOUT decreases and SNOOZE_COMP is asserted. In response to assertion of SNOOZE_COMP, SMPS 102 exits snooze mode, the value of I increases, and services the increased I_out. As further illustrated by diagram 700, in at least some examples, the rate of change in VOUT resulting from increased I_out causes FDD circuit 206 to assert FDD and transmit additional clock pulses of SNOOZE_CLK.

FIG. 8 is a diagram 800 of an exemplary signal waveform. In at least some examples, graphic 800 illustrates signals that may be provided at SMPS 102, as described in connection with various figures herein. Diagram 800 shows VOUT, VOUT_COMP_LOW, PWM Error, PFM Error, the current provided by load 106 (denoted as I_out in diagram 800), and the current in the inductor of power converter 108 (denoted as I in diagram 800). show. VOUT, VOUT_COMP_LOW, PWM Error, and PFM Error are each shown with vertical axes representing voltage in units of volts. I_out and I are shown with the vertical axis representing current, with I_out in mA and I in A. Each signal shown has a horizontal axis in units of ms.

As shown in diagram 800, VOUT_COMP_LOW is asserted in response to a rapid decrease in the value of VOUT, such as due to a sudden increase in I_out. In response to assertion of VOUT_COMP_LOW, SMPS 102 exits snooze mode and the value of I is increased to service the increased I_out. For example, PFM Error is asserted in response to assertion of VOUT_COMP_LOW. In response to assertion of PFM Error, TOFF may have a value of zero and controller 110 may control power converter 108 according to the PWM mode of operation. Such control may rapidly increase the value of IL to service the increased I_out, thereby keeping VOUT within regulation.

As used herein, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with the description herein. For example, if device A provides a signal to control device B to perform an action, then (a) in the first example, device A is directly coupled to device B, and (b) in the second In the example, device A is indirectly coupled to device B through an intervening component C, provided that the intervening component C does not substantially enforce the functional relationship between device A and device B. Therefore, device B is controlled by device A via the control signal provided by device A.

A device “configured” to perform a certain task or function may be configured (e.g., programmed and/or wired) to perform that function and/or configured by the manufacturer at the time of manufacture to perform that function. It may be configurable (or reconfigurable) by the user after manufacture to perform the function and/or other additional or alternative functions. Such configuration may be through firmware and/or software programming of the device, or through the configuration and/or layout of the hardware components and interconnections of the device, or a combination thereof. Good too.

Circuits or devices described as including certain components may alternatively be configured to be coupled to those components to form the described circuitry or device. For example, one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current A structure described as including a power source (such as a power source) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or an integrated circuit (IC) package), and may include passive elements and/or or a third party, either at the time of manufacture or at a later point in time, such as by an end user and/or a third party. can be formed.

Although certain components are described herein as being of a particular process technology, these components may be interchangeable with components of other process technologies. The circuits described herein are reconfigurable to include replaced components to provide functionality that is at least partially similar to functionality that was possible prior to component replacement. be. Components illustrated as resistors generally include any one or more coupled in series and/or parallel to provide the amount of impedance represented by the illustrated resistor, unless otherwise specified. Represents an element. For example, a resistor or capacitor illustrated and described herein as a single component, respectively, may include multiple resistors coupled in series or in parallel between the same two nodes as a single resistor or capacitor, respectively. It may be a container or a capacitor.

As used herein, use of the term "ground voltage potential" refers to chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and/or any ground applicable or suitable for the teachings herein. Including any other form of connection. Unless otherwise specified, "about," "approximately," or "substantially" before a value means +/-10 percent of the stated value.

Modifications in the described embodiments are possible and other embodiments are possible within the scope of the claims.

Claims (20)

A device,
including a control signal generator and a snooze mode controller;
The control signal generator
an error amplifier having a first output, a first input, a second input, and a first snooze input;
a first comparator having a second output, a third input coupled to the first output, and a fourth input;
a second comparator having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input;
a logic circuit having a fourth output and a logic circuit input, the first of the logic circuit inputs being coupled to the second output;
a pulse generator having a fifth output and a seventh input, the seventh input coupled to the fourth output;
including;
the snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input;
Device. 2. The apparatus of claim 1, wherein the error amplifier has a seventh output;
The control signal generator
a first timer having an eighth output and an eighth input, the eighth input coupled to the third output, and the eighth output coupled to a second of the logic circuit inputs; the first timer coupled;
a second timer having a ninth output, a ninth input, and a tenth input, the ninth input being coupled to the third output and the tenth input being coupled to the seventh input; the second timer coupled to an output, the ninth output coupled to a third of the logic circuit inputs;
including;
the logic circuit performs a logical OR operation between signals received via the logic circuit inputs;
Device. 2. The device according to claim 1,
The snooze mode controller
a clock combiner having an eleventh output and a clock combiner input;
a third comparator having a twelfth output, an eleventh input, a twelfth input, and a thirteenth input, the third comparator having the thirteenth input coupled to the eleventh output; A comparator and
a second logic circuit having a thirteenth output and a fourteenth input, the second logic circuit having the fourteenth input coupled to the twelfth output;
a third logic circuit having a fourteenth output and a third logic circuit input, wherein a first of the third logic circuit inputs is coupled to the thirteenth output; the third logic circuit coupled to the first snooze input and the second snooze input;
equipment, including. 4. The apparatus of claim 3, wherein the snooze mode controller comprises:
receiving at the eleventh input a reference voltage scaled according to a scaling factor;
receiving a feedback voltage at the twelfth input;
receiving at the clock combiner input a zero crossing detection signal, a clock signal, and a fast drop detection signal;
providing a snooze clock having an asserted pulse in response to detection of a rising edge in any one of the zero crossing detection signal, the clock signal, or the fast drop detection signal;
comparing the scaled reference voltage to the feedback voltage in response to a rising edge of the snooze clock;
providing a snooze mode control signal based on the comparison between the scaled reference voltage and the feedback voltage;
A device configured to: 5. The device of claim 4, wherein the quiescent current of the device is reduced in response to assertion of the snooze mode control signal. 2. The apparatus of claim 1, wherein the snooze mode controller comprises:
providing a snooze clock signal based on a zero crossing detection signal, a clock signal, and a fast drop detection signal, wherein the snooze clock signal is on a rising edge of any of the zero crossing detection signal, the clock signal, or the fast drop detection signal; In response, includes an asserted pulse;
responsive to a rising edge in the snooze clock signal, determining whether a scaled reference voltage is greater than a feedback voltage representative of an output voltage of a power converter to provide a snooze mode control signal;
disabling at least a portion of the error amplifier and the second comparator in response to a change in the value of the snooze mode control signal;
It is configured as follows,
A quiescent current in the device disables the error amplifier and the second comparator in response to a change in the value of the snooze mode control signal and is responsive only to rising edges in the snooze clock signal. and determining whether the scaled reference voltage is greater than the feedback voltage.
Device. 2. The device according to claim 1,
the first comparator is configured to receive at the fourth input a signal representative of a current in a power converter;
the second comparator is configured to receive a signal having substantially zero voltage at the sixth input;
The apparatus, wherein operation of the second comparator is enabled based on a value of an output signal of the snooze mode controller. A device,
a control signal generator including an error amplifier and a snooze mode controller;
The control signal generator
determining, by the error amplifier, an error signal indicative of a difference between a reference signal and a feedback signal representative of the output voltage of the power converter;
determining whether the value of the error signal is greater than a signal representing a current in the power converter to provide a comparison result;
providing a control signal for controlling the power converter based on the comparison result;
It is configured as follows,
The snooze mode controller is configured to disable at least a portion of the error amplifier in response to determining that a value of the reference voltage scaled by a scaling factor is greater than the feedback signal. ,
Device. 9. The apparatus of claim 8, wherein the snooze mode controller comprises:
a rising edge of a zero-crossing detection signal asserted in response to the current in the power converter decreasing to zero;
a rising edge of a clock signal having a fixed frequency;
a rising edge of a fast drop detection signal having a frequency proportional to a rate of change in value of the output voltage of the power converter;
configured to provide a snooze clock including a signal pulse in response to each of the
Device. 10. The apparatus of claim 9, wherein the snooze mode controller compares the scaled reference voltage with the feedback signal in response to a rising edge on the snooze clock to provide a snooze comparison result. A device configured to: 11. The apparatus of claim 10, wherein the value of the fixed frequency is reduced in response to the snooze comparison result not being asserted for a programmed number of periods of the clock signal. Device. 11. The apparatus of claim 10, wherein the snooze mode controller is configured to provide a snooze mode control signal based on the snooze comparison result, and wherein the snooze mode control signal is configured to The apparatus is configured to disable at least the portion of the error amplifier in response to a change in the error amplifier. 13. The apparatus of claim 12, wherein the control signal generator is configured to control the power converter to provide a burst of current in response to deassertion of the snooze mode control signal. ,Device. 10. The apparatus of claim 9, wherein the frequency of the snooze clock is variable based on the rate of change of the output voltage of the power converter. A system,
load and
a power converter coupled to the load, the power converter configured to switch from a power source to the load;
a controller coupled to the power converter and configured to perform control through the power converter;
including;
The controller,
a control signal generator including an error amplifier;
Snooze mode controller,
including;
The control signal generator
determining, by the error amplifier, an error signal indicative of a difference between a reference signal and a feedback signal representative of the output voltage of the power converter;
determining whether the value of the error signal is greater than a signal representing a current in the power converter to provide a comparison result;
providing a control signal for controlling the power converter based on the comparison result;
It is configured as follows,
The snooze mode controller is configured to disable at least a portion of the error amplifier in response to determining that a value of the reference voltage scaled by a scaling factor is greater than the feedback signal. Ru,
system. 16. The system of claim 15, wherein the snooze mode controller comprises:
a rising edge of a zero-crossing detection signal asserted in response to the current in the power converter decreasing to zero;
a rising edge of a clock signal having a fixed frequency determined based on the amount of time that the output voltage of the power converter remains within regulation;
a rising edge of a fast drop detection signal having a frequency proportional to a rate of change in the value of the output voltage of the power converter;
configured to provide a snooze clock including a signal pulse in response to each of the
system. 17. The system of claim 16, wherein the snooze mode controller compares the scaled reference voltage to the feedback signal in response to a rising edge on the snooze clock to provide a snooze comparison result. The system consists of: 18. The system of claim 17, wherein the snooze mode controller is configured to provide a snooze mode control signal based on the snooze comparison result, and wherein the snooze mode control signal is configured to provide a snooze mode control signal based on the snooze comparison result. The system is configured to disable it. 19. The system of claim 18, wherein assertion of the snooze mode control signal reduces quiescent current consumed by the controller. 19. The system of claim 18, wherein the control signal generator is configured to control the power converter to provide a burst of current in response to deassertion of the snooze mode control signal. ,system.

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