JP2015162578A - Wide band gap semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wide bandgap semiconductor device with a small and simple structure, which can integrate a switching element and a reflux diode, and a method for manufacturing the same.SOLUTION: In a wide bandgap semiconductor device 1, a wide bandgap semiconductor layer 11 comprises: a drift layer 12 having a first conductivity type and containing a second main surface 11b; a body region 13 provided on the drift layer 12 and having a second conductivity type; a source region 14 provided on the body region 13 in such a manner to be separated from the drift layer 12, containing a part of first main surface 11a and having the first conductivity type; and a contact region 15 provided and arranged on the body region 13 so as to abut the source region 14, and having the second conductivity type. An opening 16 which joins the drift layer 12 to the source region 14, is provided on the body region 13. A source electrode 40 is electrically connected to the source region 14 and the contact region 15.

Description

  The present invention relates to a wide band gap semiconductor device and a manufacturing method thereof, and more specifically to a wide band gap semiconductor device including a transistor element and a free wheel diode and a manufacturing method thereof.

  In recent years, silicon carbide (SiC) has been increasingly adopted as a material constituting semiconductor devices in order to enable higher breakdown voltage, lower loss, and use in high-temperature environments. SiC is a wide bandgap semiconductor having a larger bandgap than silicon (Si), which has been widely used as a material constituting a semiconductor device. Therefore, by adopting SiC as a material constituting the semiconductor device, it is possible to achieve high breakdown voltage of the semiconductor device, reduction of on-resistance, and the like. In addition, a semiconductor device that employs SiC as a material has an advantage that a decrease in characteristics when used in a high-temperature environment is smaller than a semiconductor device that employs Si as a material.

  For example, Japanese Patent Laying-Open No. 2008-17237 (Patent Document 1) discloses an electronic component using a SiC semiconductor device as a switching element. When an SiC-FET (Field Effect Transistor) is used as a switching element in a power converter, if a parasitic diode (body diode) inherent in the SiC-FET is used as a free-wheeling diode, crystal degradation of the SiC semiconductor device due to bipolar operation by the body diode May progress. For this reason, Patent Document 1 discloses that a SiC Schottky barrier diode (hereinafter also referred to as SBD) is connected in reverse parallel to the SiC-FET as a freewheeling diode, and a freewheeling current is passed through the SBD.

JP 2008-17237 A

  In the above-mentioned Patent Document 1, when the SiC-FET and the SBD are realized by separate chips or discrete elements, it is necessary to multiplex and mount a plurality of chips or discrete elements. The problem of increasing arises.

  Further, when trying to integrate the SiC-FET and the SBD on one semiconductor chip, both the region where the SiC-FET is formed and the region where the SBD is formed are arranged on one semiconductor chip. The manufacturing process becomes complicated. Moreover, the area of the active region of the SiC-FET, that is, the region contributing to current flow in the SiC-FET is reduced. In other words, the area of the semiconductor chip required to pass a certain amount of current increases.

  An object of the present invention is to provide a wide band gap semiconductor device capable of integrating a switching element and a free-wheeling diode with a small and simple configuration and a method for manufacturing the same.

  A wide band gap semiconductor device according to an aspect of the present invention includes a wide band gap semiconductor layer having a first main surface and a second main surface located on the opposite side to the first main surface. The wide band gap semiconductor layer has a first conductivity type, a drift layer including a second main surface, and a body having a second conductivity type provided in the drift layer and different from the first conductivity type A region that is provided in the body region so as to be separated from the drift layer, includes a part of the first main surface, has a first conductivity type, and is provided in the body region so as to be in contact with the source region And a contact region having a second conductivity type. The body region is provided with an opening for joining the drift layer to the source region. In the first main surface, the wide band gap semiconductor device is electrically connected to the gate insulating film in contact with the body region, the source region, and the drift region, the gate electrode provided on the gate insulating film, and the source region and the contact region. A source electrode to be connected and a drain electrode to be electrically connected to the second main surface are further provided.

  A method of manufacturing a wide band gap semiconductor device according to another aspect of the present invention includes a step of preparing a substrate, a first main surface on the substrate, and a first main surface positioned on the opposite side of the first main surface. Forming a wide band gap semiconductor layer having two main surfaces by epitaxial growth, and implanting impurities into the wide band gap semiconductor layer from the first main surface. In the step of injecting the impurity, the drift layer having the first conductivity type and including the second main surface in the wide band gap semiconductor layer, the drift layer including the first conductivity type, A body region having a different second conductivity type; a source region having a first conductivity type provided in the body region so as to be separated from the drift layer; The contact region having the second conductivity type is formed so as to be in contact with the source region, and the body region is provided with an opening for joining the drift layer to the source region. The manufacturing method includes a step of activating impurities introduced into the wide band gap semiconductor layer by heating the semiconductor substrate on which the wide band gap semiconductor layer is formed, and a gate insulating film on the first main surface. Forming a gate electrode in contact with the gate insulating film, forming an interlayer insulating film so as to cover the gate insulating film and the gate electrode, and removing the gate insulating film and the interlayer insulating film Forming a region where the source region and the contact region are exposed, forming a source electrode in the region, and forming a drain electrode electrically connected to the second main surface.

  According to the present invention, a wide band gap semiconductor device capable of integrating a switching element and a free wheel diode with a small and simple configuration can be realized.

It is a cross-sectional schematic diagram which shows the structure of the wide band gap semiconductor device which concerns on Embodiment 1 of this invention. 1 is an equivalent circuit diagram of a wide band gap semiconductor device according to a first embodiment of the present invention. It is sectional drawing which showed typically the state of the wide band gap semiconductor device in the case of drain-source voltage _VDS > 0. It is sectional drawing which showed typically the state of the wide band gap semiconductor device in the case of drain-source voltage _VDS <0. It is a top view which shows the structure of the wide band gap semiconductor device which concerns on Embodiment 1 of this invention. 3 is a flowchart schematically showing a method for manufacturing a wide band gap semiconductor device according to the first embodiment of the present invention; It is the schematic for demonstrating process (S10) and (S20) in the manufacturing method of the wide band gap semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S30) and (S40) in the manufacturing method of the wide band gap semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S50) and (S60) in the manufacturing method of the wide band gap semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S70) in the manufacturing method of the wide band gap semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S80) in the manufacturing method of the wide band gap semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows the structure of the wide band gap semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed typically the state of the wide band gap semiconductor device in the case of drain-source voltage _VDS > 0. It is sectional drawing which showed typically the state of the modification of the wide band gap semiconductor device in the case of drain-source voltage _VDS > 0. It is a top view which shows the 1st example of arrangement | positioning of a p-type buried region. It is sectional drawing along the XVI-XVI line of FIG. It is a top view which shows the 2nd example of arrangement | positioning of a p-type buried region. It is a top view which shows the 3rd example of arrangement | positioning of a p-type buried region. It is sectional drawing along the XIX-XIX line | wire of FIG. It is a top view which shows the wide band gap semiconductor device with which the 3rd example of arrangement | positioning of the p-type buried region was applied. It is sectional drawing which shows the 4th example of arrangement | positioning of a p-type buried region. It is a top view which shows the wide band gap semiconductor device with which the 4th example of arrangement | positioning of the p-type buried region was applied. It is sectional drawing which shows the 5th example of arrangement | positioning of a p-type buried region. It is the elements on larger scale which expanded some cross sections of the wide band gap semiconductor device shown in FIG. It is a cross-sectional schematic diagram which shows the other structural example of the wide band gap semiconductor device which concerns on Embodiment 1 of this invention.

[Description of Embodiment of Present Invention]
First, embodiments of the present invention will be listed and described. “Electrically connected” is not limited to the case where electrical connection between the two elements is caused by the direct connection of the two elements. Including the case that occurs through another element arranged between two elements.

  (1) A wide band gap semiconductor device according to an embodiment of the present invention includes a first main surface (11a) and a second main surface (on the opposite side to the first main surface (11a)) ( And 11b) a wide band gap semiconductor layer (11). The wide band gap semiconductor layer (11) has the first conductivity type, is provided on the drift layer (12) including the second main surface (11b), and the drift layer (12), so that the first conductivity type is provided. A body region (13) having a second conductivity type different from the type, and provided in the body region (13) so as to be separated from the drift layer (12), and a part of the first main surface (11a) is formed A source region (14) having a first conductivity type, and a contact region (15) provided in the body region (13) and disposed in contact with the source region (14) to have a second conductivity type Including. The body region (13) is provided with an opening (16) that joins the drift layer (12) to the source region (14). The wide band gap semiconductor device includes a gate insulating film (20) in contact with the body region (13), the source region (14), and the drift region (12) on the first main surface (11a), and a gate insulating film (20). The gate electrode (30) provided above, the source electrode (40) electrically connected to the source region (14) and the contact region (15), and electrically connected to the second main surface (11b) And a drain electrode (50).

  According to this configuration, a JFET in which a source electrode and a gate electrode are connected can be included in a MOSFET formed using a wide band gap semiconductor. This JFET can function as a freewheeling diode connected in antiparallel to the MOSFET. Since the free wheel diode can be integrated into the MOSFET in this way, the provision of the free wheel diode can suppress an increase in the size of the transistor cell, that is, the mounting area of the semiconductor chip. Therefore, a circuit including a transistor element and a free wheel diode such as an inverter circuit can be realized with a smaller and simpler configuration.

  (2) Preferably, the drift layer (12) is disposed in the opening (16) and is surrounded by the body region (13), and the second main surface as viewed from the first region. (11b) and a second region disposed on the side. The impurity concentration of the first region is equal to the impurity concentration of the second region or higher than the impurity concentration of the second region.

  According to this configuration, the JFET can be manufactured without greatly changing the MOSFET manufacturing process. Therefore, a circuit including the MOSFET and the free wheel diode can be manufactured by a simple process.

  (3) Preferably, the wide band gap semiconductor layer (11) is made of silicon carbide, gallium nitride or diamond.

  According to this configuration, a power semiconductor device that uses silicon carbide, gallium nitride, or diamond as a material and controls a large current can be realized with a small and simple configuration.

(4) Preferably, the first conductivity type is n-type, and the second conductivity type is p-type.
According to this configuration, since the p-type region is formed in the n-type wide band gap semiconductor layer, the ease of manufacturing the wide band gap semiconductor device can be improved.

(5) Preferably, the opening width of the opening is not less than 0.4 μm and not more than 3.0 μm.
According to this configuration, the JFET present in the MOSFET made of the wide band gap semiconductor can be a normally-off transistor. As a result, the JFET operates so as to allow only the reflux current to flow, so that the function as a reflux diode can be ensured.

  (6) Preferably, in the wide band gap semiconductor layer (11), in the plan view of the first main surface (11a), a plurality of cells whose outer peripheral shape is a hexagonal shape including a major axis are formed adjacent to each other. Is done. Each of the plurality of cells is formed with a contact region (15) so that the outer peripheral shape is surrounded by a source region (14) similar to the hexagonal shape in a plan view of the first main surface (11a), An opening (16) is formed so as to be surrounded by the contact region (15).

  According to this configuration, a plurality of cells whose outer peripheral shape is a hexagonal shape including the long axis are formed, and each cell includes a contact region and a drift layer that are in contact with the source electrode. Since a large area of the contact region and the opening can be ensured, contact resistance between the contact region and the drift layer and the source electrode can be reduced.

  (7) Preferably, the wide band gap semiconductor layer (11) is embedded in the drift layer (12) and disposed closer to the second main surface (11b) than the body region (13). The semiconductor device further includes a first impurity region (80) having two conductivity types.

  According to this configuration, the electric field applied to the drift layer that is located immediately below the source electrode and forms the channel of the JFET is relaxed by the first impurity region. As a result, the occurrence of leakage current when the MOSFET is turned off can be suppressed, and the influence on the breakdown voltage of the JFET can be avoided.

  (8) Preferably, in a plan view of the first main surface (11a), the first impurity region (80) is disposed in the opening (16).

  According to this configuration, when the return current flows through the JFET, it is possible to reduce the path of the return current from being narrowed by the first impurity region. Thereby, the on-resistance of the JFET can be reduced.

  (9) Preferably, in a plan view of the first main surface (11a), the first impurity region (80) is arranged so that at least a part thereof overlaps the body region (13).

  According to this configuration, the depletion layer extending from the body region toward the second main surface and the depletion layer extending from the first impurity region toward the second main surface can be easily connected. As a result, the electric field applied to the drift layer located immediately below the source electrode can be further relaxed. As a result, the occurrence of leakage current can be more reliably suppressed, so that the withstand voltage of the JFET can be maintained. In the structure in which the potential of the first impurity region is floating, holes are effectively injected from the body region into the first impurity region, so that depletion of the first impurity region can be performed in a short time. Can be resolved. Thereby, the response speed of JFET can be improved.

  (10) Preferably, the first impurity region (80) is provided with a through-hole (81) so that the drift layer (12) is connected along the thickness direction of the wide band gap semiconductor layer (11).

  According to this structure, the path | route through which an electric current flows through the drift layer located in a penetration part can be formed. For this reason, as described in the above (9), even when a part of the first impurity region is arranged so as to overlap the body region, the path of the reflux current is prevented from being narrowed by the first impurity region. be able to. Thereby, the on-resistance of the JFET can be lowered while maintaining the high breakdown voltage of the JFET.

  (11) Preferably, the penetrating portion (81) is disposed in the opening (16) in a plan view of the first main surface (11a).

  According to this configuration, it is possible to effectively reduce the path of the reflux current formed through the drift layer in the opening by the first impurity region.

  (12) Preferably, in a plan view of the first main surface (11a), the body region (13) has a long axis extending along a first direction parallel to the first main surface (11a). It has a peripheral shape consisting of a hexagonal shape. In a plan view of the first main surface (11a), the first impurity region (80) has an outer peripheral shape having a polygonal shape including a long axis extending along a second direction perpendicular to the first direction. Have In plan view of the first main surface (11a), the body region (13) and the first impurity region (80) are arranged to intersect each other.

  According to this configuration, a depletion layer extending from the body region toward the second main surface by the intersection of the body region and the first impurity region, and from the first impurity region toward the second main surface. It becomes easy to connect with the extended depletion layer. Thereby, generation | occurrence | production of leak current can be suppressed more reliably. In the structure in which the potential of the first impurity region is floating, carriers (holes) can be effectively injected from the body region to the first impurity region, so that the response speed of the JFET can be improved. Can do.

(13) Preferably, the first impurity region (80) is electrically floated.
According to this configuration, since the potential of the first impurity region becomes higher than the potential of the body region when the potential of the drain electrode is higher than the potential of the source electrode, the first impurity region and the body region have the same potential. In comparison with the case, the depletion layer can be extended longer from the body region to the drift layer side. As a result, the high breakdown voltage of the JFET can be maintained.

  (14) Preferably, the first impurity region (80) is arranged at a position where the distance between the body region (13) and the first impurity region (80) is 5 μm or less.

  According to this configuration, depletion of the first impurity region can be eliminated in a short time by effectively injecting holes from the body region into the first impurity region. Thereby, elimination of depletion of the first impurity region and potential recovery can be achieved.

  (15) Preferably, the first impurity region (80) is arranged at a position where the distance between the body region (13) and the first impurity region (80) is 2 μm or less.

  According to this configuration, it can be expected that depletion of the first impurity region and potential recovery can be achieved in a short time of several tens ns (nanoseconds) or less. Therefore, a wide band gap semiconductor device capable of high-speed response can be realized.

  (16) Preferably, the first impurity region (80) is electrically connected to the source electrode (40).

  According to this configuration, since the potential of the first impurity region is fixed to the same potential as that of the body region, the operation of the wide band gap semiconductor device can be stabilized. Furthermore, as a result of the first impurity region being connected to the source electrode, holes can be effectively injected into the first impurity region. This increases the response speed of the JFET.

  (17) Preferably, the wide band gap semiconductor layer (11) is embedded in the drift layer (12), has the first conductivity type, and has an impurity concentration higher than the impurity concentration of the drift layer (12). A second impurity region (82) having The second impurity region (82) is disposed closer to the second main surface (11b) than the body region (13), and the first impurity region in the plan view of the first main surface (11a). (80).

  According to this configuration, the progress of depletion in the direction perpendicular to the thickness direction from the first impurity region into the drift layer is suppressed by the second impurity region. Thereby, the on-resistance of the JFET can be lowered while maintaining the high breakdown voltage of the JFET.

  (18) Preferably, the second impurity region (82) includes a first end located on the first main surface (11a) side and a second end located on the second main surface (11b) side. And an end. The bonding surface of the first impurity region (80) facing the first main surface (11a) is in the depth direction from the first main surface (11a) to the second main surface (11b). The second impurity region (82) is located within the range from the position of the first end to the position of the second end of the second impurity region (82).

  According to this configuration, in the state where the potential of the drain electrode is lower than the potential of the source electrode, the progress of depletion in the direction perpendicular to the thickness direction from the first impurity region to the drift layer passes through the second impurity region. Is suppressed by. Thereby, the on-resistance of the JFET can be further reduced.

  (19) Preferably, a trench (TR) including a side wall (SW) and a bottom (BT) is formed on the first main surface (11a). The side wall (SW) extends from the first main surface (11a) through the source region (14) and the body region (13) to the drift layer (12). The bottom part (BT) is in contact with the side wall part (SW) and is located in the drift layer (12). The gate insulating film (20) covers the side wall (SW) and the bottom (BT) of the trench (TR), and the gate electrode (30) is provided on the gate insulating film (20).

  According to this configuration, the JFET that can function as a free-wheeling diode can be included in the cell of the trench gate type vertical MOSFET. Thereby, the integration degree of the MOSFET cell can be further increased.

  (20) A method for manufacturing a wide band gap semiconductor device according to an embodiment of the present invention includes a step (S10) of preparing a substrate (10), a first main surface (11a) on the substrate (10), Forming a wide band gap semiconductor layer (11) having a second main surface (11b) located opposite to the first main surface (11a) by epitaxial growth (S20); A step (S30) of injecting impurities into the wide band gap semiconductor layer (11) from the main surface (11a). In the impurity implantation step (S30), the drift layer (12) having the first conductivity type and including the second main surface (11b) in the wide band gap semiconductor layer (11), and the drift layer (12) provided in the body region (13) having a second conductivity type different from the first conductivity type, and being separated from the drift region (12), A part of the first main surface (11a), the source region (14) having the first conductivity type, the body region (13), and disposed so as to be in contact with the source region (14); A contact region (15) having the second conductivity type is formed, and an opening (16) for joining the drift layer (12) to the source region (14) is provided in the body region (13). The manufacturing method activates impurities introduced into the wide band gap semiconductor layer (11) by heating the semiconductor substrate (10) on which the wide band gap semiconductor layer (11) is formed (S40). A step (S50) of forming a gate insulating film (20) on the first main surface (11a), and a step of forming a gate electrode (30) in contact with the gate insulating film (20) (S60). Forming an interlayer insulating film (60) so as to cover the gate insulating film (20) and the gate electrode (30) (S70); removing the gate insulating film (20) and the interlayer insulating film (60); A step (S80) of forming a region (14) and a contact region (15) where the region (14) and the contact region (15) are exposed, and forming a source electrode (40) in the region are electrically connected to the second main surface (11b). Dore Forming an in-electrode (50) (S80).

  According to this configuration, it is possible to integrate a JFET that can function as a free-wheeling diode in a MOSFET formed using a wide band gap semiconductor material, so that an increase in the mounting area of the semiconductor chip can be suppressed. . Therefore, a circuit including a transistor element and a free wheel diode such as an inverter circuit can be realized with a smaller and simpler configuration.

  (21) Preferably, the drift region (12) is disposed in the opening (16) and is surrounded by the body region (13), and the second main surface as viewed from the first region. (11b) and a second region disposed on the side. In the step of implanting impurities (S30), the impurity concentration of the first region is made equal to the impurity concentration of the second region. Alternatively, the impurity concentration of the first region is set higher than the impurity concentration of the second region.

  According to this configuration, the JFET can be manufactured without greatly changing the MOSFET manufacturing process. Therefore, a circuit including the MOSFET and the free wheel diode can be manufactured by a simple process.

  (22) Preferably, in the step (S20) of forming the wide band gap semiconductor layer (11) by epitaxial growth, the second main surface (being embedded in the drift layer (12) and more than the body region (13) ( A first impurity region (80) having the second conductivity type disposed on the side 11b) is formed.

  According to this configuration, the electric field applied to the drift layer that is located immediately below the source electrode and forms the channel of the JFET is relaxed by the first impurity region. As a result, the occurrence of leakage current when the MOSFET is turned off can be suppressed, and the influence on the breakdown voltage of the JFET can be avoided.

  (23) Preferably, in the step (S20) of forming the wide band gap semiconductor layer (11) by epitaxial growth, the second main surface (being embedded in the drift layer (12) and more than the body region (13) ( A second impurity region (82) having the first conductivity type and disposed on the side 11b) is further formed. The second impurity region (82) has the first conductivity type, an impurity concentration higher than the impurity concentration of the drift layer (12), and in a plan view of the first main surface (11a). Are arranged in parallel with the first impurity region (80).

  According to this configuration, the progress of depletion in the direction perpendicular to the thickness direction from the first impurity region into the drift layer is suppressed by the second impurity region. Thereby, the on-resistance of the JFET can be lowered while maintaining the high breakdown voltage of the JFET. In the step (S20) of forming the wide band gap semiconductor layer (11) by epitaxial growth, the epitaxial growth is performed up to the bottom of the body region (13) having the opening (16) facing the drift layer (12). Alternatively, an impurity of the second conductivity type for forming the bottom surface portion of the body region (13) may be implanted, and epitaxial growth may be performed again. According to this configuration, the impurity implantation acceleration energy for forming the bottom surface portion of the body region (13) can be reduced, and the lateral scattering is suppressed, so that the opening (16) can be formed precisely. it can.

[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

<Embodiment 1>
FIG. 1 is a schematic cross-sectional view showing a configuration of a wide bandgap semiconductor device according to Embodiment 1 of the present invention. FIG. 1 is a cross-sectional view taken along the line II of FIG. In this embodiment, the wide gap semiconductor can be silicon carbide (SiC), gallium nitride (GaN), or diamond (C).

  Referring to FIG. 1, a wide band gap semiconductor device 1 according to a first embodiment of the present invention is realized by a plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 2 formed in silicon carbide. In the present embodiment, the plurality of MOSFETs 2 are used as switching elements, for example, in a power converter that drives and controls an inductive load such as a motor.

  MOSFET 2 is a planar type MOSFET, and includes a silicon carbide single crystal substrate 10, a silicon carbide layer 11, a gate insulating film 20, a gate electrode 30, an interlayer insulating film 60, a source electrode 40, and a source wiring layer. 41, a drain electrode 50, and a back surface pad electrode 51.

  Silicon carbide single crystal substrate 10 is made of, for example, a hexagonal silicon carbide single crystal having polytype 4H. Silicon carbide single crystal substrate 10 has a first main surface 10a and a second main surface 10b. The second main surface 10b is located on the opposite side to the first main surface 10a.

  Silicon carbide layer 11 is an epitaxial layer made of silicon carbide, and has a first main surface 11a and a second main surface 11b. Silicon carbide layer 11 is made of, for example, hexagonal silicon carbide having polytype 4H. The second main surface 11b is located on the opposite side to the first main surface 11a. Second main surface 11 b of silicon carbide layer 11 is in contact with first main surface 10 a of silicon carbide single crystal substrate 10. Silicon carbide layer 11 has a drift layer 12, a body region 13, a source region 14, and a contact region 15.

  Drift layer 12 is an n-type region including an impurity (donor) whose conductivity type is n-type (first conductivity type), such as nitrogen. Drift layer 12 includes second main surface 11 b of silicon carbide layer 11. N-type impurity concentration (first conductivity type impurity concentration) of drift layer 12 is preferably lower than the n-type impurity concentration of silicon carbide single crystal substrate 10.

  Body region 13 is a p-type region containing an impurity (acceptor) whose conductivity type is p-type (second conductivity type) such as aluminum or boron.

  Source region 14 is an n-type region containing an n-type impurity such as phosphorus, and source region 14 is provided on body region 13 so as to be separated from drift layer 12 by body region 13. The n-type impurity concentration of the source region 14 is higher than the n-type impurity concentration of the drift layer 12. Source region 14 includes contact region 15 and part of first main surface 11a of silicon carbide layer 11.

  Contact region 15 is a p-type region containing a p-type impurity such as aluminum. The contact region 15 is provided surrounded by the source region 14 and is connected to the body region 13. The contact region 15 has a p-type impurity concentration (second conductivity type impurity concentration) higher than that of the body region 13.

  An opening 16 is provided in a part of the body region 13 located below the source region 14. The opening 16 joins the drift layer 12 to the source region 14. That is, the conductivity type of the region in the opening 16 is n-type. The body region 13 is exposed on the side wall of the opening 16.

  The gate insulating film 20 is provided at a position facing the channel CH1 of the MOSFET 2 formed in the body region 13. Gate insulating film 20 is in contact with body region 13, source region 14 and drift layer 12 at first main surface 11 a of silicon carbide layer 11. Gate insulating film 20 is made of, for example, silicon dioxide.

  The gate electrode 30 is disposed on the gate insulating film 20. Gate electrode 30 faces drift layer 12, body region 13, and source region 14 so as to extend from source region 14 of MOSFET 2 to the other source region 14. The gate electrode 30 is made of a conductor such as polysilicon doped with impurities or aluminum.

  Interlayer insulating film 60 is arranged to cover gate electrode 30 and gate insulating film 20. The interlayer insulating film 60 is made of silicon dioxide. A contact hole SH is formed in the interlayer insulating film 60 at a position overlapping the source region 14 and the contact region 15. The contact hole SH is a contact hole that penetrates the interlayer insulating film 60 and the gate insulating film 20. Contact hole SH exposes first main surface 10a of silicon carbide layer 11. In other words, the contact hole SH exposes the source region 14 and the contact region 15.

  Source electrode 40 is disposed in contact hole SH and contacts source region 14 and contact region 15. Thereby, the source electrode 40 is electrically connected to the source region 14 and the contact region 15. The source electrode 40 is made of a material that can achieve a good electrical junction (ohmic junction) to the source region 14 and the contact region 15, for example, titanium, aluminum, and silicon.

  The source wiring layer 41 is disposed on the interlayer insulating film 60. Source wiring layer 41 is made of, for example, aluminum. The source wiring layer 41 is electrically connected to the source electrode 40 through the contact hole SH.

  Drain electrode 50 is in contact with second main surface 10b of silicon carbide single crystal substrate 10. Thereby, drain electrode 50 is electrically connected to silicon carbide single crystal substrate 10. Alternatively, drain electrode 50 may be made of another material capable of ohmic junction with silicon carbide single crystal substrate 10 such as nickel.

  The back pad electrode 51 is disposed in contact with the drain electrode 50. The back pad electrode 51 is made of, for example, titanium, nickel, silver, or an alloy thereof.

  Next, the operation of the wide band gap semiconductor device 1 according to the first embodiment of the present invention will be described with reference to FIGS.

In MOSFET 2, source potential V _S is applied to source region 14 and contact region 15 through source wiring layer 41 and source electrode 40. The source potential V _S is, for example, a ground potential.

To turn on the MOSFET 2, the drain potential _{V D} is applied to the drain electrode 50, the gate potential _{V G} is applied to the gate electrode 30. Drain potential _{V D} and the gate potential _{V G} is higher than both the source potential _{V S.} For example, it is assumed that V _D > V _G > V _S. The surface layer of the body region 13 below the gate electrode 30 is inverted to n-type, and n through the n-type inversion layer (channel CH1) from the source region 14 to the channel CH1, the drift layer 12, and the silicon carbide single crystal substrate 10 Connect in the mold area. As a result, as indicated by a solid line arrow in FIG. 1, current flows from drain electrode 50 to silicon electrode single crystal substrate 10, drift layer 12, channel CH 1, and source region 14 to source electrode 40.

On the other hand, when the gate potential V _G is zero, n-type inversion layer (channel CH1) disappears, the current is zero. Furthermore, the pn junction between the body region 13 and the drift layer 12 is reverse-biased so that a depletion layer mainly spreads in the drift layer 12 and the MOSFET 2 is turned off.

  In the present embodiment, as shown in FIG. 1, the drift layer 12 (n-type region) is provided in the opening 16 so as to be surrounded by the body region 13 (p-type region) and joined to the source region 14. doing. Drift layer 12, body region 13, source region 14, silicon carbide single crystal substrate 10, source electrode 40 and drain electrode 50 form JFET (Junction Field Effect Transistor) 3.

  Specifically, by providing opening 16 in body region 13, source region 14, drift layer 12, and silicon carbide single crystal substrate 10 (n-type region) are formed between source electrode 40 and drain electrode 50. A current path is formed. In the middle of this current path, a control electrode (gate) composed of the body region 13 (p-type region) is provided. When a voltage in the direction of reverse biasing the pn junction is applied between the gate and the drain, a depletion layer spreads around the pn junction, and the current flowing through the current path is controlled. That is, the JFET 3 having the source electrode 40 and the drain electrode 50 of the MOSFET 2 as the source electrode and the drain electrode, respectively, and the body region 13 as the gate is formed. The source electrode 40 and the body region 13 are electrically connected. Therefore, the gate of JFET 3 is electrically connected to the source, and the same potential as the source is applied to the gate.

  In this embodiment, the JFET 3 is a normally-off type (also called enhancement type), that is, a transistor that is turned off when the threshold voltage is higher than zero and the gate potential and the source potential are the same.

FIG. 2 is an equivalent circuit diagram of the wide band gap semiconductor device 1 according to the first embodiment of the present invention. Hereinafter, in each of the MOSFET 2 and the JFET 3, the drain potential V _D with the source potential Vs as a reference is the drain-source voltage V _DS , and the gate potential V _G with the source potential V _S is the reference is the gate-source voltage V _GS. It is defined and explained.

  Referring to FIG. 2, MOSFET 2 has a drain electrode 50, a gate electrode 30, and a source electrode 40. The JFET 3 has a drain connected to the drain electrode 50 and a source connected to the source electrode 40. The gate (body region 13) of JFET 3 is connected to the source electrode 40.

As described above, the MOSFET 2 is turned on when V _GS > 0 in a state where V _DS > 0. As a result, a current flows through the MOSFET 2 from the drain electrode 50 to the source electrode 40 as indicated by the solid line arrow in each of FIGS. 1 and 2.

At this time, in JFET 3, the same potential (ground potential) as that of the source is applied to the gate, and a potential higher than the source potential V _S is applied to the drain. That is, V _DS > 0 and V _GS = 0. In the normally-off type JFET 3, the current path is interrupted by the depletion layer (see FIG. 3), so that no current flows.

FIG. 3 is a cross-sectional view schematically showing the state of the wide band gap semiconductor device 1 when the drain-source voltage V _DS > 0. Referring to FIG. 3, a voltage is applied between drain electrode 50 and source electrode 40 so that drain potential V _D is higher than source potential V _S. Since the gate potential V _{G of} JFET 3 is equal to the source potential V _S (ground potential), the pn junction between the body region 13 and the drift layer 12 is reverse-biased. Thereby, the depletion layer 70 spreads from the junction surface between the body region 13 and the drift layer 12. The depletion layer 70 blocks the current path between the source electrode 40 and the drain electrode 50, and the JFET 3 is turned off.

On the other hand, when both MOSFETs constituting the upper and lower arms in the inverter circuit are turned off, the drain-source voltage V _DS <0, and the return current flows due to the energy stored in the inductive load. At this time, if a reflux current flows through the body diode inherent in MOSFET 2, there is a risk that crystal degradation of the SiC semiconductor device may proceed due to bipolar operation by the body diode. Further, in the wide band gap semiconductor device, since the rising voltage of the body diode is as high as about 2.5 V, there is a problem that the forward voltage drop becomes high and the conduction loss is increased.

  In this embodiment, as indicated by the dotted arrows in FIGS. 2 and 4, a reflux current is passed through JFET 3 connected in parallel to MOSFET 2. That is, JFET 3 can function as a freewheeling diode.

FIG. 4 is a cross-sectional view schematically showing the state of the wide band gap semiconductor device 1 when the drain-source voltage V _DS <0. Referring to FIG. 4, a voltage is applied between drain electrode 50 and source electrode 40 such that drain potential V _D is lower than source potential V _S when MOSFET 2 is in an off state. Such a condition can occur during operation of the power converter. When V _DS <0, the pn junction between the body region 13 and the drift layer 12 is forward-biased, so that the depletion layer 70 (FIG. 3) is eliminated. As a result, as indicated by a dotted arrow in FIG. 4, a current flows through the n-type region (drift layer 12 in the opening 16) surrounded by the p-type gate (body region 13). In the following description, the drift layer 12 in the opening 16 is also referred to as “channel CH2 of JFET 3”.

Here, in the present embodiment, when the MOSFET 2 is in the off state, it is necessary to turn off the current path of the JFET 3 by turning off the JFET 3. Therefore, the JFET 3 is a normally-off type. Specifically, the channel width of JFET 3 is adjusted so that drift layer 12 (channel CH2) in opening 16 is completely depleted when gate potential V _G and source potential V _{S of} JFET 3 are the same. To do. This channel width corresponds to the distance between p-type regions facing each other across the channel CH2. The channel width is determined by the opening width of the opening 16. The opening width of the opening 16 is the shortest distance between the p-type regions exposed on the side wall of the opening 16.

As shown in FIG. 3, when the drain-source voltage V _DS > 0, the pn junction in JFET 3 is reverse-biased, and the depletion layer 70 extends mainly in the drift layer 12. Here, the thickness of a depletion layer formed in the n-type region (drift layer 12) and X _n, and the thickness of a depletion layer formed in the p-type region (body region 13) and X _p, a depletion layer The thicknesses X _n and X _p are respectively expressed by the following equations (1) and (2).

Here, N _a is the impurity concentration in the p-type region, N _d is the impurity concentration in the n-type region, φ _B is the built-in potential of the pn junction, and Vb is the bias voltage.

In the present embodiment, the channel width of JFET 3, that is, the opening width of opening 16 is set to be approximately twice the thickness _Xn of the depletion layer formed in the n-type region. Thereby, the drift layer 12 (channel CH2) in the opening 16 is completely depleted, so that a normally-off type JFET 3 can be realized. Preferably, the opening width of the opening 16 is not less than 0.4 μm and not more than 3.0 μm. 0.4 μm, which is the lower limit value of the opening width, indicates the minimum value of the opening width that can be realized in the manufacturing process of the wide band gap semiconductor device 1 described later. Therefore, the lower limit value of the opening width depends on the manufacturing process and is not limited to the above value. On the other hand, 3.0 μm, which is the upper limit value of the opening width, shows an example of a limit value at which the channel CH2 of the JFET 3 can be completely depleted. The upper limit of the opening width is determined by the acceptor concentration in the p-type region and the donor concentration in the n-type region.

  In the present embodiment, the threshold voltage of normally-off type JFET 3 is set to a value larger than zero and lower than the rising voltage of the body diode inherent in MOSFET 2. In JFET 3, since the pn junction between the gate and the drain is forward-biased, it is necessary to suppress the threshold voltage below the built-in voltage of the pn junction in order to operate as a unipolar device.

With such a configuration, the JFET 3 is turned on before the body diode becomes conductive in the state of V _DS <0, so that a reflux current flows through the JFET 3. Therefore, the return to the body diode can be suppressed. As a result, it is possible to prevent the crystal deterioration of the SiC semiconductor device from proceeding due to the bipolar operation by the body diode.

  Further, when the MOSFET 2 is configured using a wide band gap semiconductor as a material, since the rising voltage of the body diode is as high as about 2.5 V, the forward voltage drop becomes high and the conduction loss is increased. According to the present embodiment, since the rising voltage of JFET 3 is lower than that of the body diode, the forward voltage drop is also reduced. Thereby, conduction loss can be reduced.

  In the present embodiment, since the n-type impurity concentration of the drift layer 12 is uniform, the n-type impurity concentration in the channel CH2 of the JFET 3 is arranged on the second main surface 11b side as viewed from the channel CH2. The n-type impurity concentration of the drift layer 12 is substantially equal. “The n-type impurity concentration is equal” means that the n-type impurity concentration of the channel CH2 does not necessarily match the n-type impurity concentration of the remaining drift layer 12, and the n-type impurity of the remaining drift layer 12 is not necessarily equal. It may be higher or somewhat lower than the concentration.

  FIG. 5 is a plan view showing the configuration of the wide band gap semiconductor device according to the first embodiment of the present invention. FIG. 5 shows structures of MOSFET 2 and JFET 3 in plan view of first main surface 11a of silicon carbide layer 11. In FIG. 5, the gate insulating film 20, the gate electrode 30, the source electrode 40, the source wiring layer 41, and the interlayer insulating film 60 formed on the first main surface 11a of the silicon carbide layer 11 are not shown.

  Referring to FIG. 5, a plurality of cells CL whose outer peripheral shape is a hexagonal shape including a long axis in a plan view of first main surface 11a are formed adjacent to each other in MOSFET 2. Cell CL includes drift layer 12, body region 13, source region 14 and contact region 15 formed in silicon carbide layer 11, and further includes source electrode 40 (FIG. 1) formed in contact with contact region 15. It is out. In this way, the wide band gap semiconductor device 1 is divided into a plurality of cells CL so that the outer peripheral shape of the first main surface 11a in plan view is a hexagonal shape including the long axis, thereby forming a plurality of cells CL.

  The outer peripheral shape of the cell CL is a hexagonal shape composed of a set of long sides L and a short side S connecting the set of long sides L. The long side L extends along the long axis direction of the hexagon (the direction indicated by the double-headed arrow in the figure). Specifically, the long side L extends along the <1-100> direction of silicon carbide. The plurality of cells CL are formed so as to be in contact with each other at the long side L and the short side S. The ratio of the length of the long side L to the length of the short side S is 1.2 or more and 20 or less, preferably 1.5 or more and 10 or less. For example, the length of the long side L is 200 μm, and the length of the short side S is 10 μm. The major axis direction of the hexagonal shape is not limited to the <1-100> direction, and may be any direction such as the <11-20> direction.

  The outer peripheral shape of the contact region 15 is similar to the outer peripheral shape of the cell CL in a plan view of the first main surface 11a, and is a hexagonal shape including a long axis. The source region 14 is formed so as to surround the contact region 15 in a plan view of the first main surface 11a, and the outer peripheral shape is similar to the outer peripheral shape of the cell CL and is a hexagonal shape including the long axis. Yes. The body region 13 is formed so as to surround the contact region 15 and the source region 14 in a plan view of the first main surface 11a, and the outer peripheral shape is similar to the outer peripheral shape of the cell CL and includes a long axis. It has a shape.

  Long side L and short side S constituting the outer peripheral shape (hexagonal shape) of cell CL extend along the <1-100> direction of silicon carbide. Each side of the outer peripheral shape (hexagonal shape) of body region 13, source region 14, and contact region 15 included in cell CL extends along the <1-100> direction of silicon carbide similarly to cell CL. Therefore, the direction in which carriers move in the channel region (the body region 13 under the gate electrode 30) of the MOSFET 2 (the direction indicated by the arrow in the figure) is <11-20> perpendicular to the <1-100> direction. It is a direction along the direction. With such a configuration, when the MOSFET 2 is operating, carriers can be moved along a direction in which the mobility is high (the <11-20> direction of silicon carbide), thereby reducing the on-resistance of the MOSFET 2. Can do.

  A plurality of openings 16 are provided in the body region 13. The outer peripheral shape of each opening 16 is, for example, a quadrangular shape. The outer peripheral shape of the opening 16 may be another polygonal shape or an elliptical shape. The opening 16 joins the drift layer 12 to the source region 14. Thereby, the body region 13 is formed so as to surround the drift layer 12. Then, the source region 14 is formed so as to be in contact with the drift layer 12, whereby the channel CH 2 of the JFET 3 (see FIG. 4) is formed in the drift layer 12.

  As described above, in the wide band gap semiconductor device 1 according to the first embodiment of the present invention, a plurality of cells CL whose outer peripheral shape is a hexagonal shape including the long axis are formed, and each cell CL is connected to the source electrode 40. It includes a contact area 15 that contacts. This makes it possible to further increase the area of the contact region as compared with a conventional semiconductor device in which a plurality of cells whose outer peripheral shape is a regular hexagonal shape (that is, a hexagonal shape not including a major axis) is formed. As a result, since the contact resistance between the contact region 15 and the source electrode 40 can be reduced, the electrical characteristics of the MOSFET 2 can be improved.

  Next, with reference to FIG. 6, a method for manufacturing wide bandgap semiconductor device 1 according to the first embodiment of the present invention will be described. In the method of manufacturing wide band gap semiconductor device 1 according to the first embodiment of the present invention, first, a silicon carbide substrate preparation step (S10) is performed. In this step (S10), referring to FIG. 7, silicon carbide single crystal substrate 10 having main surfaces 10a and 10b is prepared by cutting an ingot (not shown) made of, for example, 4H—SiC.

  Next, an epitaxial growth layer forming step (S20) is performed. In this step (S20), referring to FIG. 7, silicon carbide layer 11 is formed on first main surface 10a of silicon carbide single crystal substrate 10 by epitaxial growth.

  Next, an ion implantation step (S30) is performed. In this step (S30), referring to FIG. 8, first, for example, aluminum (Al) ions are implanted into silicon carbide layer 11 from first main surface 11a, whereby body region is formed in silicon carbide layer 11. 13 is formed. Next, for example, phosphorus (P) ions are implanted into body region 13 to form source region 14 in body region 13. Next, for example, Al ions are implanted into body region 13 to form contact region 15 adjacent to source region 14 in body region 13. A region in which none of body region 13, source region 14, and contact region 15 is formed in silicon carbide layer 11 becomes drift layer 12. Note that the drift layer 12 is provided so as to be surrounded by the body region 13 in the opening 16. As a result, as shown in FIG. 5, the silicon carbide layer 11 has a contact region 15 having a hexagonal shape including a long axis, and a contact region 15 surrounding the contact region 15 and having a hexagonal shape including a long axis. A source region 14 and a body region 13 that surrounds the source region 14 and the contact region 15 and has an outer peripheral shape including a hexagonal shape including a major axis are formed.

  Note that, after epitaxial growth is performed up to the bottom surface of the body region 13 facing the drift layer 12 and having the opening 16, a p-type (second conductivity type) impurity for forming the bottom surface of the body region 13 is implanted. Then, epitaxial growth may be performed again. According to this configuration, the impurity implantation acceleration energy for forming the bottom surface portion of the body region 13 can be reduced, and the lateral scattering can be suppressed, so that the opening 16 can be formed precisely.

  Next, an activation annealing step (S40) is performed. In this step (S40), impurity introduced into silicon carbide layer 11 is activated by heating silicon carbide single crystal substrate 10 on which silicon carbide layer 11 is formed. Thereby, desired carriers are generated in the impurity regions in silicon carbide layer 11.

Next, a gate insulating film formation step (S50) is performed. In this step (S50), referring to FIG. 9, for example, by heating silicon carbide single crystal substrate 10 on which silicon carbide layer 11 is formed in an atmosphere containing oxygen (O ₂ ), the first main surface is obtained. A gate insulating film 20 made of silicon dioxide (SiO ₂ ) is formed on 11a.

  Next, a gate electrode formation step (S60) is performed. In this step (S60), referring to FIG. 9, gate electrode 30 made of polysilicon and in contact with gate insulating film 20 is formed by LPCVD (Low Pressure Chemical Vapor Deposition), for example.

Next, an interlayer insulating film forming step (S70) is performed. In this step (S70), referring to FIG. 10, interlayer insulating film 60 made of SiO ₂ is formed so as to cover gate insulating film 20 and gate electrode 30 by, eg, CVD.

  Next, an ohmic electrode formation step (S80) is performed. In this step (S80), referring to FIG. 11, first, gate insulating film 20 and interlayer insulating film 60 in the region where source electrode 40 is formed are removed by etching. Thereby, a region where the source region 14 and the contact region 15 are exposed is formed. Next, an alloy containing titanium, aluminum, and silicon is formed in this region. Specifically, a titanium layer, an aluminum layer, and a silicon layer are formed in this order on the above region, and then these layers are heated to produce an alloy containing titanium, aluminum, and silicon. Alternatively, after a mixed layer containing titanium, aluminum, and silicon is formed over the above region, the mixed layer can be heated to produce an alloy containing titanium, aluminum, and silicon.

  On the other hand, a film made of nickel is formed on second main surface 10b of silicon carbide single crystal substrate 10. Thereafter, silicon carbide single crystal substrate 10 is heated, whereby at least part of the film made of nickel is silicided. Thereby, source electrode 40 and drain electrode 50 are formed on first main surface 11a of silicon carbide layer 11 and second main surface 10b of silicon carbide single crystal substrate 10, respectively.

  Next, a wiring formation step (S90) is performed. In this step (S90), the source wiring layer 41 made of a conductor such as Al or gold (Au) is formed so as to cover the source electrode 40 and the interlayer insulating film 60 by, for example, vapor deposition. Similarly to the source wiring layer 41, a back surface pad electrode 51 made of Al, Au or the like is formed so as to cover the drain electrode 50. By performing the steps (S10) to (S90), the wide band gap semiconductor device 1 (FIG. 1) in which the MOSFET 2 and the JFET 3 are integrated is manufactured.

  According to the first embodiment of the present invention, a JFET that can function as a freewheeling diode can be integrated in a single MOSFET cell. Thus, an increase in the size of the transistor cell, that is, the mounting area of the semiconductor chip, due to the provision of the free-wheeling diode can be suppressed. As a result, a circuit including a transistor element and a free-wheeling diode, such as a power conversion device, can be realized with a smaller and simpler configuration. Therefore, in a power semiconductor device configured with a wide band gap semiconductor typified by silicon carbide as a material, downsizing of the semiconductor chip is not hindered.

  Further, according to the first embodiment of the present invention, a JFET can be manufactured without greatly changing the MOSFET manufacturing process, and therefore a circuit including a transistor element and a free wheel diode can be manufactured by a simple process. it can.

<Embodiment 2>
FIG. 12 is a schematic cross-sectional view showing the configuration of the wide band gap semiconductor device according to the second embodiment of the present invention. Referring to FIG. 12, in wide band gap semiconductor device 1A according to the second embodiment of the present invention, silicon carbide layer 11 further includes ap type buried region 80 (first impurity region). The p-type buried region 80 is a p-type region including an impurity (acceptor) such as aluminum or boron. P type buried region 80 is buried in drift layer 12 so as to be located closer to second main surface 11b than body region 13. That is, p type buried region 80 is separated from body region 13 by drift layer 12. In the process of forming the silicon carbide layer 11 on the silicon carbide single crystal substrate 10 in the epitaxial growth layer formation step (S20 in FIG. 6), the p-type buried region 80 is an acceptor ion (second conductive layer) using an implantation mask. It can be formed by implantation of impurity ions for imparting a mold.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  According to the second embodiment of the present invention, the same effect as in the first embodiment can be obtained. Furthermore, according to the second embodiment of the present invention, the electric field applied to drift layer 12 (corresponding to the channel of JFET 3) located immediately below source electrode 40 is relaxed by p type buried region 80 as described below. The Thereby, since generation | occurrence | production of the leakage current at the time of JFET3 OFF can be suppressed, the influence on the proof pressure of JFET3 can be avoided.

FIG. 13 is a cross-sectional view schematically showing the state of the wide band gap semiconductor device 1A when the drain-source voltage V _DS > 0. In FIG. 13, the p-type buried region 80 is electrically connected to the source wiring layer 41. Therefore, the buried region 80 is supplied with the same potential as the potential V _S (ground potential) applied to the source electrode 40. That is, the buried region 80 has the same potential (ground potential) as the body region 13 and the contact region 15.

  Referring to FIG. 13, since a reverse bias voltage is applied to the pn junction between p type buried region 80 and drift layer 12, from the junction surface between p type buried region 80 and drift layer 12, A depletion layer spreads on the p-type buried region 80 side and the drift layer 12 side. A depletion layer extending from the junction surface of p-type buried region 80 and drift layer 12 to the drift layer 12 side, and a depletion layer extending from the junction surface of body region 13 and drift layer 12 to the drift layer 12 side (see FIG. 3) Thus, as shown in FIG. 13, depletion layer 72 having a sufficient length can be formed between body region 13 and second main surface 11 b of silicon carbide layer 11. Thereby, the proportion of the voltage between drain electrode 50 and source electrode 40 that is borne between p type buried region 80 and second main surface 11b of silicon carbide layer 11 is increased. In other words, the voltage borne by the portion shallower than the p-type buried region 80 (the upper portion in FIG. 13) is reduced. As a result, the electric field strength in a portion shallower than the p-type buried region 80 can be reduced. In other words, the electric field strength of the drift layer 12 immediately below the source region 14 where electric field concentration is likely to occur can be reduced. As a result, the leakage current is suppressed from flowing from the drain electrode 50 to the source electrode 40, so that a high voltage can be applied between the drain electrode 50 and the source electrode 40. That is, since the influence on the breakdown voltage of JFET 3 can be avoided, the high breakdown voltage of JFET 3 can be maintained.

In the present embodiment, p type buried region 80 preferably has an impurity concentration higher than that of drift layer 12. If the potential difference between the drain potential V _D and the source potential V _S is increased by making the impurity concentration of the p-type buried region 80 sufficiently higher than the impurity concentration of the drift layer 12, the p-type buried region 80 It is prevented that p type buried region 80 is completely depleted before the depletion layer sufficiently extends to second main surface 11b of silicon carbide layer 11. Thereby, a depletion layer having a sufficient length is formed between p-type buried region 80 and second main surface 11b, so that leakage current can be reliably suppressed.

  On the other hand, when the impurity concentration of p type buried region 80 is not sufficiently higher than the impurity concentration of drift layer 12, p type buried region 80 is completely depleted. In this case, the parasitic capacitance of JFET 3 can be reduced.

  In the wide band gap semiconductor device 1 </ b> A shown in FIG. 13, the p-type buried region 80 and the body region 13 have the same potential by being electrically connected to the source electrode 40. Yes. Since the potential of p-type buried region 80 is fixed, the operation of wide band gap semiconductor device 1A can be stabilized. Furthermore, as a result of the p-type buried region 80 being connected to the source electrode 40, holes can be effectively injected into the p-type buried region 80. Therefore, the response speed of JFET 3 can be increased.

As a modification, a structure in which the potential of the p-type buried region 80 is a floating potential (floating) may be used. According to this, when the drain-source voltage V _DS > 0, the potential of the p-type buried region 80 is higher than the potential of the body region 13 and lower than the drain potential V _D. Therefore, the potential difference between p-type buried region 80 and drift layer 12 is smaller than the potential difference between body region 13 potential and drift layer 12 potential. As a result, compared to the case where p-type buried region 80 and body region 13 are at the same potential (FIG. 13), depletion is longer from the junction surface between body region 13 and drift layer 12 to the drift layer 12 side. The layer can be extended. As a result, the breakdown voltage of the JFET 3 can be ensured.

In the structure in which the potential of the p-type buried region 80 is floating, the p-type buried region 80 can supply carriers (holes) from the body region 13 to the p-type buried region 80. It is preferable to be provided in the vicinity of 13. Specifically, when V _DS <0, a current flows through JFET 3. In this case, electrons injected from the drain electrode 50 can move to the source electrode 40. Thereby, the depletion layer 72 formed on the drift layer 12 side can be reduced (eliminated). On the other hand, depletion of the body region 13 can be eliminated by injecting holes from the source electrode 40 into the body region 13. Further, in the present embodiment, depletion of p type buried region 80 can be eliminated in a short time by injecting holes from body region 13 into p type buried region 80. In this way, since holes can be smoothly injected into the p-type buried region 80, the response speed of the JFET 3 can be improved.

Preferably, the distance between body region 13 and p type buried region 80 in the thickness direction of silicon carbide layer 11 (the vertical direction in FIG. 12) is 5 μm or less. The “distance is 5 μm or less” may be, for example, that the shortest distance between the body region 13 and the p-type buried region 80 is 5 μm or less. Conversely, the maximum distance between the body region 13 and the p-type buried region 80 may be 5 μm or less. For example, according to PA Ivanov et al., “High Hole lifetime (3.8 μm) in 4H-SiC diodes with 5.5 kV blocking voltage”, Electronics Letters, 1999, Vol. 35, No. 16, pages 1382 to 1383 The lifetime of holes in a 4H-SiC diode with a withstand voltage of 5.5 kV is 0.6 to 3.8 μs (300 to 550 K), and the diffusion length of holes is 16 to 22 μm (impurity concentration: 6 × 10 ¹⁴ cm ⁻³ ). It is. By setting the distance between body region 13 and p-type buried region 80 to 5 μm or less, holes can be injected from body region 13 into p-type buried region 80. Thereby, elimination of depletion of p-type buried region 80 and potential recovery can be achieved.

  More preferably, the distance between body region 13 and p type buried region 80 in the thickness direction of silicon carbide layer 11 is 2 μm or less. From the above document, by reducing the distance between the body region 13 and the p-type buried region 80 to 2 μm or less, the depletion of the p-type buried region 80 can be eliminated in a time of several tens of ns (nanoseconds) or less. It can be expected to achieve potential recovery. Therefore, a wide band gap semiconductor device capable of high-speed response can be realized.

In the present embodiment, a depletion layer extending from each of body region 13 and p type buried region 80 to second main surface 11b side of silicon carbide layer 11 is formed in the state of V _DS > 0. . That is, in addition to the body region 13, the p-type buried region 80 can also serve as the gate of the JFET 3. Therefore, as compared with the first embodiment, the size of the depletion layer that should be borne by the body region 13 in order to cut off the leakage current can be reduced. Therefore, as a modification, the JFET 3 can be a normally-on type (also referred to as a depletion type), that is, a transistor that is turned on when the threshold voltage is lower than zero and the gate potential and the source potential are the same. FIG. 14 is a cross-sectional view schematically showing a state of a modified example of the wide band gap semiconductor device 1A when the drain-source voltage V _DS > 0. In the modification of the wide band gap semiconductor device 1A shown in FIG. 14, the JFET 3 is a normally-on type transistor. Therefore, when the gate potential V _G and the source potential V _S are the same potential, the JFET 3 is turned on, and the channel is not completely depleted. Even in such a case, the leakage current can be blocked by the depletion layer 74 extending from the p-type buried region 80 to the second main surface 11b as the drain voltage increases. By using a normally-on type JFET for the free-wheeling diode, a forward voltage drop in the free-wheeling diode can be reduced as compared with the case of using a normally-off type JFET. Thereby, the conduction loss of JFET can be reduced.

  Hereinafter, the arrangement position of the p-type buried region 80 in the wide band gap semiconductor device 1A will be described in detail with reference to FIGS.

(First arrangement example)
FIG. 15 is a plan view showing a first arrangement example of the p-type buried region 80. 16 is a cross-sectional view taken along line XVI-XVI in FIG. FIG. 15 shows structures of MOSFET 2 and JFET 3 in plan view of first main surface 11a of silicon carbide layer 11. In FIG. 15, the gate insulating film 20, the gate electrode 30, the source electrode 40, the source wiring layer 41, and the interlayer insulating film 60 formed on the first main surface 11a of the silicon carbide layer 11 are not shown.

  Referring to FIGS. 15 and 16, p type buried region 80 is arranged in opening 16 in a plan view of first main surface 11a. Specifically, a gap is provided between p type buried region 80 and body region 13 in a plan view of first main surface 11a. Thereby, p type buried region 80 is arranged so as not to overlap body region 13 in plan view of first main surface 11a.

When the drain-source voltage V _DS <0, the JFET 3 is turned on and current flows from the source electrode 40 to the drain electrode 50. According to the first arrangement example, since the current path is narrowed by the p-type buried region 80, the on-resistance of the JFET 3 can be reduced.

  The outer peripheral shape of the p-type embedded region 80 is similar to the outer peripheral shape of the opening 16 in a plan view of the first main surface 11a and is a quadrangular shape including the long axis. The outer peripheral shape of the p-type embedded shape 80 may be another polygonal shape or an elliptical shape.

  Body region 13 is formed so as to surround p-type buried region 80 in a plan view of first main surface 11a, and the outer peripheral shape is similar to the outer peripheral shape of cell CL and includes a long axis. It has a shape. The rectangular long axis that forms the outer periphery of p-type buried region 80 extends along the <1-100> direction of silicon carbide (the direction indicated by the double-headed arrow in the figure), as in cell CL. The distance d1 shown in FIG. 16 is between the body region 13 and the p-type buried region 80 adjacent to the body region 13 in the <11-20> direction perpendicular to the <1-100> direction. Distance.

(Second arrangement example)
FIG. 17 is a plan view showing a second arrangement example of the p-type buried region 80. 16 is a cross-sectional view taken along line XVI-XVI in FIG. FIG. 17 shows the structures of MOSFET 2 and JFET 3 in plan view of first main surface 11a of silicon carbide layer 11 as in FIG. In FIG. 17, the gate insulating film 20, the gate electrode 30, the source electrode 40, the source wiring layer 41, and the interlayer insulating film 60 formed on the first main surface 11a of the silicon carbide layer 11 are not shown.

  Referring to FIG. 17, the second arrangement example has a plurality of p-type buried regions 80 each having a rectangular outer peripheral shape in each of the openings 16 as compared to the first arrangement example shown in FIG. 15. It differs in that it is formed. In the second arrangement example, each of the plurality of p-type buried regions 80 is arranged so as to be located in the opening 16. The outer peripheral shape of each of the p-type buried regions 80 may be a shape other than a square shape.

  Specifically, a plurality of (for example, three) rectangular p-type buried regions 80 are formed in one opening 16 in the plan view of the first main surface 11a. The plurality of p-type buried regions 80 are formed at regular intervals along the long axis direction of the hexagonal shape that is the outer peripheral shape of the cell CL.

  Even if a plurality of p-type buried regions 80 are formed in each of the plurality of openings 16, the same effect as in the first arrangement example can be obtained. The number of p-type buried regions 80 may be three in each opening 16 as shown in FIG. 17, but is not particularly limited.

  In the second arrangement example, a plurality of p-type buried regions 80 are formed in the opening 16 so as to be spaced apart from each other in the plan view of the first main surface 11a. This can further reduce the narrowing of the path of the current flowing through the JFET 3 as compared with the first arrangement example shown in FIG. Therefore, the on-resistance of JFET 3 can be further reduced.

(Third arrangement example)
FIG. 18 is a plan view showing a third arrangement example of the p-type buried region 80. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. FIG. 18 shows the structures of MOSFET 2 and JFET 3 in plan view of first main surface 11a of silicon carbide layer 11 as in FIG. In FIG. 18, gate insulating film 20, gate electrode 30, source electrode 40, source wiring layer 41 and interlayer insulating film 60 formed on first main surface 11 a of silicon carbide layer 11 are not shown.

  Referring to FIGS. 18 and 19, p type buried region 80 is arranged such that a portion of p type buried region 80 overlaps body region 13 in a plan view of first main surface 11a. In other words, a part of the p-type buried region 80 is disposed in the opening 16. Specifically, an overlap portion is provided between p type buried region 80 and body region 13 in a plan view of first main surface 11a. A distance d2 shown in FIG. 19 indicates that body region 13 and p-type buried region 80 adjacent to body region 13 in the <11-20> direction perpendicular to the <1-100> direction of silicon carbide. It is the distance of the overlapping part.

As shown in FIGS. 13 and 14, when the drain-source voltage V _DS > 0, the depletion layer extends from the junction surface of the body region 13 and the drift layer 12 toward the second main surface 11b, and p A depletion layer extends from the junction surface of mold buried region 80 and drift layer 12 toward second main surface 11b. According to the third arrangement example, these two depletion layers can be easily connected. Thereby, the electric field applied to the drift layer 12 (JFET 3 channel) located immediately below the source electrode 40 can be further relaxed. As a result, the occurrence of leakage current can be more reliably suppressed, so that the withstand voltage of JFET 3 can be maintained.

  Furthermore, according to the third arrangement example, carriers (holes) can be easily supplied from the body region 13 to the p-type buried region 80 in a structure in which the potential of the p-type buried region 80 is floating. By effectively injecting holes from the body region 13 into the p-type buried region 80, depletion of the p-type buried region 80 can be eliminated in a short time. Thereby, the response speed of JFET 3 can be further improved.

  FIG. 20 is a plan view showing a wide band gap semiconductor device 1A to which the third arrangement example is applied. FIG. 20 shows structures of MOSFET 2 and JFET 3 in plan view of first main surface 11a of silicon carbide layer 11. In FIG. 20, the gate insulating film 20, the gate electrode 30, the source electrode 40, the source wiring layer 41, and the interlayer insulating film 60 formed on the first main surface 11a of the silicon carbide layer 11 are not shown.

  Referring to FIG. 20, each side of the outer peripheral shape of body region 13 included in cell CL is a hexagonal major axis direction (<1-100> direction of silicon carbide (direction indicated by a double arrow in the figure)). It extends along. On the other hand, the p-type buried region 80 extends along a direction perpendicular to the <1-100> direction (a direction indicated by a single arrow in the drawing). A plurality of p-type buried regions 80 are arranged along the <1-100> direction. Thereby, body region 13 and p type buried region 80 are arranged so as to intersect each other in plan view of first main surface 11a.

In the above configuration, the intersection between the body region 13 and the p-type buried region 80 is an overlapping portion between the body region 13 and the p-type buried region 80 in plan view. Therefore, as described above, in the state of V _DS > 0, a depletion layer extending from the junction surface of body region 13 and drift layer 12 toward second main surface 11b, p-type buried region 80 and drift layer 12 The depletion layer extending from the bonding surface toward the second main surface 11b is easily connected. Thereby, since generation | occurrence | production of leak current can be suppressed more reliably, the proof pressure of JFET3 can be raised.

In the structure in which the potential of the p-type buried region 80 is floating, carriers (holes) can be effectively injected from the body region 13 into the p-type buried region 80 when V _DS <0. it can. Thereby, the response speed of JFET 3 can be further improved.

  Furthermore, in the plan view of the first main surface 11a, the plurality of p-type buried regions 80 are arranged side by side in the opening 16 of each cell CL so that the path of the current flowing through the JFET 3 is The narrowing can be reduced. Therefore, the on-resistance of JFET 3 can be reduced.

(Fourth arrangement example)
FIG. 21 is a cross-sectional view showing a fourth arrangement example of the p-type buried region 80. Referring to FIG. 21, in the fourth arrangement example, as compared with the third arrangement example, penetrating portion 81 has p-type buried region 80 connected to drift layer 12 along the thickness direction. It differs in that it is provided. The through portion 81 is a through hole provided in the p-type buried region 80, for example. In the fourth arrangement example, the p-type buried region 80 does not need to completely surround the through portion 81. The penetrating portion 81 is a non-pattern forming portion in the case where the p-type buried region 80 extending along a surface perpendicular to the thickness direction has a pattern on this surface (that is, in plan view). For example, the non-formed part may be configured as a through-hole by completely surrounding the non-formed part, or the non-formed part may be configured in a net shape when the formed part exists in an island shape.

The opening width of the penetrating part 81 is adjusted so that the drift layer 12 in the penetrating part 81 is completely depleted when V _DS > 0. The opening width of the penetrating part 81 is the shortest distance between the p-type buried regions 80 exposed on the side wall of the penetrating part 81.

According to the fourth arrangement example, when the drain-source voltage V _DS <0, a path of current flowing through the JFET 3 through the drift layer 12 located in the through portion 81 can be formed. Therefore, as in the third arrangement example, even when the p-type buried region 80 is arranged so as to overlap the body region 13 in plan view of the first main surface 11a, the JFET 3 It can be reduced that the current path is narrowed by the p-type buried region 80. Thereby, the on-resistance of JFET 3 can be lowered while maintaining the high breakdown voltage of JFET 3.

  FIG. 22 is a plan view showing a wide band gap semiconductor device 1A to which the fourth arrangement example of the p-type buried region is applied. FIG. 22 shows structures of MOSFET 2 and JFET 3 in plan view of first main surface 11a of silicon carbide layer 11. In FIG. 22, the gate insulating film 20, the gate electrode 30, the source electrode 40, the source wiring layer 41, and the interlayer insulating film 60 formed on the first main surface 11a of the silicon carbide layer 11 are not shown.

  Referring to FIG. 22, in p type buried region 80, penetrating portion 81 is formed to overlap opening 16 in a plan view of first main surface 11 a. Therefore, p type buried region 80 is arranged to overlap body region 13 in plan view of first main surface 11a.

(Fifth arrangement example)
FIG. 23 is a cross-sectional view showing a fifth arrangement example of the p-type buried region 80. Referring to FIG. 23, in the fifth arrangement example, silicon carbide layer 11 further includes an n-type buried region 82 (second impurity region) as compared with the first to fourth arrangement examples. Is different.

  N-type buried region 82 is an n-type region containing an impurity (donor) such as nitrogen. N type buried region 82 is buried in drift layer 12 so as to be located closer to second main surface 11b than body region 13. In the process of forming the silicon carbide layer 11 on the silicon carbide single crystal substrate 10 in the epitaxial growth layer forming step (S20 in FIG. 6), the n-type buried region 82 is formed with donor ions (first conductive layer) using an implantation mask. It can be formed by implantation of impurity ions for imparting a mold.

  N type buried region 82 has an impurity concentration higher than that of drift layer 12. Preferably, n type buried region 82 has an impurity concentration of 1.5 times or more the impurity concentration of drift layer 12. Therefore, the n-type buried region 82 in the drift layer 12 can be specified based on the n-type impurity concentration. For example, the n-type buried region 82 can be specified by analyzing the n-type impurity concentration along the thickness direction of the silicon carbide layer 11 using a scanning capacitance microscope (SCM).

  N-type buried region 82 is juxtaposed with p-type buried region 80 in plan view of first main surface 11a. As shown in FIG. 23, for example, n type buried region 82 is arranged on both sides of p type buried region 80 in a plan view of first main surface 11a. In FIG. 23, two n-type buried regions 82 are arranged with the p-type buried region 80 interposed therebetween. However, in plan view of the first main surface 11a, the two n-type buried regions 82 are disposed. May be formed so as to surround the periphery of the p-type buried region 80, thereby forming a substantially single n-type buried region 82. Further, n type buried region 82 may be in contact with p type buried region 80.

According to the fifth arrangement example, the n-type buried region 82 can reduce the on-resistance of the JFET 3 when the drain-source voltage V _DS <0. This is because the n-type buried region 82 suppresses the progress of depletion from the p-type buried region 80 into the drift layer 12 in the direction perpendicular to the thickness direction (lateral direction in FIG. 23). . Therefore, the on-resistance of JFET 3 can be lowered while maintaining the high breakdown voltage of JFET 3.

P type buried region 80 preferably has an impurity concentration higher than that of n type buried region 82. When the drain-source voltage V _DS > 0, the p-type buried region 80 is completely depleted before the depletion layer sufficiently extends from the p-type buried region 80 to the second main surface 11b. This is to prevent it. As a result, a depletion layer having a sufficient length can be formed between p-type buried region 80 and second main surface 11b, so that the breakdown voltage of JFET 3 is further increased.

  24 is a partially enlarged view of a part of the cross-sectional view of the wide band gap semiconductor device 1A shown in FIG. Referring to FIG. 24, the top line of n type buried region 82 is preferably located closer to first main surface 11a in the thickness direction than top line TL of p type buried region 80.

  The top line of n-type buried region 82 has a sharp increase in n-type impurity concentration in the profile of n-type impurity concentration along the thickness direction of silicon carbide layer 11 from first main surface 11a of silicon carbide layer 11. It can be set as the position where this occurs. The top line TL of the p-type buried region 80 is a virtual line indicating the position of the upper joint surface of the p-type buried region 80. Note that “the upper joint surface of p-type buried region 80” faces the first main surface 11 a of silicon carbide layer 11 in the joint surface between p-type buried region 80 and drift layer 12. And a bonding surface located on the first main surface 11a rather than the second main surface 10b of the silicon carbide single crystal substrate 10.

  N type buried region 82 is arranged inside drift layer 12 so as to include top line TL. Specifically, n-type buried region 82 has a first end located on the first main surface 11a side and a second end located on the second main surface 11b side. The top line TL of the p-type buried region 80 is defined as n from the position of the first end of the n-type buried region 82 in the depth direction from the first major surface 11a to the second major surface 11b. It is located within the range up to the position of the second end of the mold embedding region 82.

In FIG. 24, p-type buried region 80 extends from n-type buried region 82 toward second main surface 11b. Thus, in the state of V _DS > 0, the progress of depletion in the direction from the p-type buried region 80 toward the second main surface 11b (downward in FIG. 24) is suppressed by the n-type buried region 82. Can be prevented. Therefore, since a depletion layer having a sufficient length can be formed between the p-type buried region 80 and the second main surface 11b, the breakdown voltage of the JFET 3 is further increased.

N type buried region 82 extends from p type buried region 80 toward first main surface 11a. In the state of V _DS <0, the depletion layer extends in a direction (upward in FIG. 24) from the p-type buried region 80 toward the first main surface 11a. At this time, the depletion layer can also extend in a direction perpendicular to the thickness direction (lateral direction in FIG. 24). The lateral spread of the depletion layer can be suppressed by the n-type buried region 82. As a result, since the narrowing of the current flow path of JFET 3 can be reduced, the on-resistance of JFET 3 can be further reduced.

  In the first and second embodiments described above, the vertical planar MOSFET has been described as an example, but the structure of the MOFET is not limited to this. For example, the wide band gap semiconductor device according to the present invention can be applied to a trench MOSFET. FIG. 25 is a schematic cross-sectional view showing another configuration example of the wide band gap semiconductor device according to the first embodiment of the present invention. Referring to FIG. 25, second main surface 11a of silicon carbide layer 11 is provided with (gate) trench TR. Trench TR is composed of side wall portion SW and bottom portion BT. Sidewall portion SW extends from first main surface 11 a to source region 14 and body region 13 to drift layer 12. Bottom portion BT is in contact with side wall portion SW and located in drift layer 12. Sidewall portion SW includes a channel surface of MOSFET 2 on body region 13. Sidewall portion SW is inclined with respect to first main surface 11a of silicon carbide layer 11. In a cross-sectional view (a visual field parallel to the first main surface 11b), the trench TR extends in a tapered shape toward the opening. Preferably, the side wall part SW includes a special surface. The special plane is a plane including the first plane having the plane orientation {0-33-8}. More preferably, the special surface includes the first surface microscopically and further includes the second surface having the surface orientation {0-11-1} microscopically. More preferably, the first surface and the second surface include a composite surface having a plane orientation {0-11-2}. The special surface is a surface having an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} surface.

  Note that sidewall portion SW of trench TR may be perpendicular to first main surface 11a of silicon carbide layer 11.

  Gate insulating film 20 covers sidewall portion SW and bottom portion BT of trench TR. The gate electrode 30 is provided on the gate insulating film 20. That is, the gate electrode 30 is in contact with the gate insulating film 20 and is provided inside the trench TR.

  Also in the trench MOSFET shown in FIG. 25, a JFET having the drift layer 12 below the opening 16 as a channel is formed. Therefore, the same effects as those described above can be obtained.

  In the first and second embodiments, the MOSFET is exemplified as the transistor disposed in the wide band gap semiconductor device. However, the transistor element arranged in the wide band gap semiconductor device according to the embodiment of the present invention may be, for example, an IGBT (Insulated Gate Bipolar Transistor).

  In the first and second embodiments, silicon carbide layer 11 is an n-type silicon carbide layer as a whole. That is, in the first and second embodiments, the first conductivity type that is the conductivity type of silicon carbide layer 11 is n-type, and the second conductivity type that is the conductivity type of body region 13 is p-type. By forming the p-type region in the n-type silicon carbide layer, the ease of manufacturing the wide band gap semiconductor device can be improved. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1,1A Wide band gap semiconductor device 2 MOSFET
3 JFET
DESCRIPTION OF SYMBOLS 10 Silicon carbide single crystal substrate 11 Silicon carbide layer 12 Drift layer 13 Body region 14 Source region 15 Contact region 16 Opening 20 Gate insulating film 30 Gate electrode 40 Source electrode 41 Source wiring layer 50 Drain electrode 51 Back surface pad electrode 60 Interlayer insulating film 70, 72, 74 Depletion layer 80 p-type buried region 81 penetrating portion 82 n-type buried region CH1, CH2 channel CL cell

Claims (23)

A wide band gap semiconductor device,
A wide band gap semiconductor layer having a first main surface and a second main surface located on the opposite side to the first main surface;
The wide band gap semiconductor layer is
A drift layer having a first conductivity type and including the second main surface;
A body region provided in the drift layer and having a second conductivity type different from the first conductivity type;
A source region provided in the body region so as to be separated from the drift layer, including a part of the first main surface, and having the first conductivity type;
A contact region provided in the body region, disposed in contact with the source region, and having the second conductivity type;
The body region is provided with an opening for joining the drift layer to the source region,
The wide band gap semiconductor device is:
A gate insulating film in contact with the body region, the source region, and the drift region in the first main surface;
A gate electrode provided on the gate insulating film;
A source electrode electrically connected to the source region and the contact region;
A wide band gap semiconductor device further comprising a drain electrode electrically connected to the second main surface. The drift layer is
A first region disposed within the opening and surrounded by the body region;
A second region disposed on the second main surface side when viewed from the first region,
2. The wide band gap semiconductor device according to claim 1, wherein an impurity concentration of the first region is equal to an impurity concentration of the second region or higher than an impurity concentration of the second region.   The wide band gap semiconductor device according to claim 1, wherein the wide band gap semiconductor layer is made of silicon carbide, gallium nitride, or diamond. The first conductivity type is n-type,
The wide band gap semiconductor device according to any one of claims 1 to 3, wherein the second conductivity type is a p-type.   5. The wide band gap semiconductor device according to claim 1, wherein an opening width of the opening is not less than 0.4 μm and not more than 3.0 μm. In the wide band gap semiconductor layer, in a plan view of the first main surface, a plurality of cells whose outer peripheral shape is a hexagonal shape including a long axis are formed adjacent to each other,
Each of the plurality of cells has the contact region formed so as to be surrounded by the source region whose outer peripheral shape is similar to the hexagonal shape in plan view of the first main surface, and the contact The wide band gap semiconductor device according to claim 1, wherein the opening is formed so as to be surrounded by a region.   The wide band gap semiconductor layer further includes a first impurity region having the second conductivity type embedded in the drift layer and disposed closer to the second main surface than the body region. The wide band gap semiconductor device according to claim 1, further comprising:   The wide band gap semiconductor device according to claim 7, wherein the first impurity region is disposed in the opening in a plan view of the first main surface.   The wide band gap semiconductor device according to claim 7, wherein the first impurity region is arranged so that at least a part thereof overlaps the body region in a plan view of the first main surface.   10. The wide band gap semiconductor device according to claim 9, wherein a penetration portion is provided in the first impurity region so that the drift layer is connected along a thickness direction of the wide band gap semiconductor layer.   The wide band gap semiconductor device according to claim 10, wherein, in a plan view of the first main surface, the through portion is disposed in the opening. In plan view of the first main surface, the body region has an outer peripheral shape including a hexagonal shape including a long axis extending along a first direction parallel to the first main surface;
In a plan view of the first main surface, the first impurity region has an outer peripheral shape including a polygonal shape including a long axis extending along a second direction perpendicular to the first direction. ,
The wide band gap semiconductor device according to claim 9, wherein the body region and the first impurity region are arranged so as to cross each other in a plan view of the first main surface.   The wide band gap semiconductor device according to claim 7, wherein the first impurity region is electrically floated.   The wide band gap semiconductor device according to claim 13, wherein the first impurity region is disposed at a position where a distance between the body region and the first impurity region is 5 μm or less.   The wide band gap semiconductor device according to claim 14, wherein the first impurity region is disposed at a position where a distance between the body region and the first impurity region is 2 μm or less.   The wide band gap semiconductor device according to claim 7, wherein the first impurity region is electrically connected to the source electrode. The wide band gap semiconductor layer further includes a second impurity region embedded in the drift layer, having the first conductivity type, and having an impurity concentration higher than that of the drift layer;
The second impurity region is disposed closer to the second main surface than the body region, and is juxtaposed with the first impurity region in a plan view of the first main surface. The wide band gap semiconductor device according to any one of claims 7 to 16. The second impurity region is
A first end located on the first main surface side;
A second end located on the second main surface side,
The bonding surface of the first impurity region opposed to the first main surface is the first impurity region in the depth direction from the first main surface to the second main surface. The wide band gap semiconductor device according to claim 17, wherein the wide band gap semiconductor device is located within a range from a position of one end portion to a position of the second end portion of the second impurity region. A trench composed of a side wall and a bottom is formed on the first main surface,
The side wall portion extends from the first main surface through the source region and the body region to the drift layer,
The bottom is in contact with the side wall and located in the drift layer;
The gate insulating film covers the sidewall and the bottom of the trench;
The wide band gap semiconductor device according to claim 1, wherein the gate electrode is provided on the gate insulating film. Preparing a substrate;
Forming a wide bandgap semiconductor layer on the substrate by epitaxial growth having a first main surface and a second main surface located on the opposite side of the first main surface;
Injecting impurities into the wide band gap semiconductor layer from the first main surface,
In the step of injecting the impurities, the wide band gap semiconductor layer has a first conductivity type, includes a drift layer including the second main surface, and is provided in the drift layer. A body region having a second conductivity type different from the conductivity type; and provided in the body region so as to be separated from the drift layer, including a part of the first main surface, and the first conductivity type And a contact region provided in the body region and disposed so as to be in contact with the source region and having the second conductivity type, and the body region includes the source region An opening for joining the drift layer is provided,
Activating the impurities introduced into the wide band gap semiconductor layer by heating the semiconductor substrate on which the wide band gap semiconductor layer is formed;
Forming a gate insulating film on the first main surface;
Forming a gate electrode in contact with the gate insulating film;
Forming an interlayer insulating film so as to cover the gate insulating film and the gate electrode;
Removing the gate insulating film and the interlayer insulating film to form a region where the source region and the contact region are exposed, and forming a source electrode in the region;
Forming a drain electrode electrically connected to the second main surface. A method of manufacturing a wide band gap semiconductor device. The drift region is
A first region disposed within the opening and surrounded by the body region;
A second region disposed on the second main surface side when viewed from the first region,
21. The wide according to claim 20, wherein in the step of injecting the impurities, the impurity concentration of the first region is equal to or higher than the impurity concentration of the second region. A method of manufacturing a bandgap semiconductor device.   In the step of forming the wide band gap semiconductor layer by epitaxial growth, the second conductive type is embedded in the drift layer and disposed closer to the second main surface than the body region. The method for manufacturing a wide band gap semiconductor device according to claim 20 or 21, wherein one impurity region is formed. In the step of forming the wide band gap semiconductor layer by epitaxial growth, a first conductive type embedded in the drift layer and disposed closer to the second main surface than the body region has the first conductivity type. 2 impurity regions are further formed,
The second impurity region has the first conductivity type, an impurity concentration higher than the impurity concentration of the drift layer, and the first main surface in the plan view of the first main surface. The method for manufacturing a wide band gap semiconductor device according to claim 22, wherein the wide band gap semiconductor device is arranged in parallel with the impurity region.

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