JP2015144322A - Laminated ceramic electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that after plated layers for external terminal electrodes are formed by applying copper plating, for example, on an end face of a component main body having end parts of internal electrodes exposed, when the plated layers are subjected to heat processing at 1000°C or higher in order to improve adhesion strength and moisture resistance of the external terminal electrodes, a part of the plated layers is melted so as to deteriorate adhesion force of the plated layers.SOLUTION: Plated layers 10 and 11 include an eutectic state and surface area ratios (=a three dimensional area/a two dimensional area) of the plated layers 10 and 11 are set to 1.011 or more. This can confirm that melting of the plated layers caused by heat processing can be prevented completely while keeping adhesion force between the plated layers 10 and 11 and a component main body 2 in a step for heat processing the component main body, on which the plated layers 10 and 11 are formed, at temperatures of 1000°C or more. Further the surface area ratios of the plated layers 10 and 11 can be kept high, which can also enhance adhesion force of plated layers 12 and 13 above the layers 10 and 11.

Description

  The present invention relates to a multilayer ceramic electronic component, and more particularly to a multilayer ceramic electronic component formed by direct plating so that an external terminal electrode is electrically connected to an internal electrode.

  As shown in FIG. 3, a multilayer ceramic electronic component 101 typified by a multilayer ceramic capacitor is generally formed along a plurality of stacked ceramic layers 102 made of, for example, a dielectric ceramic, and an interface between the ceramic layers 102. A component main body 105 having a laminated structure including a plurality of layered internal electrodes 103 and 104 is provided. The end portions of the plurality of internal electrodes 103 and the plurality of internal electrodes 104 are exposed on one and other end surfaces 106 and 107 of the component main body 105, respectively. External terminal electrodes 108 and 109 are formed so that each end is electrically connected to each other.

  In forming external terminal electrodes 108 and 109, generally, paste electrode layer 110 is first formed by applying a metal paste containing a metal component and a glass component onto end faces 106 and 107 of component body 105 and then baking the paste. The Next, a first plating layer 111 mainly composed of nickel, for example, is formed on paste electrode layer 110, and a second plating layer 112 mainly composed of tin or gold, for example, is further formed thereon. The That is, each of external terminal electrodes 108 and 109 has a three-layer structure of paste electrode layer 110, first plating layer 111, and second plating layer 112.

  The external terminal electrodes 108 and 109 are required to have good wettability with solder when the multilayer ceramic electronic component 101 is mounted on a substrate using solder. At the same time, a plurality of internal electrodes 103 that are electrically insulated from each other are electrically connected to the external terminal electrode 108, and are electrically insulated from each other with respect to the external terminal electrode 109. The role of electrically connecting the plurality of internal electrodes 104 in the connected state is required. The above-mentioned second plating layer 112 plays a role of ensuring solder wettability, and the paste electrode layer 110 plays a role of electrical connection between the internal electrodes 103 and 104. The 1st plating layer 111 has played the role which prevents the solder erosion at the time of solder joining.

  However, the paste electrode layer 110 has a large thickness of several tens of μm to several hundreds of μm. Therefore, in order to keep the dimensions of the multilayer ceramic electronic component 101 within a certain standard value, it is necessary to secure the volume of the paste electrode layer 110. Undesirably, it is effective for securing the capacitance. There is a need to reduce the volume. On the other hand, since the plating layers 111 and 112 have a thickness of about several μm, if the external terminal electrodes 108 and 109 can be configured with only the first plating layer 111 and the second plating layer 112, the capacitance can be secured. It is possible to secure a larger effective volume.

  For example, International Publication No. 2008/059666 (Patent Document 1) describes that a plating layer serving as an external terminal electrode is directly formed on an end surface of a component main body. Further, Patent Document 1 also describes that an interdiffusion region is formed at the boundary between the internal electrode and the plating layer by performing a heat treatment after the plating layer is formed.

  Therefore, when this prior art is applied, the volume expansion of the metal occurs in the interdiffusion region, so that the gap that may exist at the interface between the ceramic layer and each of the internal electrode and the external terminal electrode can be effectively filled. Then, it is possible to advantageously prevent a plating solution or other moisture in a plating process that may be performed thereafter from entering the component main body.

  In addition, when this prior art is applied, it is expected that the adhesion strength at the interface between the ceramic and the plating layer constituting the ceramic layer laminated with the internal electrode interposed in the component body is also expected. When this improvement in adhesion is required, it is considered desirable to perform heat treatment at a temperature of 1000 ° C. or higher, which is the eutectic temperature of the metal constituting the plating layer. For example, when a copper plating layer is formed, it is considered desirable to perform heat treatment at a temperature of 1000 ° C. or higher which is close to the eutectic temperature of copper.

  However, when heat treatment is performed at a temperature of 1000 ° C. or higher, a problem that a part of copper is melted may be encountered. As a result, when the multilayer ceramic electronic component is mounted on the circuit board using solder, there is a risk that the fixing force to the circuit board will be reduced.

  Moreover, when forming plating layers, such as nickel, on a copper plating layer, there exists a possibility that the adhesive force with a copper plating layer may fall a little.

International Publication No. 2008/059666 Pamphlet

  An object of the present invention is to provide a multilayer ceramic electronic component capable of solving the above problems.

  The present invention has a laminated structure composed of a plurality of ceramic layers, the internal electrode is formed inside, and a part of the internal electrode is exposed, and the component main body is electrically connected to the internal electrode. And an external terminal electrode formed on the outer surface of the component body, the external terminal electrode having a plating layer formed on the exposed surface of the internal electrode in the component body, toward a multilayer ceramic electronic component It is done. In the multilayer ceramic electronic component according to the present invention, the plating layer includes a eutectic state, and a surface area ratio evaluated by tapping AFM is 1.011 or more in a 50 μm × 50 μm region near the center of the plating layer. It is characterized by. In addition, the plating layer having such a surface area ratio is a plating layer that is the most base formed on the component main body when a plurality of plating layers are formed in a laminated form.

  The surface area ratio is expressed by surface area ratio = three-dimensional area / two-dimensional area. Here, the two-dimensional area is the area of the measurement region, and the three-dimensional area is the surface area that takes into account the depth (in other words, unevenness) of the measurement region. Therefore, a surface area ratio of 1 means that the surface is in a completely flat state without surface roughness, and on the other hand, as the surface area ratio increases, the surface irregularities become more severe.

  According to the present invention, since the surface area ratio of the plating layer is kept as high as 1.011 or more, it is possible to almost completely prevent the plating layer from being melted by heat treatment while maintaining the adhesion between the plating layer and the component main body. It can be confirmed that it was possible. Moreover, since the surface area ratio of the plating layer is kept high, the adhesion with the plating layer thereon can be further increased.

  In the present invention, when the main component of the plating layer is copper, copper is a metal that originally exhibits good adhesion to the ceramic, so that the adhesion between the plating layer and the component body can be further increased.

  In this invention, an interdiffusion region where both the metal component contained in the plating layer and the metal component contained in the internal electrode can be detected is formed at the boundary portion between the plating layer and the internal electrode. It is formed so as to extend to both the plating layer side and the internal electrode side, and on the internal electrode side, if it reaches a position 2 μm or more away from the exposed surface of the internal electrode in the component body, in order to improve the fixing force As described above, it can be confirmed that the effect of heat-treating the component main body on which the plating layer is formed at a temperature of 1000 ° C. or more is sufficiently exhibited.

1 is a cross-sectional view showing a multilayer ceramic electronic component 1 according to an embodiment of the present invention. In the course of the manufacturing process of the multilayer ceramic electronic component 1 shown in FIG. 1, after forming the first plating layer 10 on the component main body 2 and then performing heat treatment in order to form external terminal electrodes It is an expanded sectional view which shows a part of component main body 2 of. It is sectional drawing of the conventional multilayer ceramic electronic component 101. FIG.

  A multilayer ceramic electronic component 1 according to an embodiment of the present invention will be described with reference to FIGS.

  The multilayer ceramic electronic component 1 includes a component body 2 having a multilayer structure. The component body 2 has a plurality of internal electrodes 3 and 4 formed therein. More specifically, the component body 2 includes a plurality of laminated ceramic layers 5 and a plurality of layered internal electrodes 3 and 4 formed along an interface between the ceramic layers 5. The internal electrodes 3 and 4 are mainly composed of nickel, for example.

  When the multilayer ceramic electronic component 1 constitutes a multilayer ceramic capacitor, the ceramic layer 5 is composed of a dielectric ceramic. In addition, the multilayer ceramic electronic component 1 may constitute an inductor, a thermistor, a piezoelectric component, or the like. Therefore, according to the function of the multilayer ceramic electronic component 1, the ceramic layer 5 may be made of a magnetic ceramic, a semiconductor ceramic, a piezoelectric ceramic, or the like in addition to the dielectric ceramic.

  The ends of the plurality of internal electrodes 3 and the plurality of internal electrodes 4 are exposed at one and the other end surfaces 6 and 7 of the component body 2, respectively. External terminal electrodes 8 and 9 are formed so that each end is electrically connected to each other.

  Although the illustrated multilayer ceramic electronic component 1 is a two-terminal type including two external terminal electrodes 8 and 9, the present invention can also be applied to a multi-terminal multilayer ceramic electronic component. it can.

  Each of the external terminal electrodes 8 and 9 is formed on the exposed surfaces of the internal electrodes 3 and 4 in the component main body 2, that is, the first plating layers 10 and 11 formed by direct plating on the end surfaces 6 and 7. The second plating layers 12 and 13 are provided.

  The first plating layers 10 and 11 are for electrically connecting the plurality of internal electrodes 3 and 4 to each other, and preferably contain copper as a main component. On the other hand, the second plating layers 12 and 13 are for improving or imparting the mountability of the multilayer ceramic electronic component 1, and are each a solder barrier layer made of a plating layer mainly composed of nickel, for example. 14 and 15, and solder wettability imparting layers 16 and 17 formed on the solder barrier layers 14 and 15 for imparting solder wettability and made of, for example, a plating layer mainly composed of tin or gold. Yes. Note that the above-described plating mainly composed of tin includes, for example, Sn—Pb solder plating. The plating mainly composed of nickel includes Ni-P plating by electroless plating.

  As described above, when the first plating layers 10 and 11 are mainly composed of copper having good throwing power during the plating process, the efficiency of the plating process can be improved and the external terminal electrodes 8 and 9 can be fixed. The wearing power can be increased.

  The plating method for forming the first plating layers 10 and 11 and the second plating layers 12 and 13 may be an electroless plating method in which metal ions are deposited using a reducing agent, or an energization treatment may be performed. The electrolytic plating method to be performed may be used.

  Next, a method for manufacturing the multilayer ceramic electronic component 1 shown in FIG. 1, particularly a method for forming the external terminal electrodes 8 and 9 will be described.

  First, the component main body 2 is produced by a known method. Next, the external terminal electrodes 8 and 9 are formed on the end faces 6 and 7 of the component body 2 so as to be electrically connected to the internal electrodes 3 and 4.

  In forming the external terminal electrodes 8 and 9, first, the first plating layers 10 and 11 are formed on the end surfaces 6 and 7 of the component body 2. In the component body 2 before plating, the plurality of internal electrodes 3 exposed on one end face 6 and the plurality of internal electrodes 4 exposed on the other end face 7 are electrically insulated. It has become. In order to form the first plating layers 10 and 11, first, metal ions in the plating solution are deposited on the exposed portions of the internal electrodes 3 and 4. Then, this plating deposit is further grown, and the plating deposits in each exposed portion of the adjacent internal electrode 3 and each exposed portion of the adjacent internal electrode 4 are physically connected. In this way, uniform and dense first plating layers 10 and 11 are formed.

  In this embodiment, the component body 2 of the multilayer ceramic electronic component 1 includes a pair of main surfaces 19 and 20 facing each other and a pair of side surfaces facing each other in addition to the pair of end surfaces 6 and 7 described above. (Not shown in FIG. 1) and having a substantially rectangular parallelepiped shape. The first plating layers 10 and 11 described above are formed on the pair of end faces 6 and 7, respectively, and the edge thereof is on the pair of main faces 19 and 20 adjacent to the end faces 6 and 7. As well as on a pair of sides.

  As described above, in order to make it possible to efficiently form the first plating layers 10 and 11 such that the edges thereof reach the pair of main surfaces 19 and 20 and the pair of side surfaces. Although not shown, dummy conductors may be formed on the end portions adjacent to the end surfaces 6 and 7 of the main surfaces 19 and 20 of the component body 2 and / or on the outer layer portion of the component body 2. Such a dummy conductor does not substantially contribute to the development of electrical characteristics, but causes the deposition of metal ions for the formation of the first plating layers 10 and 11 and promotes the plating growth. Act on.

  Prior to the above-described plating step, it is preferable to subject the end surfaces 6 and 7 of the component body 2 to a polishing process in order to sufficiently expose the internal electrodes 3 and 4 at the end surfaces 6 and 7. In this case, if the polishing process is performed to such an extent that the exposed ends of the internal electrodes 3 and 4 protrude from the end faces 6 and 7, each exposed end spreads in the surface direction, so that energy required for plating growth can be reduced. it can.

  Next, the component main body 2 on which the first plating layers 10 and 11 are formed as described above is heat-treated. As the heat treatment temperature, a temperature of 1000 ° C. or higher is employed. The state after this heat treatment is shown in FIG. In FIG. 2, the internal electrode 3 and the first plating layer 10 are illustrated. The configuration on the side of the internal electrode 4 and the first plating layer 11 not shown in FIG. 2 is substantially the same as the configuration on the side of the internal electrode 3 and the first plating layer 10 shown in FIG. Omitted.

  Referring to FIG. 2, an interdiffusion region 25 is formed between internal electrode 3 and first plating layer 10. This interdiffusion region 25 is preferably present in a region having a length L of 2 μm or more from the boundary between the internal electrode 3 and the first plating layer 10. In other words, it is preferable to perform the heat treatment under such conditions that the length L is 2 μm or more. In the interdiffusion region 25, since the volume expansion of the metal occurs, the gap that may exist at the interface between the ceramic layer 5 and each of the internal electrode 3 and the first plating layer 10 can be advantageously filled, and as a result, The effect of preventing moisture from entering the interior of the component body 2 is achieved.

  In addition, since the heat treatment described above is performed at a temperature of 1000 ° C. or higher which is the eutectic temperature of the metal constituting the first plating layers 10 and 11, the internal electrode 3 and 4 are interposed in the component main body 2. It is also possible to improve the adhesion at the interface between the ceramic constituting the laminated ceramic layer 5 and the first plating layers 10 and 11. For this reason, in the heat treatment, a step of keeping at a top temperature of 1000 ° C. or higher is performed.

  However, if heat treatment is performed at a temperature of 1000 ° C. or higher, there is a possibility that a part of the metal constituting the first plating layers 10 and 11 containing copper as a main component may be melted. As a result, when the multilayer ceramic electronic component 1 is mounted on a circuit board (not shown) using solder, there is a risk that the fixing force to the circuit board will be reduced. In addition, the adhesion of the second plating layers 12 and 13 formed on the first plating layers 10 and 11 to the first plating layers 10 and 11 may be slightly reduced.

  Therefore, in the heat treatment step at a temperature of 1000 ° C. or higher, the average rate of temperature rise from room temperature to the top temperature of 1000 ° C. or higher is set to 100 ° C./min or higher, and the keep time at the top temperature is set to 1 minute. Thereby, melting of the metal constituting the first plating layers 10 and 11 can be almost completely prevented while maintaining the fixing force between the first plating layers 10 and 11 and the component main body 2. Therefore, as can be seen from the experimental examples described later, the first plating layers 10 and 11 maintain an appropriate eutectic state, and the surface area ratio of the first plating layers 10 and 11 remains high at 1.011 or higher. For this reason, the adhesion with the second plating layers 12 and 13 described below can be increased.

  Next, the second plating layers 12 and 13 are formed. Since the second plating layers 12 and 13 are after the first plating layers 10 and 11 are formed, they can be easily formed by a normal method. This is because at the stage where the second plating layers 12 and 13 are to be formed, the place to be plated is a continuous surface having conductivity.

  In this embodiment, in order to form the second plating layers 12 and 13, a step of forming solder barrier layers 14 and 15 made of, for example, nickel, and formation of solder wettability imparting layers 16 and 17 made of, for example, tin or gold The steps are performed sequentially.

  Hereinafter, experimental examples carried out to determine the scope of the present invention and to confirm the effects of the present invention will be described.

  A multilayer ceramic electronic component body having a length of 0.94 mm, a width of 0.47 mm, and a height of 0.47 mm as a component body of a multilayer ceramic electronic component as a sample, the ceramic layer being a barium titanate dielectric ceramic The internal electrode was prepared with nickel as the main component. In this component main body, the number of laminated ceramic layers was 220, and the thickness of each ceramic layer was 1.5 μm. The finished multilayer ceramic capacitor was designed to have a capacitance of 2.2 μF and a rated voltage of 6.3 V.

Next, 500 pieces of the component main body were put into a horizontal rotating barrel having a capacity of 300 ml, and in addition, 100 ml of a medium having a diameter of 0.7 mm was put. Then, the rotating barrel was immersed in a copper plating bath with a bath temperature of 25 ° C. adjusted to pH 8.7, and rotated at a barrel peripheral speed of 2.6 m / min. At a current density of 0.5 A / dm ² . A copper plating layer having a film thickness of about 1 μm was directly formed on the end face of the component main body where the internal electrodes were exposed. The copper plating bath contained 14 g / liter copper pyrophosphate, 120 g / liter pyrophosphoric acid, and 10 g / liter potassium oxalate.

  Next, the component main body on which the copper plating layer is formed as described above is heated from room temperature to a top temperature of 1065 ° C. at a heating rate as shown in Table 1 in an atmosphere having an oxygen concentration of 100 ppm, The top temperature was kept for 1 minute.

  In Table 1, Samples 1 to 9 have a heating rate of 100 ° C./min or more, and Samples 10 to 13 have a heating rate of less than 100 ° C./min.

  With respect to the multilayer ceramic capacitor according to each sample obtained as described above, the surface area ratio and the fixing force were evaluated.

  The surface area ratio (S ratio) was evaluated according to the tapping AFM using an apparatus “SPA400” manufactured by SII nanotechnology, and the ratio of the three-dimensional area / two-dimensional area in the measurement region was defined as the surface area ratio. The measurement visual field was an area of 50 μm × 50 μm in the vicinity of the center of the cross section defined by the width direction dimension and the thickness direction dimension of the multilayer ceramic capacitor according to the sample.

  The fixing force was evaluated by applying a load causing shear fracture to the multilayer ceramic capacitor according to the sample. That is, the multilayer ceramic capacitor according to each sample is mounted on a substrate by soldering, and a load is applied in parallel to both external terminal electrodes at a weighting speed of 0.5 mm / second until breakdown occurs. The mode (destructed part) was observed.

  The above results are shown in Table 2.

  In Samples 1 to 9 where the rate of temperature increase is 100 ° C./min or more, no breakage occurs at the interface between the component main body and the copper plating layer, the broken portion is in the component main body, and the adhesion of the copper plating layer to the component main body is We were able to secure enough. This is presumably because an appropriate eutectic state could be maintained in the copper plating layer. In Samples 1 to 9, a surface area ratio of 1.011 or more could be maintained. This is presumed to be because the melting of the copper plating layer was prevented as much as possible.

  On the other hand, in Samples 10 to 13 where the rate of temperature increase was less than 100 ° C./min, breakage occurred at the interface between the component body and the copper plating layer, and the adhesion of the copper plating layer to the component body was poor. In Samples 10 to 13, the surface area ratio was less than 1.011 and a value close to 1. These are presumed to be because the time for keeping around the eutectic temperature is lengthened and the melting of the copper plating layer has progressed.

  Further, in order to confirm the state of mutual diffusion at the boundary portion between the internal electrode and the copper plating layer generated by the above heat treatment, WDX mapping analysis was performed on samples 1 to 9 within the scope of the present invention, and the metal element The two-dimensional diffusion state was analyzed. In this analysis, “JXA8500F” manufactured by JEOL Ltd. was used as an apparatus, the acceleration voltage was 15 kV, the irradiation current was 50 nA, the scanning electron microscope (SEM) magnification was 5000 times, the integration time was 40 ms, Ni and Cu detection characteristic X-ray was used, and a primary line of Kα characteristic X-ray was used. From the diffusion state thus analyzed, an interdiffusion region is formed so as to extend to both the copper plating layer side and the internal electrode side. On the internal electrode side, 2 μm from the exposed surface of the internal electrode in the component body. It was confirmed that it reached the position far away.

  In the above experimental examples, copper was used as the metal constituting the plating layer, but even an alloy composed of copper and another metal has a eutectic temperature of 1000 ° C. or higher, It has been confirmed that similar results can be obtained.

DESCRIPTION OF SYMBOLS 1 Multilayer ceramic electronic component 2 Component main body 3, 4 Internal electrode 5 Ceramic layer 6, 7 End surface 8, 9 External terminal electrode 10, 11 1st plating layer 12, 13 2nd plating layer 25 Interdiffusion area

Claims (3)

A component body having a laminated structure composed of a plurality of ceramic layers, an internal electrode is formed inside, and a part of the internal electrode is exposed,
An external terminal electrode electrically connected to the internal electrode and formed on the outer surface of the component body;
The external terminal electrode includes a plating layer formed on an exposed surface of the internal electrode in the component main body, the plating layer includes a eutectic state, and is in a region of 50 μm × 50 μm near the center of the plating layer. The surface area ratio evaluated by tapping AFM is 1.011 or more.
Multilayer ceramic electronic components.   An interdiffusion region in which both the metal component contained in the plating layer and the metal component contained in the internal electrode can be detected is formed at the boundary portion between the plating layer and the internal electrode, and the interdiffusion region Is formed so as to extend to both the plating layer side and the internal electrode side, and on the internal electrode side, it reaches a position 2 μm or more away from the exposed surface of the internal electrode in the component body. Item 2. The multilayer ceramic electronic component according to Item 1.   The multilayer ceramic electronic component according to claim 1, wherein the plating layer contains copper as a main component.

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