JP2015047040A - Switching power supply circuit - Google Patents

Abstract

The present invention suppresses fluctuations in output voltage at the time of transition of an operation mode.
A voltage control circuit 4 fixes a boosting transistor T2 at 5% regardless of control of an error amplifier 13 during a boost transition period in which the operation in the step-down mode is shifted to the operation in the boost mode. An operation is performed in a fixed duty boost mode that is driven at an on-duty. The voltage control circuit 4 drives the step-down transistor T1 with a fixed on-duty of 95% regardless of the control of the error amplifier 13 during the step-down transition period during which the operation in the step-up mode is shifted to the operation in the step-down mode. The operation in the fixed duty step-down mode is performed.
[Selection] Figure 1

Description

  The present invention relates to a step-up / step-down switching power supply circuit that boosts an input voltage applied to a power supply input terminal and outputs the boosted voltage from a power supply output terminal, and performs a step-down operation that steps down the input voltage and outputs the voltage from a power supply output terminal.

  A step-up / step-down switching power supply circuit (see, for example, Patent Document 1) is used to convert a battery voltage supplied from, for example, an in-vehicle battery into a DC voltage having a voltage value suitable for a circuit power supply such as a microcomputer. In this case, if the battery voltage is a normal value (steady value), the switching power supply circuit performs a step-down operation (step-down mode). However, normally, the battery supplies power to other than the microcomputer. Therefore, depending on other load conditions, the battery voltage may suddenly change to a low value. In such a case, the switching power supply circuit performs a boosting operation (boost mode). Thereby, an appropriate power supply voltage is always applied to the microcomputer, and a situation in which the operation stops can be prevented.

Japanese Patent No. 3206556

  However, the switching power supply circuit configured as described above differs in control contents based on the output of the error amplifier (error amplifier circuit) in each operation mode (step-down mode and step-up mode). Therefore, there is a possibility that the output voltage becomes unstable (fluctuates) when the step-down mode and the step-up mode are switched (when each operation mode is shifted).

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a step-up / step-down switching power supply circuit capable of suppressing fluctuations in output voltage at the time of transition to an operation mode.

  The switching power supply circuit according to claim 1 performs a step-up operation in which an input voltage applied to a power supply input terminal is boosted and output from the power supply output terminal, and a step-down operation in which the input voltage is stepped down and output from the power supply output terminal. This is a step-up / step-down switching power supply circuit. The switching power supply circuit includes a step-up switching element that performs a switching operation during a step-up operation, a step-down switching element that performs a switching operation during a step-down operation, a voltage detection circuit that outputs a detection voltage corresponding to an output voltage at a power supply output terminal, and a step-up operation A drive signal generation circuit for generating a drive signal for driving the switching element and the step-down switching element, a step-up drive circuit for driving the step-up switching element based on the drive signal, and a step-down switching element based on the drive signal And a step-down driving circuit for driving.

  When the drive signal generation circuit operates in the boost mode, a PWM signal having a duty corresponding to the reference voltage corresponding to the target value of the detection voltage and the output voltage is output as a drive signal to the boost drive circuit. Thus, the switching operation of the boosting switching element is feedback-controlled so that the output voltage obtained by boosting the input voltage becomes a desired target value, and the boosting operation described above is performed. When the drive signal generation circuit operates in the step-down mode, a PWM signal having a duty corresponding to the detected voltage and the reference voltage is output as a drive signal to the step-down drive circuit. Thus, the switching operation of the step-down switching element is feedback-controlled so that the output voltage obtained by stepping down the input voltage becomes a desired target value, and the step-down operation described above is performed.

  As described in the description of the prior art, the period during which the operation in the step-down mode is shifted to the operation in the step-up mode (step-up transition period) and the period during which the operation in the boost mode is shifted to the operation in the step-down mode (step-down) During the transition period, there may be a problem that the output voltage fluctuates. The reason why such a problem occurs is considered to be as follows.

  In other words, at the end of the step-down mode, the output voltage is similarly lowered as the input voltage is lowered, and the output voltage is greatly below the target value, that is, the detected voltage is well below the reference voltage. . Therefore, the on-duty of the PWM signal is a maximum value or a value close thereto. If the step-up mode is shifted to this state, the period during which the step-up switching element is turned on becomes longer from the beginning by the feedback control. As a result, the output voltage rapidly increases immediately after the start of the boost mode. As a result, overshoot of the output voltage occurs and time is required for feedback control immediately after the start of the boost mode, resulting in a problem that the output voltage becomes unstable (fluctuates).

  In addition, at the end of the boost mode, the output voltage increases in the same manner as the input voltage increases, and the output voltage greatly exceeds the target value, that is, the detected voltage greatly exceeds the reference voltage. . Therefore, the on-duty of the PWM signal is a minimum value or a value close thereto. When shifting to the step-down mode in such a state, the period during which the step-down switching element is turned on is shortened from the beginning by the feedback control. As a result, the output voltage rapidly decreases immediately after the start of the step-down mode. As a result, undershoot of the output voltage occurs, and time is required for feedback control immediately after the start of the step-down mode. As a result, there arises a problem that the output voltage becomes unstable (fluctuates).

  In order to suppress the occurrence of such a problem, in this means, the drive signal generation circuit performs the following operation in one or both of the step-up transition period and the step-down transition period. That is, the drive signal generation circuit outputs the first fixed pulse signal having the first pulse width smaller than the maximum value of the pulse width (on duty) indicating the ON period of the PWM signal in the step-down mode in the step-up transition period. It operates in a fixed duty boost mode in which it is output to the boost drive circuit as a drive signal.

  As a result, during the boost transition period, a boost operation not related to the feedback control is performed. Along with this, the decrease in the output voltage is reduced or the output voltage starts to increase, so that the difference between the detection voltage and the reference voltage becomes small. Therefore, when the boosting mode is started after that, the period during which the boosting switching element is turned on is shorter than the synchronization period when the step-down mode is directly shifted to the boosting mode. This makes it difficult for output voltage overshoot or the like to occur, and as a result, the occurrence of a problem that the output voltage fluctuates during the boost transition period is suppressed.

  In the step-down transition period, the drive signal generation circuit outputs a second fixed pulse signal having a second pulse width larger than the minimum value of the pulse width (on-duty) indicating the ON period of the PWM signal in the step-up mode. It operates in a fixed duty step-down mode that is output as a drive signal to a step-down drive circuit. Thereby, the step-down operation not related to the feedback control is performed during the step-down transition period. Accordingly, an increase in the output voltage is reduced or the output voltage starts to decrease, so that the difference between the detection voltage and the reference voltage is reduced. Therefore, when the step-down mode is started after that, the period during which the step-down switching element is turned on is longer than the synchronization period when the step-down mode is directly shifted to the step-down mode. As a result, undershoot of the output voltage is less likely to occur, and as a result, the occurrence of a problem that the output voltage fluctuates during the step-down transition period is suppressed.

  Thus, according to the means described in claim 1, it is possible to obtain an effect that the fluctuation of the output voltage in at least one of the step-up transition period and the step-down transition period can be suppressed. According to a second aspect of the present invention, the drive signal generation circuit has both a fixed duty boost mode and a fixed duty step down mode. Therefore, according to the means of the second aspect, it is possible to obtain an effect that the fluctuation of the output voltage can be surely suppressed in both the step-up transition period and the step-down transition period.

1 is a block diagram of a step-up / step-down switching power supply circuit showing a first embodiment. The figure which shows the relationship between the input voltage, the switching signal and the operating state of each part Timing chart showing the waveform of each part FIG. 1 equivalent diagram showing the second embodiment 2 equivalent diagram 3 equivalent figure FIG. 1 equivalent diagram showing the third embodiment 2 equivalent diagram FIG. 1 equivalent view showing the fourth embodiment

Hereinafter, a plurality of embodiments of a switching power supply circuit will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
A power supply circuit 1 shown in FIG. 1 is used in, for example, an ECU mounted on a vehicle. The power supply circuit 1 includes transistors T1 and T2, diodes D1 and D2, an inductor L1, a capacitor C1, a step-down driver 2, a step-up driver 3, a voltage control circuit 4, and the like. The transistors T1 and T2 are both N-channel MOS transistors.

  For example, the power supply circuit 1 boosts an input voltage Vi supplied from a vehicle-mounted battery (not shown) to the power input terminal P1 and outputs the boosted voltage from the power output terminal P2, and a step-down operation that lowers and outputs the input voltage Vi. This is a step-up / step-down switching power supply circuit. During the step-down operation, the driving of the transistor T1 is controlled by PWM (Pulse Width Modulation). That is, the transistor T1 corresponds to a step-down switching element that performs a switching operation during the step-down operation. During the boosting operation, the drive of the transistor T2 is PWM controlled. That is, the transistor T2 corresponds to a boosting switching element that performs a switching operation during the boosting operation.

  The drain of the transistor T1 is connected to the power input terminal P1. Between the power input terminal P1 and the ground terminal (not shown), an input voltage Vi (for example, a steady value of +12 V) is applied from the in-vehicle battery. The ground terminal is connected to the ground line 5. The source of the transistor T1 is connected to the node N1. A driving voltage is applied from the step-down driver 2 to the gate of the transistor T1. The diode D1 is connected between the node N1 and the ground line 5 (0 V) with the ground line 5 side as an anode. The diode D1 functions as a free wheeling diode during the step-down operation.

  The drain of the transistor T2 is connected to the node N2. The source of the transistor T2 is connected to the ground line 5. A driving voltage is applied from the boosting driver 3 to the gate of the transistor T2. A smoothing inductor L1 is connected between the nodes N1 and N2. The diode D2 is connected between the node N2 and the power supply output terminal P2 with the node N2 side as an anode. The diode D2 functions as a free wheeling diode during the boosting operation. The smoothing capacitor C <b> 1 is connected between the power output terminal P <b> 2 and the ground line 5. The voltage (output voltage Vo) at the power supply output terminal P2 is given to the voltage control circuit 4 (feedback). An output voltage Vo (for example, the target value is +5 V) output via the power output terminal P2 and the ground terminal is supplied to a load (not shown) such as a microcomputer.

  The step-down driver 2 (corresponding to a step-down drive circuit) outputs a drive voltage for driving the transistor T1 on or off based on the drive signal Sa supplied from the voltage control circuit 4 to the gate of the transistor T1. The step-down driver 2 drives the transistor T1 on during the period when the drive signal Sa is at the H level, and turns off the transistor T1 during the period when the drive signal Sa is at the L level.

  The boosting driver 3 (corresponding to the boosting drive circuit) outputs a drive voltage for driving the transistor T2 on or off based on the drive signal Sb supplied from the voltage control circuit 4 to the gate of the transistor T2. The step-up driver 3 drives the transistor T2 on during the period when the drive signal Sb is at the H level, and turns off the transistor T2 during the period when the drive signal Sb is at the L level.

  The voltage control circuit 4 (drive signal generation circuit) has four operation modes (step-down mode, step-up mode, fixed duty step-down mode, and fixed duty step-up mode). The contents of each operation mode will be described later. The voltage control circuit 4 operates in one of the four operation modes according to the voltage value of the input voltage Vi.

Specifically, the voltage control circuit 4 operates in the step-down mode while the input voltage Vi is equal to or higher than the first threshold value Vth1. In addition, the voltage control circuit 4 operates in the fixed duty step-down mode for a period in which the input voltage Vi is less than the first threshold Vth1 and greater than or equal to the second threshold Vth2. Further, the voltage control circuit 4 operates in the fixed duty boost mode during a period in which the input voltage Vi is less than the second threshold value Vth2 and greater than or equal to the third threshold value Vth3. Further, the voltage control circuit 4 operates in the boost mode during the period when the input voltage Vi is less than the third threshold value Vth3. The relationship between the threshold values is as shown in the following equation (1).
Vth3 <Vth2 <Vth1 (1)

  When the voltage control circuit 4 operates in the step-down mode, the drive signal Sb output to the step-up driver 3 is fixed at the L level. Therefore, in the step-down mode, the transistor T2 is always off and the power supply circuit 1 is in the step-down type. The voltage control circuit 4 then outputs a drive signal Sa to the step-down driver 2 so that the output voltage Vo matches the target value based on the difference between the target value of the output voltage Vo and the fed back output voltage Vo. The duty ratio is changed (voltage feedback control). That is, when the voltage control circuit 4 operates in the step-down mode, the voltage control circuit 4 outputs the PWM signal to the step-down driver 2 as the drive signal Sa.

  When operating in the boost mode, the voltage control circuit 4 fixes the drive signal Sa output to the step-down driver 2 at the H level. Therefore, in the boost mode, the transistor T1 is always on and the power supply circuit 1 is in the boost type. The voltage control circuit 4 then outputs a drive signal Sb to be output to the booster driver 3 so that the output voltage Vo matches the target value based on the difference between the target value of the output voltage Vo and the feedback output voltage Vo. The duty ratio is changed (voltage feedback control). That is, when operating in the boost mode, the voltage control circuit 4 outputs the PWM signal as the drive signal Sb to the boost driver 3.

  When the voltage control circuit 4 operates in the fixed duty step-down mode, the drive signal Sb output to the boosting driver 3 is fixed at the L level. Therefore, in the fixed duty step-down mode, the transistor T2 is always off and the power supply circuit 1 is in the step-down type. Then, the voltage control circuit 4 outputs a pulse signal (corresponding to the second fixed pulse signal) having a fixed pulse width (second pulse width) to the step-down driver 2 as the drive signal Sa.

  The pulse width referred to here represents the ON period, and is the width when the pulse signal is at the H level. That is, when the voltage control circuit 4 operates in the fixed duty step-down mode, the on-duty of the drive signal Sa output to the step-down driver 2 is fixed. The second pulse width may be a width larger than the minimum value of the pulse width representing the ON period of the PWM signal in the boost mode. In the present embodiment, the second pulse width is set so that the on-duty of the drive signal Sa is fixed at 95%.

  When operating in the fixed duty boost mode, the voltage control circuit 4 fixes the drive signal Sa output to the step-down driver 2 to the H level. Therefore, in the fixed duty boost mode, the transistor T1 is always on and the power supply circuit 1 is in a boost type configuration. Then, the voltage control circuit 4 outputs a pulse signal (first fixed pulse signal) having a fixed pulse width (first pulse width) to the boosting driver 3 as the drive signal Sb.

  That is, when operating in the fixed duty boost mode, the voltage control circuit 4 fixes the on duty of the drive signal Sb output to the boost driver 3. The first pulse width may be a width smaller than the maximum value of the pulse width representing the ON period of the PWM signal in the step-down mode. In the present embodiment, the first pulse width is set so that the on-duty of the drive signal Sb is fixed at 5%.

  The voltage control circuit 4 may be of any configuration that can realize each of the above-described operations. For example, a specific configuration as shown in FIG. 1 can be adopted. That is, in this embodiment, the voltage control circuit 4 includes an input voltage determination circuit 6, a reference voltage generation circuit 7, AND circuits 8 to 10, a NAND circuit 11, an output voltage detection circuit 12 (corresponding to a voltage detection circuit), an error amplifier. 13 (corresponding to an error amplification circuit), a threshold selection circuit 14 (corresponding to an input signal switching circuit), a comparator 15 (corresponding to a comparison circuit), a triangular wave oscillation circuit 16, a selector circuit 17, an inverter circuit 18 and the like.

  The input voltage determination circuit 6 includes resistors R1 to R4 and comparators CP1 to CP3. The resistors R1 to R4 are connected in series between the power input terminal P1 and the ground line 5. The voltage at the node N3, which is an interconnection point between the resistors R1 and R2, is applied to the inverting input terminal of the comparator CP1. The voltage at the node N4, which is an interconnection point between the resistors R2 and R3, is applied to the inverting input terminal of the comparator CP2. The voltage at the node N5, which is an interconnection point between the resistors R3 and R4, is applied to the inverting input terminal of the comparator CP3.

  A reference voltage Vr1 for determining the voltage value of the input voltage Vi is applied to the non-inverting input terminals of the comparators CP1 to CP3. In the present embodiment, the reference voltage Vr1 is generated by a reference voltage generation circuit 7 described later. Switching signals S1 to S3 output from comparators CP1 to CP3 are applied to AND circuits 8 to 10 and NAND circuit 11. The resistance values (voltage division ratio) of the resistors R1 to R4 and the voltage value of the reference voltage Vr1 are set to values that satisfy the following conditions (a) to (d).

(A) During the period when the input voltage Vi is equal to or higher than the first threshold value Vth1, the switching signals S1 to S3 are all at the L level.
(B) While the input voltage Vi is less than the first threshold value Vth1 and greater than or equal to the second threshold value Vth2, the switching signals S1 and S2 become L level and the switching signal S3 becomes H level.
(C) While the input voltage Vi is less than the second threshold value Vth2 and greater than or equal to the third threshold value Vth3, the switching signal S1 is at L level and the switching signals S2, S3 are at H level.
(D) During the period when the input voltage Vi is less than the third threshold value Vth3, the switching signals S1 to S3 are all at the H level.

  The resistors R5 and R6 of the output voltage detection circuit 12 are connected in series between the power supply output terminal P2 and the ground line 5. A detection voltage Vd obtained by dividing the voltage of the node N6, which is an interconnection point of the resistors R5 and R6, that is, the output voltage Vo by the resistors R5 and R6, is applied to the inverting input terminal of the error amplifier 13.

  The reference voltage generation circuit 7 is mainly composed of, for example, a band gap reference circuit (BGR), and generates the above-described reference voltage Vr1 and the reference voltage Vr2 for instructing the target value of the output voltage Vo. A reference voltage Vr2 (for example, 1.22 V) generated by the reference voltage generation circuit 7 is given to the non-inverting input terminal of the error amplifier 13. A feedback resistor Rf is connected between the output terminal and the inverting input terminal of the error amplifier 13. The error amplifier 13 outputs an error signal Sc obtained by amplifying the error of the detection voltage Vd with respect to the reference voltage Vr2.

  The threshold selection circuit 14 selects one of the error signal Sc and the fixed duty generation threshold signal Sd output from the error amplifier 13 and outputs the selected signal to the subsequent comparator 15. The fixed duty generation threshold signal Sd (corresponding to the first threshold signal and the second threshold signal) is a signal fixed at a constant level, and is a signal for fixing the duty of the drive signals Sa and Sb.

  The threshold selection circuit 14 selects each of the signals based on the selection signal Se. That is, the threshold selection circuit 14 outputs the error signal Sc to the subsequent stage when the selection signal Se is at the L level, and outputs the fixed duty generation threshold signal Sd to the subsequent stage when the selection signal Se is at the H level. The selection signal Se described above is an output signal of the AND circuit 8. A switching signal S <b> 1 is given to the inverting input terminal of the AND circuit 8. A switching signal S3 is given to the non-inverting input terminal of the AND circuit 8.

  The triangular wave oscillation circuit 16 generates a triangular wave signal Sf (corresponding to a carrier signal) that is a PWM carrier wave. The error signal Sc output from the threshold selection circuit 14 or the fixed duty generation threshold signal Sd is supplied to the non-inverting input terminal of the comparator 15. A triangular wave signal Sf output from the triangular wave oscillation circuit 16 is given to the inverting input terminal of the comparator 15.

  With such a configuration, the output signal of the comparator 15 becomes L level in a period in which the error signal Sc or the fixed duty generation threshold signal Sd is smaller than the triangular wave signal Sf, and the error signal Sc or the fixed duty generation threshold signal Sd is from the triangular wave signal Sf. It becomes H level during a long period. That is, the comparator 15 compares the error signal Sc or the fixed duty generation threshold signal Sd with the triangular wave signal Sf, and generates a duty signal Sg having a duty according to the comparison result.

  Note that the level of the fixed duty generation threshold signal Sd is the ratio of the period in which the output signal of the comparator 15 is at the H level when the signal is supplied to the comparator 15 (the ratio of the period in which the H level is in one cycle). Is set to a value that is 95%. Therefore, when the selection signal Se is at the H level, the duty signal Sg output from the comparator 15 is fixed to 95% on-duty.

  The switching signal S2 is given to one inverting input terminal of the NAND circuit 11. A duty signal Sg output from the comparator 15 is supplied to the other inverting input terminal of the NAND circuit 11. The output signal of the NAND circuit 11 is given to the step-down driver 2 as the drive signal Sa.

  The four non-inverting input terminals of the AND circuit 9 are supplied with the switching signals S1 to S3 and the duty signal Sg output from the comparator 15, respectively. A switching signal S <b> 1 is given to the inverting input terminal of the AND circuit 10. Switching signals S2 and S3 are given to the two non-inverting input terminals of the AND circuit 10, respectively. The output signal of the AND circuit 9 is given to one input terminal (0) of the selector circuit 17. A duty signal Sg ′ is given to the other input terminal (1) of the selector circuit 17. The duty signal Sg ′ is an output signal of the inverter circuit 18 that receives the duty signal Sg, and is a signal obtained by inverting the duty signal Sg. The output signal of the AND circuit 10 is given to the selection terminal of the selector circuit 17 as the selection signal Sh. The output signal of the selector circuit 17 is given to the boosting driver 3 as the drive signal Sb.

  According to the voltage control circuit 4 having the above configuration, as shown in FIG. 2, the levels of the switching signals S1 to S3 are switched according to the voltage value of the input voltage Vi, so that the above-described operations are realized as follows. be able to. That is, during the period when the input voltage Vi is equal to or higher than the first threshold value Vth1, the switching signals S1 to S3 are all at the L level. As a result, the selection signal Sh becomes L level and the output signal of the AND circuit 9 becomes L level, so that the drive signal Sb is fixed at L level. Therefore, the transistor T2 is always off.

  Since the selection signal Se becomes L level, the error signal Sc output from the error amplifier 13 is given to the comparator 15. Therefore, the comparator 15 outputs a duty signal Sg having a duty corresponding to the comparison result between the error signal Sc and the triangular wave signal Sf. Then, a drive signal Sa having the same logic as the duty signal Sg is output from the NAND circuit 11. As a result, the drive of the transistor T1 is duty-controlled by the error amplifier 13. Thus, the voltage control circuit 4 operates in the step-down mode while the input voltage Vi is equal to or higher than the first threshold value Vth1.

  In addition, during a period in which the input voltage Vi is less than the first threshold value Vth1 and greater than or equal to the second threshold value Vth2, the switching signals S1 and S2 are at the L level and the switching signal S3 is at the H level. As a result, the selection signal Sh becomes L level and the output signal of the AND circuit 9 becomes L level, so that the drive signal Sb is fixed at L level. Therefore, the transistor T2 is always off.

  Since the selection signal Se becomes H level, the fixed duty generation threshold signal Sd is given to the comparator 15. Therefore, the comparator 15 outputs a duty signal Sg having a fixed on-duty (95%) regardless of the error signal Sc. Then, a drive signal Sa having the same logic as the duty signal Sg is output from the NAND circuit 11. As a result, the transistor T1 is driven with an on-duty of 95% regardless of the control of the error amplifier 13. As described above, the voltage control circuit 4 operates in the fixed duty step-down mode during a period in which the input voltage Vi is less than the first threshold value Vth1 and greater than or equal to the second threshold value Vth2.

  Further, during a period in which the input voltage Vi is less than the second threshold value Vth2 and equal to or greater than the third threshold value Vth3, the switching signal S1 becomes L level and the switching signals S2 and S3 become H level. As a result, the selection signal Se becomes the H level, and thus the fixed duty generation threshold signal Sd is given to the comparator 15. Therefore, the comparator 15 outputs a duty signal Sg having a fixed on-duty (95%) regardless of the error signal Sc. However, since the switching signal S2 is at the H level, the drive signal Sa output from the NAND circuit 11 is fixed at the H level. Therefore, the transistor T1 is always on (full on).

  Since the selection signal Sh becomes H level, the selector circuit 17 outputs the drive signal Sb having the same logic as that of the duty signal Sg ′, that is, having the logic opposite to that of the duty signal Sg. As a result, the transistor T2 is driven with an on-duty of 5% regardless of the control of the error amplifier 13. As described above, the voltage control circuit 4 operates in the fixed duty boost mode during a period in which the input voltage Vi is less than the second threshold Vth2 and equal to or greater than the third threshold Vth3.

  Further, the switching signals S1 to S3 are all at the H level during the period when the input voltage Vi is less than the third threshold value Vth3. As a result, the selection signal Se becomes L level, and the error signal Sc output from the error amplifier 13 is given to the comparator 15. Therefore, the comparator 15 outputs a duty signal Sg having a duty corresponding to the comparison result between the error signal Sc and the triangular wave signal Sf. However, since the switching signal S2 is at the H level, the drive signal Sa output from the NAND circuit 11 is fixed at the H level. Therefore, the transistor T1 is always on (full on).

  Then, the selection signal Sh becomes L level, and the same signal as the duty signal Sg is given to one input terminal (0) of the selector circuit 17. Therefore, the drive signal Sb having the same logic as the duty signal Sg is output from the selector circuit 17. As a result, the drive of the transistor T2 is duty-controlled by the error amplifier 13. As described above, during the period in which the input voltage Vi is less than the third threshold value Vth3, the voltage control circuit 4 operates in the boost mode.

  As described above, in the voltage control circuit 4 of the present embodiment, there is one voltage boost operation (operation in the boost mode and fixed duty boost mode) and one step-down operation (operation in the step-down mode and fixed duty step-down mode). The error amplifier 13 and one comparator 15 are commonly used. According to such a configuration, the circuit configuration can be simplified in the step-up operation and the step-down operation, compared to a configuration in which separate error amplifiers (error amplification circuits) and comparators (comparison circuits) are provided. It is done.

  As described in the description of the prior art, in the step-up transition period in which the operation in the step-down mode is shifted to the operation in the step-up mode and in the step-down transition period in which the operation in the step-up mode is shifted to the operation in the step-down mode. May cause a problem that the output voltage Vo fluctuates. The reason why such a problem occurs is considered to be as follows.

  That is, at the end of the step-down mode, the output voltage Vo similarly decreases as the input voltage Vi decreases, and the output voltage Vo is greatly below the target value, that is, the detection voltage Vd is significantly below the reference voltage Vr2. It is in a state. Therefore, the on-duty of the duty signal Sg is a maximum value or a value close thereto. If the voltage is shifted to the step-up mode in such a state, the period during which the step-up transistor T2 is turned on becomes longer by the voltage feedback control by the error amplifier 13 from the beginning. As a result, the output voltage Vo rapidly increases immediately after the start of the boost mode. For this reason, overshoot of the output voltage Vo occurs, and time is required for feedback control immediately after the start of the boost mode, and as a result, the output voltage Vo becomes unstable (varies).

  Further, at the end of the boost mode, the output voltage Vo increases in the same manner as the input voltage Vi increases, and the output voltage Vo greatly exceeds the target value, that is, the detection voltage Vd greatly exceeds the reference voltage Vr2. It is in a state. Therefore, the on-duty of the duty signal Sg is a minimum value or a value close thereto. When the step-down mode is entered in this state, the period during which the step-down transistor T1 is turned on is shortened from the beginning by the voltage feedback control by the error amplifier 13. As a result, the output voltage Vo rapidly decreases immediately after the start of the step-down mode. Therefore, undershoot of the output voltage Vo occurs, for example, the feedback control immediately after the start of the step-down mode takes time, and as a result, the output voltage Vo becomes unstable (varies).

  In the present embodiment, the voltage control circuit 4 performs the following operation to suppress the occurrence of such a problem. That is, the voltage control circuit 4 operates in the fixed duty step-down mode during a period in which the input voltage Vi is less than the first threshold value Vth1 and greater than or equal to the second threshold value Vth2. Therefore, the voltage control circuit 4 operates in the fixed duty step-down mode in the first half of the boost transition period (time t1 to t2 in FIG. 3). The voltage control circuit 4 operates in the fixed duty boost mode during a period in which the input voltage Vi is less than the second threshold value Vth2 and greater than or equal to the third threshold value Vth3. Therefore, in the second half of the boost transition period (time t2 to t3 in FIG. 3), the voltage control circuit 4 operates in the fixed duty boost mode.

  As a result, during the step-up transition period, a step-down operation and a step-up operation that are not related to the voltage feedback control by the error amplifier 13 are performed. Along with the boosting operation performed in the latter half of the boosting transition period, the decrease in the output voltage Vo is reduced or the output voltage Vo starts to increase. Therefore, even if the detection voltage Vd exceeds or falls below the reference voltage Vr2, the difference between them becomes small.

  As a result, when the boost mode is subsequently started (time t3 in FIG. 3), the error signal Sc output from the error amplifier 13 becomes a low level. Accordingly, at the start of the boost mode, the period during which the transistor T2 is turned on (the on-duty of the transistor T2) is a minimum value (for example, 3%), which is the same as when the step-down mode is directly shifted to the boost mode. Shorter than the period. As a result, overshoot of the output voltage Vo is less likely to occur, and as a result, the occurrence of a problem that the output voltage Vo fluctuates during the boosting transition period is suppressed.

  Further, in the fixed duty boost mode, the boosting transistor T2 is driven at an on-duty of 5%, which is close to the minimum on-duty value (3%). As a result, the on-duty (5%) of the transistor T2 in the second half of the boosting transition period is close to the on-duty (3%) of the transistor T2 at the start of the boosting mode to be executed thereafter. Therefore, since the transition from the fixed duty boost mode to the boost mode can be performed smoothly, fluctuations in the output voltage Vo can be further suppressed.

  The voltage control circuit 4 operates in the fixed duty boost mode in the first half of the step-down transition period (time t4 to t5 in FIG. 3), and in the second half of the step-up transition period (time t5 to t6 in FIG. 3). Operates in buck mode. Thus, during the step-down transition period, a step-up operation and a step-down operation that are not related to the voltage feedback control by the error amplifier 13 are performed. Then, with the step-down operation performed in the latter half of the step-down transition period, the increase in the output voltage Vo is reduced or the output voltage Vo starts to decrease. Therefore, even if the detection voltage Vd is lower than or higher than the reference voltage Vr2, the difference between them is reduced.

  Thereby, when the step-down mode is subsequently started (time t6 in FIG. 3), the error signal Sc output from the error amplifier 13 becomes a high level. Therefore, at the start of the step-down mode, the period during which the transistor T1 is turned on (the on-duty of the transistor T1) has a maximum value (for example, 97%). Longer than the period. As a result, an undershoot of the output voltage Vo is unlikely to occur, and as a result, the occurrence of a problem that the output voltage Vo fluctuates during the step-down transition period is suppressed.

  Further, in the fixed duty step-down mode, the step-down transistor T1 is driven with an on-duty of 95%, which is close to the maximum value (97%) of the on-duty. As a result, the on-duty (95%) of the transistor T1 in the second half of the step-down transition period and the on-duty (97%) of the transistor T1 at the start of the step-down mode to be executed thereafter are close to each other. Therefore, since the transition from the fixed duty step-down mode to the step-down mode can be performed smoothly, fluctuations in the output voltage Vo can be further suppressed.

  The voltage control circuit 4 is configured to switch between the four operation modes described above according to the voltage value of the input voltage Vi. Therefore, even if the input voltage Vi suddenly increases for some reason in the latter half of the boost transition period in which the input voltage Vi gradually decreases and shifts from the step-down mode to the step-up mode, the step-down mode after passing through the fixed duty step-down mode. Therefore, the problem that the output voltage Vo fluctuates hardly occurs. Further, even if the input voltage Vi suddenly decreases for any reason in the second half of the step-down transition period in which the input voltage Vi gradually increases and shifts from the step-up mode to the step-down mode, the step-up mode is started after passing through the fixed duty step-up mode. Therefore, the problem that the output voltage Vo fluctuates hardly occurs.

  As described above, the power supply circuit 1 according to the present embodiment performs the operations in the fixed duty step-down mode and the fixed duty step-up mode for driving the transistors T1 and T2 with a fixed on-duty regardless of the control of the error amplifier 13. It is possible. The step-up transition period includes an operation in the fixed-duty step-up mode, and the step-down transition period includes an operation in the fixed-duty step-down mode. Therefore, according to the present embodiment, there is an effect that the fluctuation of the output voltage Vo can be reliably suppressed in both the step-up transition period and the step-down transition period.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
A power supply circuit 21 (corresponding to a switching power supply circuit) of the present embodiment shown in FIG. 4 differs from the power supply circuit 1 of the first embodiment shown in FIG. The signal generation circuit). The voltage control circuit 22 considers not only the voltage value of the input voltage Vi but also the transition of the value, and is in one of the operation modes of the step-down mode, the step-up mode, the fixed duty step-down mode, and the fixed duty step-up mode. Works with.

  Specifically, the voltage control circuit 22 operates in the step-down mode during a period in which the input voltage Vi is equal to or higher than the first threshold value Vth1, regardless of the value of the input voltage Vi before that. In addition, the voltage control circuit 22 operates in the boost mode during the period in which the input voltage Vi is less than the third threshold value Vth3, regardless of the value of the input voltage Vi before that. Further, the voltage control circuit 22 has a period before the transition to the common transition period in a period in which the input voltage Vi is less than the first threshold Vth1 and is equal to or greater than the third threshold Vth3 (hereinafter referred to as a common transition period). It operates in either the fixed duty step-up mode or the fixed duty step-down mode according to the voltage value of the input voltage Vi.

  That is, before the transition to the common transition period, the voltage control circuit 22 operates in the fixed duty boost mode when the input voltage Vi is equal to or higher than the first threshold value Vth1. In addition, the voltage control circuit 22 operates in the fixed duty step-down mode when the input voltage Vi is less than the third threshold value Vth3 before the transition to the common transition period.

  The voltage control circuit 22 only needs to have a configuration capable of realizing the above-described operations. For example, a specific configuration as shown in FIG. 4 can be adopted. That is, the voltage control circuit 22 of the present embodiment has a sequencer 23 newly added to the voltage control circuit 4, a point that the AND circuit 8 is omitted, and a threshold selection circuit 24 instead of the threshold selection circuit 14. (Corresponding to an input signal switching circuit), a NAND circuit 25 in place of the NAND circuit 11, and AND circuits 26 and 27 in place of the AND circuits 9 and 10 are different. .

  Switching signals S <b> 1 to S <b> 3 output from the input voltage determination circuit 6 are input to the sequencer 23. The sequencer 23 acquires the levels of the switching signals S1 to S3 every predetermined period, and determines the levels of the switching signals S4 to S7 to be output based on the acquired levels. The switching signals S4 to S7 output from the sequencer 23 are given to the threshold selection circuit 24, the NAND circuit 25, and the AND circuits 26 and 27. The relationship of input / output signals in the sequencer 23 is as shown in FIG. Note that “*” in FIG. 5 indicates that the level may be H level or L level.

  That is, when all the switching signals S1 to S3 acquired in a predetermined cycle (sequence n in FIG. 5) are at the L level, the sequencer 23 acquires in the previous cycle (sequence n-1 in FIG. 5). Regardless of the level of the switched signals S1 to S3, the switching signals S4 to S6 are set to H level and the switching signal S7 is set to L level. Further, when all the switching signals S1 to S3 acquired in the predetermined cycle are at the H level, the sequencer 23 switches the switching signal S4 regardless of the level of the switching signals S1 to S3 acquired in the immediately preceding cycle. , S6 and S7 are set to H level, and the switching signal S5 is set to L level.

  In addition, when the switching signal S1 acquired in a predetermined cycle is at the L level and the switching signal S3 is at the H level, the sequencer 23 sets the level of the switching signals S1 to S3 acquired in the previous cycle. Accordingly, the levels of the switching signals S4 to S7 are set as follows. That is, in this case, the sequencer 23 sets the switching signals S5 and S6 to the H level and sets the switching signals S4 and S7 to the L level if all the switching signals S1 to S3 acquired in the previous cycle are at the H level. To level. In this case, the sequencer 23 sets all the switching signals S4 to S7 to the L level if all the switching signals S1 to S3 acquired in the previous cycle are the L level.

  The threshold selection circuit 24 selects one of the error signal Sc and the fixed duty generation threshold signal Sd based on the switching signal S4 provided from the sequencer 23, and outputs the selected signal to the comparator 15. That is, the threshold selection circuit 24 outputs the error signal Sc to the subsequent stage when the switching signal S4 is at the H level, and outputs the fixed duty generation threshold signal Sd to the subsequent stage when it is at the L level. A switching signal S5 is applied to the non-inverting input terminal of the NAND circuit 25. A duty signal Sg is given to the inverting input terminal of the NAND circuit 25. The output signal of the NAND circuit 25 is given to the step-down driver 2 as the drive signal Sa.

  The four non-inverting input terminals of the AND circuit 26 are supplied with switching signals S4, S6, S7 and a duty signal Sg, respectively. A switching signal S5 is given to the inverting input terminal of the AND circuit 26. The output signal of the AND circuit 26 is given to one input terminal (0) of the selector circuit 17. Switching signals S4 to S7 are given to the four inverting input terminals of the AND circuit 27, respectively. The output signal of the AND circuit 27 is given to the selection terminal of the selector circuit 17 as the selection signal Sh.

  According to the voltage control circuit 22 having the above configuration, the level of the switching signals S4 to S7 is switched according to the voltage value of the input voltage Vi and the transition of the value as shown in FIG. Each operation can be realized. That is, while the input voltage Vi is equal to or higher than the first threshold value Vth1, the switching signals S4 to S6 are at the H level and the switching signal S7 is at the L level. As a result, the selection signal Sh becomes L level and the output signal of the AND circuit 26 becomes L level, so that the drive signal Sb is fixed at L level. Therefore, the transistor T2 is always off.

  Since the switching signal S4 is at the H level, the error signal Sc is given to the comparator 15. Therefore, the comparator 15 outputs a duty signal Sg having a duty corresponding to the comparison result between the error signal Sc and the triangular wave signal Sf. Then, the drive signal Sa having the same logic as the duty signal Sg is output from the NAND circuit 25. As a result, the drive of the transistor T1 is duty-controlled (Duty control) by the error amplifier 13. Thus, the voltage control circuit 22 operates in the step-down mode while the input voltage Vi is equal to or higher than the first threshold value Vth1.

  Also, from the period when the input voltage Vi is equal to or higher than the first threshold Vth1, that is, the period during which the voltage control circuit 22 operates in the step-down mode as described above, the input voltage Vi is less than the first threshold Vth1 and equal to or higher than the third threshold Vth3. When switching to a certain period, the switching signals S4 to S7 are all at the L level. As a result, the fixed duty generation threshold signal Sd is given to the comparator 15. Therefore, the comparator 15 outputs a duty signal Sg having a fixed on-duty (95%) regardless of the error signal Sc. However, since the switching signal S5 is at the L level, the drive signal Sa output from the NAND circuit 25 is fixed at the H level. Therefore, the transistor T1 is always on (full on).

  Since the selection signal Sh becomes H level, the selector circuit 17 outputs the drive signal Sb having the same logic as that of the duty signal Sg ′, that is, having the logic opposite to that of the duty signal Sg. As a result, the transistor T2 is driven with an on-duty of 5% regardless of the control of the error amplifier 13. As described above, when the input voltage Vi transitions from the period in which the input voltage Vi is equal to or higher than the first threshold Vth1 to the period in which the input voltage Vi is lower than the first threshold Vth1 and equal to or higher than the third threshold Vth3, the voltage control circuit 22 operates in the fixed duty boost mode. To do.

  Further, during a period in which the input voltage Vi is less than the third threshold value Vth3, the switching signals S4, S6, and S7 are at the H level and the switching signal S5 is at the L level. As a result, the error signal Sc is given to the comparator 15. Therefore, the comparator 15 outputs a duty signal Sg having a duty corresponding to the comparison result between the error signal Sc and the triangular wave signal Sf. However, since the switching signal S5 is at the L level, the drive signal Sa output from the NAND circuit 25 is fixed at the H level. Therefore, the transistor T1 is always on (full on).

  Then, the selection signal Sh becomes L level, and the same signal as the duty signal Sg is given to one input terminal (0) of the selector circuit 17. Therefore, the drive signal Sb having the same logic as the duty signal Sg is output from the selector circuit 17. As a result, the drive of the transistor T2 is duty-controlled by the error amplifier 13. Thus, the voltage control circuit 22 operates in the boost mode during the period when the input voltage Vi is less than the third threshold value Vth3.

  Further, from the period in which the input voltage Vi is less than the third threshold value Vth3, that is, the period in which the voltage control circuit 22 operates in the boost mode as described above, the input voltage Vi is less than the first threshold value Vth1 and not less than the third threshold value Vth3. When the transition is made during the period, the switching signals S4 and S7 become L level, and the switching signals S5 and S6 become H level. As a result, the selection signal Sh becomes L level and the output signal of the AND circuit 26 becomes L level, so that the drive signal Sb is fixed at L level. Therefore, the transistor T2 is always off.

  Since the switching signal S4 is at the L level, the fixed duty generation threshold signal Sd is given to the comparator 15. Therefore, the comparator 15 outputs a duty signal Sg having a fixed on-duty (95%) regardless of the error signal Sc. Then, the drive signal Sa having the same logic as the duty signal Sg is output from the NAND circuit 25. As a result, the transistor T1 is driven with an on-duty of 95% regardless of the control of the error amplifier 13. As described above, when the input voltage Vi transitions from the period in which the input voltage Vi is less than the third threshold Vth3 to the period in which the input voltage Vi is less than the first threshold Vth1 and equal to or more than the third threshold Vth3, the voltage control circuit 22 is fixed. Operates in duty step-down mode.

  As described above, the voltage control circuit 22 operates in the fixed duty boost mode during the boost transition period (period from time t1 to time t2 in FIG. 6) in which the operation in the step-down mode is shifted to the operation in the boost mode. Perform the action. The voltage control circuit 22 operates in the fixed duty step-down mode during the step-down transition period (period from time t3 to t4 in FIG. 6) in which the operation in the step-up mode is shifted to the operation in the step-down mode. Therefore, also by the power supply circuit 21 of the present embodiment, as in the power supply circuit 1 of the first embodiment, it is possible to reliably suppress fluctuations in the output voltage Vo in both the step-up transition period and the step-down transition period. Is obtained.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS.
A power supply circuit 31 (corresponding to a switching power supply circuit) shown in FIG. 7 is different from the power supply circuit 1 of the first embodiment shown in FIG. The signal generation circuit). The voltage control circuit 32 performs the same operation as that of the voltage control circuit 4, but the specific configuration is different.

  That is, the voltage control circuit 32 of the present embodiment is different from the voltage control circuit 4 in that the AND circuit 8 and the threshold selection circuit 14 are omitted, and the AND circuits 33 and 34 and the reference voltage selection circuit 35 (fixed output) are newly added. It is different in that it is equipped with a circuit). In this case, the error signal Sc output from the error amplifier 13 is directly supplied to the non-inverting input terminal of the comparator 15.

  Switching signals S1 and S2 are applied to the inverting input terminal and the non-inverting input terminal of the AND circuit 33, respectively. The output signal of the AND circuit 33 is given to the reference voltage selection circuit 35 as the switching signal S8. Switching signals S2 and S3 are applied to the inverting input terminal and the non-inverting input terminal of the AND circuit 34, respectively. The output signal of the AND circuit 34 is given to the reference voltage selection circuit 35 as the switching signal S9.

  The reference voltage selection circuit 35 is supplied with a reference voltage Vr2, an upper fixed voltage Vα, and a lower fixed voltage Vβ. The upper fixed voltage Vα is set to a voltage value (for example, 2.0 V) that exceeds the maximum value of the detection voltage Vd. Further, the lower fixed voltage Vβ is set to a voltage value (for example, 0.5 V) that is lower than the minimum value of the detection voltage Vd. The reference voltage selection circuit 35 selects one of the reference voltage Vr2, the upper fixed voltage Vα, and the lower fixed voltage Vβ and outputs the selected voltage to the error amplifier 13 (the non-inverting input terminal) at the subsequent stage. The reference voltage selection circuit 35 selects each of the voltages based on the levels of the switching signals S8 and S9.

  That is, the reference voltage selection circuit 35 outputs the reference voltage Vr2 to the subsequent stage when both the switching signals S8 and S9 are at the L level. Further, when the switching signal S8 is at the L level and the switching signal S9 is at the H level, the reference voltage selection circuit 35 outputs the upper fixed voltage Vα to the subsequent stage. Further, the reference voltage selection circuit 35 outputs the lower fixed voltage Vβ to the subsequent stage when the switching signal S8 is at the H level and the switching signal S9 is at the L level.

  According to the voltage control circuit 32 having the above configuration, the levels of the switching signals S1 to S3, S8, and S9 are switched according to the voltage value of the input voltage Vi as shown in FIG. Operation can be realized. That is, during the period when the input voltage Vi is equal to or higher than the first threshold value Vth1, the switching signals S1 to S3 are all at the L level. Therefore, the boosting transistor T2 is always turned off by the same operation as in the first embodiment.

  Since both of the switching signals S8 and S9 are at the L level, the reference voltage Vr2 for instructing the target value of the output voltage Vo is supplied to the non-inverting input terminal of the error amplifier 13. As a result, the duty of the duty signal Sg output from the comparator 15 changes so that the output voltage Vo matches the target value. Then, a drive signal Sa having the same logic as the duty signal Sg is output from the NAND circuit 11. As a result, the drive of the step-down transistor T1 is duty-controlled by the error amplifier 13. Thus, the voltage control circuit 32 operates in the step-down mode while the input voltage Vi is equal to or higher than the first threshold value Vth1.

  In addition, during a period in which the input voltage Vi is less than the first threshold value Vth1 and greater than or equal to the second threshold value Vth2, the switching signals S1 and S2 are at the L level and the switching signal S3 is at the H level. Therefore, the boosting transistor T2 is always turned off by the same operation as in the first embodiment.

  Since the switching signal S8 becomes L level and the switching signal S9 becomes H level, the upper fixed voltage Vα is applied to the non-inverting input terminal of the error amplifier 13. Thereby, the error signal Sc is fixed to the H level (maximum value) regardless of the value of the detection voltage Vd. Therefore, the duty of the duty signal Sg output from the comparator 15 is fixed to the maximum value (for example, 95%) regardless of the error signal Sc. Then, a drive signal Sa having the same logic as the duty signal Sg is output from the NAND circuit 11. As a result, the step-down transistor T1 is driven with an on-duty of 95% regardless of the voltage feedback control by the error amplifier 13. As described above, the voltage control circuit 32 fixes the output of the error amplifier 13 to the H level (maximum value) during a period in which the input voltage Vi is less than the first threshold Vth1 and greater than or equal to the second threshold Vth2. Realizes step-down mode.

  Further, during a period in which the input voltage Vi is less than the second threshold value Vth2 and equal to or greater than the third threshold value Vth3, the switching signal S1 becomes L level and the switching signals S2 and S3 become H level. Therefore, the step-down transistor T1 is always turned on by the same operation as in the first embodiment. Since the switching signal S8 becomes H level and the switching signal S9 becomes L level, the lower fixed voltage Vβ is applied to the non-inverting input terminal of the error amplifier 13. As a result, the error signal Sc is fixed at the L level (minimum value) regardless of the detection voltage Vd. Therefore, the duty of the duty signal Sg output from the comparator 15 is fixed to the minimum value (for example, 5%) regardless of the error signal Sc.

  Then, the drive signal Sb having the logic opposite to that of the duty signal Sg is output from the selector circuit 17 by the same operation as in the first embodiment. As a result, the boosting transistor T2 is driven with an on-duty of 5% regardless of the voltage feedback control by the error amplifier 13. As described above, the voltage control circuit 32 fixes the output of the error amplifier 13 to the L level (minimum value) during a period in which the input voltage Vi is less than the second threshold value Vth2 and greater than or equal to the third threshold value Vth3. Realize boost mode.

  Further, the switching signals S1 to S3 are all at the H level during the period when the input voltage Vi is less than the third threshold value Vth3. Therefore, the step-down transistor T1 is always turned on by the same operation as in the first embodiment. Since both of the switching signals S8 and S9 are at the L level, the reference voltage Vr2 for instructing the target value of the output voltage Vo is supplied to the non-inverting input terminal of the error amplifier 13. As a result, the duty of the duty signal Sg output from the comparator 15 changes so that the output voltage Vo matches the target value.

  Then, the drive signal Sb having the same logic as the duty signal Sg is output from the selector circuit 17 by the same operation as that of the first embodiment. As a result, the drive of the boosting transistor T2 is duty-controlled by the error amplifier 13. Thus, during the period when the input voltage Vi is less than the third threshold value Vth3, the voltage control circuit 32 operates in the boost mode.

  The voltage control circuit 32 configured as described above can perform the same operation as the voltage control circuit 4 of the first embodiment. That is, the voltage control circuit 32 operates in the fixed duty step-down mode in the first half of the boost transition period (time t1 to t2 in FIG. 3), and in the fixed duty boost mode in the second half (time t2 to t3 in FIG. 3). Operate. The voltage control circuit 32 operates in the fixed duty step-up mode in the first half of the step-down transition period (time t4 to t5 in FIG. 3), and in the fixed duty step-down mode in the second half (time t5 to t6 in FIG. 3). Operate. Therefore, the power supply circuit 31 of the present embodiment can obtain the same operations and effects as those of the power supply circuit 1 of the first embodiment.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG.
A power supply circuit 41 (corresponding to a switching power supply circuit) shown in FIG. 7 differs from the power supply circuit 1 of the first embodiment shown in FIG. The signal generation circuit). The voltage control circuit 42 performs the same operation as that of the voltage control circuit 4, but the specific configuration is different.

  That is, the voltage control circuit 42 of the present embodiment is different from the voltage control circuit 4 in that the AND circuit 8, the threshold selection circuit 14, and the inverter circuit 18 are omitted, the AND circuits 33 and 34, the signal selection circuit 43, The difference is that a first fixed pulse signal generation circuit 44 and a second fixed pulse signal generation circuit 45 are provided. In this case, the error signal Sc output from the error amplifier 13 is directly supplied to the non-inverting input terminal of the comparator 15. The switching signals S8 and S9 output from the AND circuits 33 and 34 are given to the signal selection circuit 43.

  The signal selection circuit 43 is supplied with the duty signal Sg, the first fixed pulse signal Sp1, and the second fixed pulse signal Sp2 output from the comparator 15. The first fixed pulse signal Sp1 is generated by the first fixed pulse signal generation circuit 44. The pulse width (first pulse width) of the first fixed pulse signal Sp1 is set similarly to the first fixed pulse signal of the first embodiment. That is, the first fixed pulse signal Sp1 is a signal fixed at an on-duty of 5%.

  The second fixed pulse signal Sp2 is generated by the second fixed pulse signal generation circuit 45. The pulse width (second pulse width) of the second fixed pulse signal Sp2 is set in the same manner as the second fixed pulse signal of the first embodiment. That is, the second fixed pulse signal Sp2 is a signal fixed at an on-duty of 95%.

  The signal selection circuit 43 selects and outputs one of the duty signal Sg, the first fixed pulse signal Sp1, and the second fixed pulse signal Sp2. The output signal of the signal selection circuit 43 is given to the non-inverting input terminal of the AND circuit 9, the inverting input terminal of the NAND circuit 11, and the input terminal (0) of the selector circuit 17. The signal selection circuit 43 selects each signal based on the levels of the switching signals S8 and S9.

  That is, the signal selection circuit 43 outputs the duty signal Sg to the subsequent stage when both the switching signals S8 and S9 are at the L level. In addition, when the switching signal S8 is at the L level and the switching signal S9 is at the H level, the signal selection circuit 43 outputs the second fixed pulse signal Sp2 to the subsequent stage. Further, the signal selection circuit 43 outputs the first fixed pulse signal Sp1 to the subsequent stage when the switching signal S8 is at the H level and the switching signal S9 is at the L level.

  The voltage control circuit 42 configured as described above can perform the same operation as that of the voltage control circuit 4 of the first embodiment. That is, the voltage control circuit 42 operates in the fixed duty step-down mode in the first half of the boost transition period (time t1 to t2 in FIG. 3), and in the fixed duty boost mode in the second half (time t2 to t3 in FIG. 3). Operate. Further, the voltage control circuit 42 operates in the fixed duty step-up mode in the first half of the step-down transition period (time t4 to t5 in FIG. 3), and in the fixed duty step-down mode in the second half (time t5 to t6 in FIG. 3). Operate. Therefore, the power circuit 41 of this embodiment can obtain the same operations and effects as those of the power circuit 1 of the first embodiment.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The voltage control circuits 4, 22, 32, 42 may be configured to have one of a fixed duty boost mode and a fixed duty step-down mode. When the fixed duty boost mode is provided, the operation in the fixed duty boost mode may be included in the boost transition period. When the fixed duty step-down mode is provided, the operation in the fixed duty step-down mode may be included in the step-down transition period. Even with such a configuration, it is possible to obtain an effect that the fluctuation of the output voltage Vo in at least one of the step-up transition period and the step-down transition period can be suppressed.

  In each of the above embodiments, the detection voltage Vd is applied to the inverting input terminal of the error amplifier 13 and the reference voltage Vr2 is applied to the non-inverting input terminal. However, the voltages applied to the input terminals of the error amplifier 13 are switched. May be. However, in that case, it is necessary to add a configuration for achieving logic consistency, such as an inverter circuit for inverting the output signal of the error amplifier 13 or the output signal of the comparator 15. In addition, when the above change is made to the voltage control circuit 32 of the third embodiment, it is necessary to switch the selection of the upper fixed voltage Vα and the lower fixed voltage Vβ by the reference voltage selection circuit 35.

When operating in the fixed duty step-up mode, the step-down transistor T1 is fixed at full-on, but the present invention is not limited to this, and may be PWM-controlled, for example. Further, when operating in the fixed duty step-down mode, the boosting transistor T2 is fixed to be off, but the present invention is not limited thereto, and may be PWM-controlled, for example.
The fixed duty in the fixed duty step-up mode and the fixed duty step-down mode is not limited to one type of value, and a plurality of values of fixed duty may be changed stepwise.

  In the drawings, 1, 21, 31, and 41 are power supply circuits (switching power supply circuits), 2 is a step-down driver (step-down drive circuit), 3 is a step-up driver (step-up drive circuit), 4, 22, 32, and 42. Is a voltage control circuit (drive signal generation circuit), 12 is an output voltage detection circuit (voltage detection circuit), 13 is an error amplifier (error amplification circuit), 14 and 24 are threshold selection circuits (input signal switching circuit), and 15 is a comparator. (Comparison circuit), 35 is a reference voltage selection circuit (output fixing circuit), 44 is a first fixed pulse signal generation circuit, 45 is a second fixed pulse signal generation circuit, P1 is a power input terminal, P2 is a power output terminal, T1 Denotes a transistor (step-down switching element), and T2 denotes a transistor (step-up switching element).

Claims (8)

A step-up / step-down type that boosts an input voltage applied to the power input terminal (P1) and outputs the boosted voltage from the power output terminal (P2), and performs a step-down operation that steps down the input voltage and outputs the boosted voltage from the power output terminal. A switching power supply circuit (1, 21, 31, 41),
A boosting switching element (T2) that performs a switching operation during the boosting operation;
A step-down switching element (T1) that performs a switching operation during the step-down operation;
A voltage detection circuit (12) for outputting a detection voltage corresponding to an output voltage at the power output terminal;
A drive signal generation circuit (4, 22, 32, 42) for generating a drive signal for driving the step-up switching element and the step-down switching element;
A boost drive circuit (3) for driving the boost switching element based on the drive signal;
A step-down drive circuit (2) for driving the step-down switching element based on the drive signal;
With
The drive signal generation circuit includes:
A step-up mode for outputting a PWM signal having a duty corresponding to a reference voltage corresponding to a target value of the detection voltage and the output voltage as the drive signal to the step-up drive circuit;
A step-down mode for outputting a PWM signal having a duty according to the detection voltage and the reference voltage to the step-down drive circuit as the drive signal;
In addition,
A fixed duty step-up mode for outputting a first fixed pulse signal having a first pulse width smaller than the maximum value of the pulse width representing the ON period of the PWM signal in the step-down mode to the step-up drive circuit as the drive signal;
A fixed duty step-down mode for outputting a second fixed pulse signal having a second pulse width larger than a minimum value of a pulse width representing an ON period of the PWM signal in the step-up mode to the step-down drive circuit as the drive signal;
One or both of
When the fixed duty boost mode is provided, the operation in the fixed duty boost mode is included in the boost transition period in which the operation in the step-down mode shifts to the operation in the boost mode.
In the case of providing the fixed duty step-down mode, the switching power supply is characterized in that the operation in the fixed duty step-down mode is included in the step-down transition period in which the operation in the step-up mode is shifted to the operation in the step-down mode. circuit.   The switching power supply circuit according to claim 1, wherein the drive signal generation circuit (4, 22, 32, 42) includes both the fixed duty step-up mode and the fixed duty step-down mode. The drive signal generation circuit (4, 32, 42)
The switching power supply circuit according to claim 2, wherein the operation in the fixed duty step-down mode is performed prior to the operation in the fixed duty step-up mode in the step-up transition period. The drive signal generation circuit (4, 32, 42)
4. The switching power supply circuit according to claim 2, wherein in the step-down transition period, the operation in the fixed duty step-up mode is performed prior to the operation in the fixed duty step-down mode. The drive signal generation circuit (4, 22, 32, 42)
An error amplification circuit (13) for outputting an error signal obtained by amplifying an error of the detection voltage with respect to the reference voltage;
A comparison circuit (15) for inputting the error signal and the carrier signal and outputting a signal corresponding to the comparison result of each input signal;
With
5. The switching power supply circuit according to claim 2, wherein in the step-up mode and the step-down mode, an output signal of the comparison circuit is output as the drive signal. 6. The drive signal generation circuit (4, 22) inputs a first threshold signal to the comparison circuit instead of the error signal in the fixed duty step-up mode, and replaces the error signal in the fixed duty step-down mode. An input signal switching circuit (14, 24) for inputting two threshold signals to the comparison circuit;
6. The switching power supply circuit according to claim 5, wherein the drive signal generation circuit outputs an output signal of the comparison circuit as the drive signal in the fixed duty step-up mode and the fixed duty step-down mode. The drive signal generation circuit (32) fixes the output of the error amplifier circuit to one of a maximum value and a minimum value in the fixed duty step-up mode, and outputs the error amplifier circuit in the fixed duty step-down mode. An output fixing circuit (35) for fixing either the maximum value or the minimum value to the other;
6. The switching power supply circuit according to claim 5, wherein the drive signal generation circuit outputs an output signal of the comparison circuit as the drive signal in the fixed duty step-up mode and the fixed duty step-down mode. The drive signal generation circuit (42) includes a first fixed pulse signal generation circuit (44) that generates the first fixed pulse signal and a second fixed pulse signal generation circuit (45) that generates the second fixed pulse signal. And comprising
The drive signal generation circuit outputs the first fixed pulse signal as the drive signal to the boost drive circuit in the fixed duty boost mode, and drives the second fixed pulse signal in the fixed duty step-down mode. 6. The switching power supply circuit according to claim 5, wherein the switching power supply circuit outputs the signal to the step-down driving circuit as a signal.

Images