JP2014204286A - Multistage active filter and reception device - Google Patents

Abstract

A high-quality semiconductor device suitable for a receiving device or the like can be provided. A multi-stage active filter includes a front-side biquad filter LPF1 and a rear-stage LPF2. The resistance values and the capacitance values of the resistors included in the biquad filters LPF1 and LPF2 are scaled so that the transfer function from input to output remains constant and the gain at the internal contact becomes smaller than before scaling. The biquad filter LPF1 is scaled so that the resistance value of the first resistor R1 constituting the input unit is equal to or lower than that before the scaling, and the biquad filter LPF2 includes capacitors C1 and C2 included in the biquad filter LPF2. Scaled so that area is less than or equal to before scaling. [Selection] Figure 2

Description

  The present invention relates to a multistage active filter and a receiving apparatus.

  A method of configuring a radio signal processing circuit used for a mobile phone or the like with individual components is generally called a superheterodyne system.

  On the other hand, Non-Patent Document 1 describes the basic principle of a method called a zero IF method or a low IF method as a wireless signal processing method that does not require an external SAW filter or dielectric filter.

  Patent Document 1 describes a technique related to a zero-IF or low-IF receiver.

JP 2011-142373 A

By Aarno Parssinen, Direct conversion receivers in wide-band systems, Kluwer Academic Publishers

  The inventors have found various problems in developing a semiconductor device used for a receiving device or the like. Each embodiment disclosed in the present application provides a semiconductor device suitable for a receiving device or the like, for example.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a channel filter including a two-stage biquad filter.

  According to one embodiment, for example, a high-quality semiconductor device that is suitable for a receiving device or the like can be provided.

It is a block diagram which shows a direct conversion and a WCDMA (trademark) receiver. It is a circuit diagram which shows the bicut filter which comprises the multistage active filter concerning embodiment of this invention. FIG. 3 is a graph showing frequency characteristics of G _BQ = 1, Q = 2, and ω ₀ = 1 in the biquad filter shown in FIG. FIG. 3 is a graph showing the frequency characteristics of G _BQ = 1, Q = 0.5, and ω ₀ = 1 in the biquad filter shown in FIG. It is a figure which shows the scaling condition which _GBD , omega ₀ , and Q do not change before and after scaling. FIG. 4 is a graph showing the results of FIG. 3 together with the transfer functions from the scaled input terminals INT and INB to the internal node terminals XT and XB. FIG. 5 is a graph showing the results of FIG. 4 together with the transfer functions from the scaled input terminals INT and INB to the internal node terminals XT and XB. It is a figure which shows the element constant at the time of performing a simulation with a biquad filter. FIG. 9 is a graph showing the result of simulating the input equivalent noise level by configuring the biquad filter shown in FIG. 2 using the element constants shown in FIG. 8. It is a figure which shows the two-stage active filter concerning Embodiment 1 of this invention. It is a figure which shows the multistage active filter concerning the modification 1 of embodiment of this invention. It is a circuit diagram which shows an example of the 1st-order low pass filter applied when comprising Embodiment 1 of this invention by an odd number stage. It is a figure which shows the multistage active filter concerning the modification 2 of embodiment of this invention. It is a circuit diagram which shows the receiver concerning Embodiment 2 of this invention. It is a circuit diagram which shows the receiver concerning Embodiment 3 of this invention. 10 is a circuit diagram showing a capacitor bank described in Patent Document 1. FIG.

  Hereinafter, specific embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiment. In addition, for clarity of explanation, the following description and drawings are simplified as appropriate.

  The radio signal processing circuit is a circuit that converts a high-frequency signal received from an antenna into a signal of a lower frequency band with high quality (low noise, suppression of a signal other than the desired signal band, etc.). The multistage active filter, the radio processing circuit, and the receiving apparatus according to the present embodiment can be used in, for example, a mobile phone. In this case, the radio signal processing circuit, the amplifier that amplifies the signal, the signal A mixer that converts the frequency, a filter that passes only a desired band of the signal, and the like are incorporated in one semiconductor chip, so that the size and cost can be reduced.

  By the way, even when these functional blocks are incorporated in one semiconductor chip, a filter circuit such as a SAW (Surface Acoustic Wave) filter or a dielectric filter that suppresses signals in a band other than the desired band is used. It cannot be built in a semiconductor chip (superheterodyne method).

  Therefore, when the radio signal processing circuit is configured by a semiconductor chip by the superheterodyne method, it is necessary to externally attach a SAW filter, a dielectric filter or the like outside the semiconductor chip. For this reason, the number of parts, mounting area, etc. will increase.

  Therefore, the inventors of the present application have first used the advantage of the semiconductor circuit that the absolute values of the component constants between the semiconductor chips vary, but the relative values of the component constants in one semiconductor chip coincide with each other with high accuracy. Have proposed a wireless signal processing circuit system that does not require a SAW filter or a dielectric filter (see Patent Document 1). This is called a zero IF system or a low IF system. Neither of them requires an external SAW filter or dielectric filter, and can suppress signals existing in bands other than the desired band with a filter that can be incorporated in a semiconductor. Note that it may be necessary to attach some filters externally depending on the wireless system or system requirements.

  The basic principle such as the zero IF method or the low IF method is described in Non-Patent Document 1, for example. The zero IF method and the low IF method have a common operational characteristic in that one signal is decomposed and processed into two components, an I component and a Q component. By inputting two local oscillation signals having phases different by 90 degrees at the same frequency and a signal to be decomposed into an I component and a Q component into the quadrature mixer, the signal can be decomposed into an I component and a Q component. .

  A variable gain amplifying circuit and a channel filter that allows only a desired channel band to pass are provided after the mixer. A channel filter can be realized by a filter circuit (hereinafter referred to as an active filter) that combines resistance and capacitance with a transistor circuit such as an operational amplifier. It is possible to suppress a signal existing in a channel other than a desired channel such as a direct channel.

  However, in the channel filter described in Patent Document 1, when the gain of the circuit used in the preceding stage is high, the gain at the internal node between the two-stage integrators included in the biquad filter used is too large. In some cases, the signal becomes saturated and correct filtering results cannot be obtained.

  Further, the cut-off frequency of such a gain signal has a certain value depending on the received modulation signal. For example, GSM (registered trademark) (Global System for Mobile Communications) uses a fixed value such as 140 kHz and WCDMA (Wideband Code Division Multiple Access) uses 2 MHz or the like, but LTE (Long Term Evolution) uses 700 kHz, for example. Six types of 1.5 MHz, 2.5 MHz, 5 MHz, 10 MHz, 7.5 MHz, and 10 MHz are used. That is, it is necessary to vary the cut-off frequency over a wide range.

  Here, first, a direct conversion / WCDMA / receiver as an example of a receiving apparatus according to the present embodiment will be described. FIG. 1 is a block diagram showing a direct conversion WCDMA receiver. As shown in FIG. 1, a direct conversion WCDMA receiver (hereinafter referred to as a receiving device) 101 includes an antenna 101, a band pass filter (BPF) 102, a low noise amplifier (LNA) 103, an I signal mixer 104, A 1-channel selection filter 105, a first amplifier 106, a Q signal mixer 107, a second channel selection filter 108, a second amplifier 109, a 90-degree phase shifter 110, and an RF voltage controlled oscillator (VCO) 111 are provided. In the subsequent stage, a digital signal processing unit 112 including an analog-digital converter, a digital filter, and the like is provided.

  The receiving apparatus 1 includes a low noise amplifier 103, an I signal mixer 104, a first channel selection filter 105, a first amplifier 106, a Q signal mixer 107, a second channel selection filter 108, a second amplifier 109, and a 90 degree phase shifter. 110 and the RF voltage controlled oscillator 111 are integrated on a semiconductor chip of a semiconductor integrated circuit mounted on a mobile phone terminal.

  An RF voltage controlled oscillator (VCO) 111 and a 90 degree phase shifter 110 supply an I local signal and a Q local signal having a phase difference of 90 degrees to the I signal mixer 104 and the Q signal mixer 107, respectively.

  An RF reception signal by the WCDMA system received by the antenna 101 is supplied to the input terminal of the low noise amplifier 103 via the band pass filter 102, and the RF reception amplification signal of the low noise amplifier 103 is an I signal that constitutes an orthogonal down conversion mixer. The signals are supplied to the mixer 104 and the Q signal mixer 107, respectively. The I baseband signal generated from the I signal mixer 104 is supplied to the first channel selection filter 105 and the first amplifier 106, while the Q baseband signal generated from the Q signal mixer 107 is supplied to the second channel selection filter 108. Supplied to the second amplifier 109.

  The receiving device 101 is supplied with a 3-bit baseband signal band selection signal from a baseband processor (not shown), and in response to this, the cutoff frequencies of the first and second channel selection filters 105 and 108 are 700 kHz, 1.5 MHz, 2.5 MHz, 5.0 MHz, 7.5 MHz, or 10 MHz.

  As a channel filter (multistage active filter) capable of supporting such a wide range of cut-off frequencies, the inventor of the present application performs scaling on a two-stage biquad filter so that the resistance value of the resistor and the capacitance value of the capacitor. Was set to an appropriate value, and the output gain with respect to the input remained the same, the gain of the internal node with respect to the input was lowered, and at the same time, a channel filter that was excellent in noise characteristics and could cope with the circuit area was successfully developed.

FIG. 2 is a circuit diagram showing a bicut filter used in the multistage active filter according to the embodiment of the present invention.
In FIG.
INT and INB are input terminals,
OUTT and OUTB are output terminals,
XT and XB are internal node terminals,
OPA1 to OPA2 are operational amplifiers,
R1 to R4 are resistors,
C1 to C2 are capacities.
Also,
V _in : voltage obtained by subtracting the potential of the input terminal INB from the potential of the input terminal INT V _out : voltage obtained by subtracting the potential of the output terminal OUTB from the potential of the output terminal OUTT V _x : the potential of the internal node terminal XT to the internal node terminal XB The voltage obtained by subtracting the potential is shown.

The transfer function from the input terminals INT and INB to the output terminals OUTT and OUTB of the biquad filter shown in FIG. 2 is the following s function (s is a Laplace variable). Here, omega ₀ is the center angular frequency, Q is the Q value of the passband or stopband (quality factor), G _BQ represents the gain of the biquad filter.

Here, G _BQ , Q, and ω ₀ in Expression 1 are expressed as follows only by resistance and capacitance. _C 1 a capacitance value of the capacitor C1, C2, _{C 2,} the resistance value of the resistor R1~R4 and _R 1 to R _4.

There is a product of capacitance values C ₁ and C ₂ in the root of the numerator of ω ₀ in Equation 4. Since C ₁ and C ₂ are capacitance values, C ₁ > 0 and C ₂ > 0. Further, since the product C ₁ · C ₂ of the capacitance value for determining a certain ω ₀ is constant, C ₁ · C ₂ = A (constant), and the capacitance values C ₁ and C ₂ that minimize the circuit area are obtained. Find the condition. When A is used as the sum of C ₁ and C ₂ , the following function f (C ₁ ) of the capacitance value C ₁ is obtained.

ｆ（Ｃ_１）の導関数は以下となるので、

The derivative of f (C ₁ ) is

となるときの容量値Ｃ_１がｆ（Ｃ_１）の最小値となる条件である。したがって、

In which the capacitance value C ₁ becomes the minimum value of f (C ₁ ). Therefore,

このとき、

At this time,

であるから、ｆ（Ｃ_１）の最小値、すなわち回路面積を最小にする容量値の条件はＣ_１＝Ｃ_２となる。

Therefore, the condition of the minimum value of f (C ₁ ), that is, the capacitance value that minimizes the circuit area is C ₁ = C ₂ .

  Next, the transfer function from the input terminals INT and INB to the internal node terminals XT and XB of the biquad filter shown in FIG. 2 will be described. The transfer function from the input terminals INT and INB to the internal node terminals XT and XB is the following s function.

である。また、その直流利得は以下のようになる。

It is. The DC gain is as follows.

Therefore, it can be seen that has a gain G _BQ different gains biquad filter shown in Equation 2. Next, the frequency characteristics of gains other than the direct current gain of Equation 1 and Equation 8 are compared.

In the case of R ₁ = R ₂ = R ₃ = C ₁ = C ₂ = 1 and R ₄ = 2, G _BQ = 1 from Equation 2, Q = 2 from Equation 3, and ω ₀ = 1 from Equation 4. The frequency characteristics at this time are shown in FIG. On the other hand, when R ₁ = R ₂ = R ₃ = C ₁ = C ₂ = 1 and R ₄ = 0.5, G _BQ = 1 from Equation 2, Q = 0.5 from Equation 3, and ω ₀ from Equation 4. = 1. The frequency characteristics at this time are shown in FIG.

3 and 4, the solid lines are transfer functions from the input terminals INT and INB to the output terminals OUTT and OUTB (Equation 1), and the dotted lines are transfer functions from the input terminals INT and INB to the internal node terminals XT and XB (Equation 2). ). 3 and 4 that the signal level at the internal node terminals XT and XB increases as Q decreases. From Equation 8 and Equation 9, the capacitance value C ₁ or the resistance value R ₁ or resistance value R ₄ L times (L is a positive real number) or, when the resistance value R ₃ scaling or to the 1 / L times The gain from the input terminals INT and INB to the internal node terminals XT and XB decreases. Incidentally, etc. multiply both 1 / √L the capacitance value C ₁ and the capacitance value R _1, the other scaling means exist indefinitely.

At this time, since the transfer functions of the biquad filter shown in Equation 1 need to be the same, G _BD , ω ₀ , and Q need to be unchanged before and after scaling. FIG. 5 shows a scaling condition that satisfies this. 3 and 4 are graphs in which the transfer functions from the input terminals INT and INB to the internal node terminals XT and XB after scaling with L = 2 are combined with a one-dot chain line, respectively. It shows in FIG.6 and FIG.7. 5A and 5B, the signal levels at the internal node terminals XT and XB can be lowered as indicated by the one-dot chain line in FIGS.

In FIG. 5, the scaling rule [S−1] has the capacitance value C ₁ = C ₂ , and therefore satisfies the minimum area condition as described in Expressions 5 to 7. However, the noise characteristics are deteriorated when the value of the resistance value R ₁ which constitutes the input of the biquad filter shown in FIG. 1 is increased. In the scaling rule [S-2], since the resistance value R ₁ is unchanged before and after scaling, the noise characteristics are not deteriorated, but the capacitance value C ₁ ≈C ₂ , so the area minimum condition is not satisfied. Like the scaling rule [S-2], the scaling rule [S-3] does not degrade the noise characteristics before and after scaling, but does not satisfy the area minimum condition because the capacitance value C ₁ ≈C ₂ . Further, as described above, a wide range of use capacitor bank in order to vary the cutoff frequency (see Non-Patent Document 1), it is necessary to further reduce the minimum capacitance value of the capacitance value C _2, fulfilling is not.

  A specific example will be described. FIG. 9 shows the result of simulating the input equivalent noise level by configuring the biquad filter shown in FIG. 2 using the element constants shown in FIG. The result before scaling (Original) is shown by a solid line, the result of applying the scaling rule [S-1] is shown by a dotted line, and the result of applying the scaling rule [S-2] is shown by an alternate long and short dash line. FIG. 9 also shows that the noise characteristics can be improved by applying the scaling rule [S-2].

  Based on these simulations, the inventor of the present application has found an active filter that can vary a cut-off frequency (cutoff frequency) in a wide range, which is suitable for a zero-IF or low-IF radio signal processing circuit. That is, a scaling rule [S-2] that can lower the gain at the internal contact without degrading noise characteristics is placed in front of the active filter, and the scaling rule [S If the filter of -1] is arranged in the subsequent stage, a multistage active filter with a smaller area and low noise can be configured. Hereinafter, a multistage active filter according to an embodiment of the present invention and a receiving apparatus including the multistage active filter as a channel filter will be described.

<Embodiment 1>
FIG. 10 is a diagram illustrating the two-stage active filter according to the first embodiment of the present invention. Such a two-stage active filter can be used, for example, as a channel selection filter for direct conversion, WCDMA, or a receiver to support the LTE system. In FIG.
INT and INB are input terminals,
OUTT, OUTB: output terminals,
V _in : voltage obtained by subtracting the potential of the input terminal INT from the potential of the input terminal INT,
V _out : voltage obtained by subtracting the potential of the output terminal OUTT from the potential of the output terminal OUTT,
LPF1: biquad filter applying the scaling rule [S-2] of FIG.
LPF2: A biquad filter to which the scaling rule [S-1] of FIG. 5 is applied.

  As shown in FIG. 10, the multistage active filter 10 includes a first biquad filter LPF1 provided at the front stage and a second biquad filter LPF2 provided at the rear stage of the multistage active filter 10. The first biquad filter LPF1 in the first stage is composed of a complete integrator, and the second biquad filter LPF2 in the second stage is from an incomplete integrator in which the charge of the feedback capacitor C is discharged by the variable feedback resistor R3. It is configured.

  That is, each of the biquad filter LPF1 and the biquad filter LPF2 of the multistage active filter 10 includes a first integrator and a second integrator connected thereto, and a first resistor that constitutes an input unit of the biquad filter LPF1. And the first and second integrators are fed back to the input through a complete integrator whose output is fed back to the input through a feedback capacitor or a feedback capacitor and a feedback resistor in parallel with the output, respectively. It can be either an incomplete integrator.

  The resistance values of the resistors and the capacitance values of the capacitors included in the first biquad filter LPF1 and the second biquad filter LPF2 are such that the transfer function from the input to the output remains constant, and the gain at the internal node is higher than before the scaling. Is also scaled down. Furthermore, the scaling rule [S-2] shown in FIG. 5 is applied so that the resistance value of the first resistor constituting the input unit of the first biquad filter LPF1 is equal to or lower than that before scaling. That is, the biquad filter LPF1 is scaled so that the feedback capacitors of the first integrator and the feedback capacitors of the second integrator have different capacitance values. Further, the second biquad filter LPF2 is scaled by applying the scaling rule [S-1] shown in FIG. 5 so that the area of the capacitance contained therein is equal to or less than that before scaling. In this scaling law, the biquad filter LPF2 is scaled so that the feedback capacity of the first integrator is equal to the feedback capacity of the second integrator.

  The biquad filter LPF1 and the biquad filter LPF2 of the multistage active filter 10 according to the present embodiment will be described in more detail. As shown in FIG. 2, each of the biquad filter LPF1 and the biquad filter LPF2 in this embodiment includes two resistors R1 that constitute an input unit, an operational amplifier OPA1 that constitutes a first integrator, and two feedback capacitors. C1, two resistors R3 constituting the input part of the second biquad filter LPF2, an operational amplifier OPA2 constituting the second integrator, two feedback resistors R4, two feedback capacitors C2, and an output OUTT of the multistage active filter 10 , OUTB has two feedback resistors R4 connected to the input side.

  The inverting input terminal − and the non-inverting input terminal + of the first stage operational amplifier OPA1 are connected to the non-inverting input terminal INT and the inverting input terminal INB via resistors R1 and R1, respectively. A feedback capacitor C is connected between the inverting input terminal − and the non-inverting output terminal + of the first stage operational amplifier OPA1, and between the non-inverting input terminal + and the inverting output terminal − of the first stage operational amplifier OPA1. Is connected to a feedback capacitor C.

  The non-inverting output terminal + and the inverting output terminal − of the first stage operational amplifier OPA1 are connected to the inverting input terminal − and the non-inverting input terminal + of the second stage operational amplifier OPA1 via resistors R3 and R3, respectively. ing. A feedback capacitor C2 and a variable feedback resistor R4 are connected in parallel between the inverting input terminal − and the non-inverting output terminal + of the second stage operational amplifier OPA2, and the non-inverting input terminal of the second stage operational amplifier OPA2 is connected. A feedback capacitor C2 and a variable feedback resistor R4 are connected in parallel between + and the inverted output terminal −.

  A resistor R2 is connected between the inverting output terminal − of the second stage operational amplifier OPA2 and the inverting input terminal − of the first stage operational amplifier OPA1, and the non-inverting output terminal + of the second stage operational amplifier OPA2 and A resistor R2 is connected to the non-inverting input terminal + of the first stage operational amplifier OPA1. The non-inverting output terminal + and the inverting output terminal − of the second stage operational amplifier OPA2 are set to a non-inverting output terminal OUTT and an inverting output terminal OUTB.

As described above, since the biquad filter to which the scaling rule [S-2] is applied has good noise characteristics, it is disposed in the previous stage, and the biquad filter to which the scaling law [S-1] is applied has a small area, and thus the latter stage. To place. By making G _BQ > 1 and giving a gain to the second biquad filter LPF2 at the subsequent stage, the noise characteristic contribution ratio due to the first biquad filter LPF1 applying the scaling law [S-2] may be reduced. it can. Furthermore, by disposing a digital filter (see FIG. 1) disposed in the subsequent stage, it is possible to suppress the residual amount of signals existing in a band other than the desired signal.

  FIG. 10 is an even-order filter because it is fourth-order, but when an odd-order filter is configured, a first-order LPF may be added. FIG. 11 is a diagram showing a multistage active filter 20 according to the first modification of the present embodiment, and shows a multistage active filter including a fifth-order filter.

In the multistage active filter 20 shown in FIG.
INT, INB: input terminal,
OUTT, OUTB: output terminals,
V _in : voltage obtained by subtracting the potential of the input terminal INT from the potential of the input terminal INT,
V _out : voltage obtained by subtracting the potential of the output terminal OUTT from the potential of the output terminal OUTT,
LPF0: first-order low-pass filter,
Indicates.

The primary low-pass filter LPF0 can be configured as shown in FIG. 12, for example. FIG. 12 is a circuit diagram showing a first-order low-pass filter. In FIG.
INT, INB: input terminal,
OUT0T, OUT0B: output terminals,
V _in : voltage obtained by subtracting the potential of the input terminal INT from the potential of the input terminal INT,
V _out : voltage obtained by subtracting the potential of the output terminal OUT0T from the potential of the output terminal OUT0T,
OPA01: operational amplifier,
R01, R02: resistance,
C01: Indicates capacity. The transfer function from the input terminals INT and INB to the output terminals OUTT and OUTB of the low-pass filter LPF0 in FIG. 12 is the following s function.

  As shown in FIG. 10, the position of the primary low-pass filter LPF0 is between the biquad filter LPF1 and the biquad filter LPF2, or after the biquad filter LPF2, other than the pre-stage of the biquad filter LPF1 at the front stage. Also good.

It is also possible to configure a multistage filter. FIG. 13 is a block diagram showing a multistage active filter 30 according to the second modification of the present embodiment. The multistage active filter 30 according to this modification includes a plurality of biquad filters LPF1 and biquad filters LPF2. In FIG.
INT, INB: input terminal,
OUTT, OUTB: output terminals,
V _in : voltage obtained by subtracting the potential of the input terminal INT from the potential of the input terminal INT,
V _out : voltage obtained by subtracting the potential of the output terminal OUTT from the potential of the output terminal OUTT,
Indicates. The primary low-pass filter LPF0 is, for example, the low-pass filter shown in FIG.

  The multistage active filter 30 of the present modification includes an N-stage (N is an integer of 1 or more) biquad filter LPF1 and an M-stage (M is an integer of 1 or more) biquad filter LPF2. As described above, the biquad filter LPF1 is a biquad filter to which the scaling law [S-2] shown in FIG. 5 is applied, and the biquad filter LPF2 applies the scaling law [S-1] shown in FIG. This is a biquad filter. Also in this modification, when it is desired to configure an odd-order filter, a low-pass filter LPF0 shown in FIG. At this time, the low-pass filter LPF0 may be at the first stage or at an arbitrary position other than the first stage.

  Further, noise characteristics can be improved if at least one biquad filter LPF1 is arranged on the front stage side. For example, the biquad filter LPF1 is arranged in the first stage and the biquad filter LPF2 is arranged in the rear stage. A plurality of stages may be provided. That is, noise characteristics can be improved by disposing at least one biquad filter LPF1 at or near the first stage. Further, the biquad filter LPF2 disposed in the subsequent stage may be one stage or two stages or more. A filter different from the biquad filters LPF1 and LPF2, a one-stage low-pass filter LPF0, or the like may be arranged in the meantime or in the subsequent stage. In either case, it is possible to configure a multistage active filter that suppresses an increase in circuit scale without deteriorating noise characteristics.

<Embodiment 2>
Next, an example in which the multistage active filter 10 shown in FIG. 10 is applied to a receiving apparatus will be described. FIG. 14 is a circuit diagram showing a receiving apparatus according to the second embodiment of the present invention. As illustrated in FIG. 14, the receiving device 40 according to the second embodiment of the present invention includes a low noise amplifier circuit LNA1 that is an amplifier circuit to which a radio signal is input, a low noise amplifier circuit LNA1, and capacitors C1T and C1B. And a local amplifying circuit LoBuf1 that amplifies a local balanced signal for turning on and off the switches of the transistors M1 to M4 constituting the passive mixer M10. Furthermore, it has a biquad filter LPF10 which is a low-pass filter to which the output signal of the passive mixer M10 is input, and a multistage active filter 10 to which the output of the biquad filter LPF10 is input.

  The multistage active filter 10 can be configured similarly to the multistage active filter according to the first embodiment shown in FIG. That is, the multistage active filter 10 includes a biquad filter LPF1 and a biquad filter LPF2 provided at a subsequent stage of the biquad filter LPF1. The resistance values of the resistors and the capacitance values of the capacitors included in the biquad filter LPF1 and the biquad filter LPF2 are such that the transfer function from the input to the output remains constant and the gain at the internal node becomes smaller than before the scaling. The biquad filter LPF1 is scaled so that the resistance value of the first resistor constituting the input unit is equal to or lower than that before the scaling, and the biquad filter LPF2 has a capacitance included in the biquad filter LPF2. Scaled so that area is less than or equal to before scaling.

In FIG.
LNA1: Low noise amplifier circuit (hereinafter referred to as LNA),
INT, INB: wireless signal input terminal,
C1T, C1B: capacity,
LoBuf1: a local amplifier circuit,
LoT, LoB: local oscillation input terminal,
M1-M4: MOSFET,
CFBT, CFBB: capacity,
RFBB, RFBT: resistance,
OPA1: Fully differential amplifier circuit,
OUTT, OUTB: Indicates output terminals.

  In FIG. 14, a circuit portion composed of MOSFETs (hereinafter referred to as transistors) M1 to M4 is a passive mixer M10. In the passive mixer M10, the transistors M1 to M4 may be N-channel Mos transistors (NMOS) or P-channel Mos transistors (PMOS). Further, an NMOS and a PMOS may be connected in parallel and may function as a switch.

  In the receiving device 40, a radio signal input from an antenna or a cable (not shown) is converted into a balanced signal by an unbalanced balance conversion circuit, a SAW (Surface Acoustic Wave) filter (not shown), or the like, and a matching circuit (not shown). The signal is input from the wireless signal input terminals INT and INB to the low noise amplifier circuit LNA1. The low noise amplifier circuit LNA1 amplifies a radio signal in a desired band so as not to degrade the signal-to-noise ratio (hereinafter referred to as SNR) as much as possible.

  A local oscillation balanced signal from an oscillation circuit (not shown) is input from the local oscillation input terminals LoT and LoB to the local oscillation amplifier LoBuf1. The local oscillation circuit LoBuf1 amplifies the local oscillation balanced signal input to the local oscillation input terminals LoT and LoB to power sufficient to switch the transistors M1 to M4. Since the local oscillation signal output from the local oscillation circuit LoBuf1 is a balanced signal, if the transistors M1 and M3 are on, the transistors M2 and M4 are off, and if the transistors M2 and M4 are on, the transistors M1 and M3 are Turn off.

  The output signal of the low noise amplifier circuit LNA1 is input to the transistors M1 to M4 of the passive mixer M10 via the capacitors C1T and C1B. The reason why the output signal of the low noise amplifier circuit LNA1 is input to the transistors M1 to M4 which are the passive mixers M10 through the capacitors C1T and C1B is because 1 / f noise characteristics are taken into consideration. That is, by preventing the DC bias current from flowing through the transistors M1 to M4, the occurrence of 1 / f noise, which is a function of the DC bias current flowing through the transistors, can be suppressed. The transistors M1 to M4 are converted into a sum of two current components of a difference frequency component and a sum frequency component of the radio signal and the local oscillation signal. In the case of the zero IF method, the local frequency is set to the center frequency of the desired reception signal of the radio signal.

  The fully differential amplifier circuit OPA1, resistors RFBB and RFBT, capacitors CFBT and CFBB are low-pass filters LPF10, and the difference frequency component and sum frequency component of the radio signal and the local oscillation signal that are the output signals of the passive mixer M10. Only the difference frequency component between the radio signal and the local oscillation signal is converted into a voltage from the sum of the two current components, and output to the channel filter 50 including the biquad filter LPF1 and the biquad filter LPF2.

  The biquad filter LPF1 and the biquad filter LPF2 constitute a channel filter in combination with a fully-differential amplifier circuit OPA1 and a low-pass filter including resistors RFBB and RFBT and variable capacitors CFBT1 and CFBB1. A signal existing in a band other than the desired signal is suppressed and output from the output terminals OUTT and OUTB.

  In general, since it is important that the receiving apparatus has low noise characteristics, in the receiving apparatus 40 according to the present embodiment, the biquad filter LPF1 is reduced in noise by applying the scaling rule [S-2]. The receiving device 40 having a wide dynamic range can be configured.

  Further, the two stages of LPFT1 and LPFT2 shown in FIG. 13 may be multi-staged as shown in FIG. In this case, the output of any of the biquad filters LPF1 group to which the scaling rule [S-2] is applied may be output by bypassing the subsequent biquad filters LPF1 group and biquad filter LPF2. Furthermore, by arranging the low-pass filter LPF0, it is possible to configure an odd-stage channel filter.

<Embodiment 3>
FIG. 15 is a circuit diagram showing a receiving apparatus according to the third embodiment of the present invention. As illustrated in FIG. 15, the receiving device 60 according to the present embodiment bypasses the biquad filter LPF2 from the output of the biquad filter LPF1 in the channel filter 50 in the receiving device 40 according to the second embodiment. The switch SW is added so that it can be output.

  As described above, the cut-off frequency has a fixed value depending on the received modulation signal, for example, a fixed value such as 140 kHz for GSM and 2 MHz for WCDMA, for example. On the other hand, in LTE, for example, there are many types and types of 700 kHz, 1.5 MHz, 2.5 MHz, 5 MHz, 10 MHz, 7.5 MHz, and 10 MHz, and it is necessary to vary a wide range of cutoff frequencies.

  For example, when receiving a modulated signal having a low cut-off frequency such as GSM, the receiving device 60 shown in FIG. 15 bypasses the biquad filter LPF2 by the switch SW and outputs the bypassed signal. If the cut-off frequency is varied in the capacitor bank as described in Patent Document 1 described above, the low cut-off frequency is set with a large capacity, and therefore the biquad filter LPF1 uses the scaling law [S- Applying 2] does not increase the area.

  FIG. 16 is a circuit diagram showing a capacitor bank described in Patent Document 1. In FIG. The capacitor bank C shown in FIG. 16 has a plurality of capacitors CD0, CD1, CD2, CD3, CD4, and CDcom connected in parallel between the first terminal 300 and the second terminal 310.

  The capacities CD0, CD1, CD2, CD3, CD4, and CDcom are respectively 0.02 Cb, 0.04 Cb, 0, .4 corresponding to weights of 1 times, 2 times, 4 times, 8 times, 16 times, and 34 times, respectively. The capacitance values are set to 08 Cb, 0.16 Cb, 0.32 Cb, and 0.68 Cb.

  A switch SW0 is connected to the capacitor CD0, a switch SW is connected to the capacitor CD1, a switch SW2 is connected to the capacitor CD2, a switch SW3 is connected to the capacitor CD3, and a switch SW4 is connected to the capacitor CD4. The switches SW 0, SW 1, SW 2, SW 3, SW 4 are each turned on / off by a 1-bit signal from the least significant 1 bit to the most significant 5 bit of the 5-bit control signal 320.

  For example, the digital capacitance value when the switches SW0 to SW4 of the capacitor bank C are all off is the minimum value 0.68Cb, and the digital capacitance value when the switches SW0 to SW4 are all on is the maximum value 1.30Cb. Become. Further, when only the switch SW4 is on, the digital capacitance value is approximately the intermediate value 1.00Cb.

  In this case, a modulated signal having a low cutoff frequency is received by a low-order channel filter. However, for a signal having a small modulated signal bandwidth such as GSM, the biquad filter LPF2 is used. The resolution of the analog-digital converter (not shown) arranged in the subsequent stage is also high, and the digital filter (see FIG. 1) arranged in the subsequent stage suppresses the residual signal remaining in the band other than the desired signal. can do.

  Similar to the receiving device 40 shown in FIG. 14, since it is generally emphasized that the receiving device has low noise characteristics, the scaling rule shown in FIG. 5 is applied to the biquad filter LPF1 in this embodiment as well. A receiver having a wide dynamic range while maintaining low noise even when one or more of the capacitor C and the capacitor C2 of the biquad filter LPF2 and the resistor R4 are variable capacitors or variable resistors and Q is variable 50 can be provided.

  Further, depending on the system specifications, the biquad filter LPF1 and the biquad filter LPF2 may be configured not only in these two stages but also in multiple stages shown in FIG. In this case, the output of any of the biquad filters LPF1 group to which the scaling rule [S-2] is applied may be output by bypassing the subsequent biquad filters LPF1 group and biquad filter LPF2 group. Furthermore, by arranging the low-pass filter LPF0, it is possible to configure an odd-stage channel filter.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

10 Multistage Active Filter 20 Multistage Active Filter 30 Multistage Active Filter 40 Receiver 50 Channel Filter 60 Receiver LPF1 First Biquad Filter LPF2 Second Biquad Filter INT Input Terminal INB Input Terminal OUTT Output Terminal OUTB Output Terminal XT Internal Node Terminal XB Internal node terminal OPA1 operational amplifier OPA2 operational amplifier RFBB resistor RFBT resistor R1 resistor R2 feedback resistor R3 resistor R4 feedback resistor C1 feedback capacitor C2 feedback capacitor CFBT capacitor CFBB capacitor LPF1 biquad filter LPF2 biquad filter LPF0 low pass filter OUT0T output terminal OUT0T output terminal OPA01 Operational amplifier LPF1 Biquad filter LNA1 Low noise amplifier circuit LoBuf1 Local oscillator circuit LoT Local oscillator Power terminal LoB local oscillation input terminal M MOSFET
OPA1 Fully differential amplifier circuit CFBT1 Variable capacitor CFBB1 is a variable capacitor LPFT1 Biquad filter LPFT2 Biquad filter SW switch

Claims (14)

A multi-stage active filter comprising two biquad filters,
A first biquad filter;
A second biquad filter provided downstream of the first biquad filter,
The resistance values of the resistors and the capacitance values of the capacitors included in the first and second biquad filters are scaled so that the transfer function from the input to the output remains constant and the gain at the internal contact becomes smaller than before the scaling. Which has been
The first biquad filter is scaled so that the resistance value of the first resistor constituting the input unit is equal to or lower than that before scaling,
The second biquad filter is a multistage active filter that is scaled so that the area of the capacitance included in the second biquad filter is equal to or less than that before scaling. A multi-stage active filter comprising two biquad filters,
A first biquad filter;
A second biquad filter provided downstream of the first biquad filter,
The first and second biquad filters are respectively
A first integrator and a second integrator connected thereto;
A first resistor constituting the input part of the biquad filter,
The resistance value of the resistor and the capacitance value of the capacitor included in the first and second biquad filters are obtained from the input of the resistance value of the resistor and the capacitance value of the capacitor included in the first and second biquad filters, respectively. The transfer function to the output remains constant, and the gain at the internal contact is scaled to be smaller than before scaling,
The first and second integrators are respectively a complete integrator whose output is fed back to the input via a feedback capacitor or an incomplete integrator whose output is fed back to the input via a feedback capacitor and a feedback resistor in parallel. Either
The first biquad filter is scaled so that the feedback capacitors of the first integrator and the second integrator have different capacitance values,
The second biquad filter is a multistage active filter that is scaled so that the feedback capacitance of the first integrator and the feedback capacitance of the second integrator are equal.   The multistage active filter according to claim 1, further comprising at least one low-pass filter and / or biquad filter in addition to the first biquad filter and the second biquad filter.   The multistage active filter according to claim 1, wherein the first biquad filter includes N stages (N is an integer of 1 or more) and the second biquad filter includes M stages (M is an integer of 1 or more).   The multistage active filter according to claim 1, further comprising a digital filter subsequent to the second biquad filter. An amplifier circuit to which a radio signal is input;
A passive mixer connected to the amplifier circuit via a capacitor;
A local amplifying circuit for amplifying a local balanced signal for turning on and off a switch of a transistor constituting the passive mixer;
A low-pass filter to which the output signal of the passive mixer is input;
A two-stage active filter to which the output of the low-pass filter is input,
The two-stage active filter is:
A first biquad filter;
A second biquad filter provided downstream of the first biquad filter,
The resistance values of the resistors and the capacitance values of the capacitors included in the first and second biquad filters are scaled so that the transfer function from the input to the output remains constant and the gain at the internal contact becomes smaller than before the scaling. Which has been
The first biquad filter is scaled so that the resistance value of the first resistor constituting the input unit is equal to or lower than that before scaling,
The receiving apparatus, wherein the second biquad filter is scaled so that an area of a capacitor included in the second biquad filter is equal to or less than that before scaling. The first and second biquad filters are respectively
A first integrator and a second integrator connected thereto;
A first resistor constituting the input part of the biquad filter,
The resistance value of the resistor and the capacitance value of the capacitor included in the first and second biquad filters are obtained from the input of the resistance value of the resistor and the capacitance value of the capacitor included in the first and second biquad filters, respectively. The transfer function to the output remains constant, and the gain at the internal contact is scaled to be smaller than before scaling,
The first and second integrators are respectively a complete integrator whose output is fed back to the input via a feedback capacitor or an incomplete integrator whose output is fed back to the input via a feedback capacitor and a feedback resistor in parallel. Either
The first biquad filter is scaled so that the feedback capacitors of the first integrator and the second integrator have different capacitance values,
The receiving apparatus according to claim 6, wherein the second biquad filter is scaled so that a feedback capacity of the first integrator is equal to a feedback capacity of the second integrator. The first and second biquad filters are respectively
A first integrator consisting of a complete integrator whose output is fed back to the input via a feedback capacitor;
A second integrator comprising an incomplete integrator connected to the first integrator, the output of which is fed back to the input via a parallel feedback capacitor and feedback resistor;
The radio signal processing circuit according to claim 6, further comprising a first resistor that constitutes an input unit of the biquad filter. The passive mixer converts the radio signal and the local oscillation signal into a sum of two current components, a difference frequency component and a sum frequency component thereof,
The low-pass filter converts the sum of the two current components into a voltage of a difference frequency component between the radio signal and the local oscillation signal and inputs the voltage to the two-stage active filter. Wireless signal processing circuit.   The radio signal processing circuit according to claim 6, further comprising a switch circuit that bypasses the second biquad filter when a modulated signal having a low cut-off frequency is received as the radio signal.   The radio signal processing circuit according to claim 6, further comprising at least one low-pass filter and / or biquad filter in addition to the first biquad filter and the second biquad filter.   The radio signal processing circuit according to claim 6, wherein the first biquad filter includes N stages (N is an integer of 1 or more) and the second biquad filter includes M stages (M is an integer of 1 or more).   The radio signal processing circuit according to claim 6, further comprising an analog-to-digital converter after the two-stage active filter.   The radio signal processing circuit according to claim 13, further comprising a digital filter after the analog-digital converter.

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