JP2010026950A - Storage device - Google Patents

Abstract

Provided is a storage device that achieves high speed and downsizing with a simple configuration.
A semiconductor nonvolatile memory, a semiconductor volatile memory, a semiconductor nonvolatile memory, and a controller that performs memory access to the semiconductor volatile memory are provided. The controller includes a central processing unit and a control logic circuit. The control logic circuit shares the memory control corresponding to the first frequency for the data transfer operation between the semiconductor nonvolatile memory and the semiconductor volatile memory. The central processing unit shares memory control operations other than memory control performed by the control logic circuit corresponding to a second frequency lower than the first frequency.
[Selection] Figure 1

Description

  The present invention relates to a storage device and, for example, relates to a technique that is effective when used in a storage device configured using a NAND flash memory and capable of replacing an HDD.

Japanese Patent Application Laid-Open Nos. 7-302176 and 2007-280140 disclose a storage device that can replace, for example, an HDD using a type flash memory. In these storage devices, the entire memory is controlled using a microcomputer such as a CPU (central processing unit).
JP-A-7-302176 JP 2007-280140 A

  A semiconductor nonvolatile memory such as a NAND flash memory has been increased in capacity and speed due to progress in semiconductor technology. Similarly, higher speed is also being promoted in a semiconductor volatile memory such as a synchronous random access memory (hereinafter simply referred to as SDRAM) mounted as a cache memory or the like. Therefore, the inventors of the present application faced the following problems in examining the speed-up of a storage device (Solid State Drive; SSD) for HDD compatibility and the like. For example, in a CPU that operates with a clock corresponding to the SDRAM that operates at about 130 MHz, it is necessary to flow a large current in order to realize an operating speed corresponding to that, so the amount of heat generation is large. In an HDD compatible storage device, a large number of flash memories and controllers for realizing the storage capacity required for a small package are mounted at a high density, so the heat generated by the CPU adversely affects the data retention characteristics of the flash memory. End up. Therefore, when a high-speed CPU as described above is used, a powerful cooling means is required. Such CPU heat generation and its cooling means greatly impair the low power consumption and miniaturization required for the HDD-compatible storage device.

  When using the SDRAM as a cache memory or a buffer memory or the like, in order to cope with an unexpected power cut-off, etc., in order to secure an operating voltage for saving SDRAM data to a flash memory using a held charge of a capacitor or the like, If the current consumption of the CPU is large, the data cannot be saved. The controller of the storage device also requires various circuits such as an external input / output interface, an ECC (error detection / correction circuit), an interface with a flash memory and an SDRAM. Therefore, in order to reduce the size of the storage device, it is beneficial to configure the CPU and the various circuits using a so-called system LSI composed of a single semiconductor integrated circuit device. This is not suitable for mounting a CPU that requires cooling.

  An object of the present invention is to provide a storage device that achieves high speed and downsizing with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. The storage device includes a semiconductor nonvolatile memory, a semiconductor volatile memory, and a controller that performs memory access to the semiconductor nonvolatile memory and the semiconductor volatile memory. The controller includes a central processing unit and a control logic circuit. The control logic circuit shares the memory control corresponding to the first frequency for the data transfer operation between the semiconductor nonvolatile memory and the semiconductor volatile memory. The central processing unit shares memory control operations other than memory control performed by the control logic circuit corresponding to a second frequency lower than the first frequency.

  By sharing the control logic circuit that has a simple configuration by specializing in simple data transfer between the semiconductor non-volatile memory and the semiconductor volatile memory, etc., and other memory control operations by the low-speed CPU, By avoiding problems such as heat generation in the CPU, it is possible to increase the speed and size of the storage device.

  FIG. 1 is a schematic block diagram showing an embodiment of a storage device SSD (Solid State Drive) according to the present invention. The storage device of this embodiment is not particularly limited as an HDD compatible storage device, but a large number of multi-value (four-value) nonvolatile memories (flash memories) are mounted in one package to store a plurality of pages. A file memory having a capacity is configured. The multi-level (4-level) flash memory can store 2 bits in one memory cell, and corresponds to one of four types of threshold voltage distribution according to 2-bit write information. To have a threshold voltage.

  In the storage device SSD of this embodiment, a semiconductor volatile memory is provided. The semiconductor volatile memory is composed of, for example, SDRAM (Synchronous Dynamic Random Access Memory), and in order to improve the rewrite endurance of the multi-level flash memory, write data from the host and a non-host for managing them. Used to maintain and cache data.

  These multiple semiconductor nonvolatile memories are connected to a control logic circuit (routing block) LTC that constitutes a part of a controller unit that inputs and outputs data through the semiconductor nonvolatile memory I / F (interface). The controller unit includes the logic control circuit LTC and a central processing unit CPU. Data exchange with the outside is not particularly limited, but is performed by an interface I / F such as ATA (AT Attachment).

  The multi-level flash memory is a device that assumes that error bits are generated more frequently than other memory devices and that it is allowed. As data rewriting and erasing are repeated, the memory cell may have deteriorated data storage characteristics, and normal data may not be read at the time of reading. Therefore, when configuring an SSD using a semiconductor nonvolatile memory as a storage medium, an error detection / correction circuit ECC is essential. The error detection / correction circuit ECC performs encoding and decoding of a Hamming code / Reed-Solomon code / BCH code or the like when performing error detection / correction.

  In this embodiment, a power supply detection circuit PDT and a capacitor CP and a switch SW for securing an operating voltage when the power supply is shut off are further provided. The capacitor CP supplies a voltage to the semiconductor nonvolatile memory, the controller unit, the semiconductor volatile memory, and the power detection circuit by the accumulated charge even when an unexpected power interruption occurs on the system side, and the capacitor CP It operates so as to ensure an operating voltage and a save time for saving data to be saved in the semiconductor volatile memory to the semiconductor nonvolatile memory until a normal end state including the interruption process. The capacitor CP is set to have a capacitance value necessary for securing an operating voltage such that the above interruption processing and data saving are performed.

  The power supply detection circuit PDT receives a power supply voltage from the host side such as a microcomputer and detects the power-on and power-off. These power-on detection signal and power-off detection signal are the signals from the controller corresponding to power-on or power-off, or the control of the switch SW and the semiconductor nonvolatile memory in response to the control signal supplied from the control line. It is used to instruct data transfer operations with a semiconductor volatile memory.

  The switch SW is switched between power-on and power-off by a detection signal, and the capacitor CP performs an operation of supplying the holding voltage as an operating voltage of an internal circuit of the storage device SSD from a charging operation by the power supply voltage. The power supply detection circuit PDT also has a function of preventing the operating voltage formed by the capacitor CP from flowing back to the system side so that the holding voltage of the capacitor CP can be used effectively. It is. In the simplest configuration, a power supply voltage from the system side is charged up to the capacitor CP through the switch SW as a power supply voltage of the storage device SSD through a unidirectional element such as a diode, a control unit, a semiconductor nonvolatile memory, It is transmitted to the semiconductor volatile memory, the interface circuit I / F, and the power supply detection circuit.

  When a power interruption occurs on the system side, the voltage detection circuit as described above prevents the controller unit and the semiconductor non-volatile memory from being back-flowed to maintain the operating voltage from the capacitor CP, and the interface circuit I / F Control is performed so as not to respond to the signal from the system side, and when the save data exists in the semiconductor volatile memory, the save data related to a predetermined save area of the semiconductor nonvolatile memory is saved. If the writing operation to the semiconductor nonvolatile memory is being performed, a reset command is issued and the writing operation of the semiconductor semiconductor nonvolatile memory is interrupted. Similarly, if the semiconductor nonvolatile memory is being erased, a reset command is issued and the semiconductor nonvolatile memory erase operation is also interrupted.

  The control logic circuit LTC performs data transfer operations including encoding and decoding in the ECC circuit between the semiconductor nonvolatile memory and the semiconductor volatile memory in order to realize a reduction in size and speed of the storage device SSD. Share specialized and simple memory control. For example, the central processing unit CPU is responsible for memory control operations that do not require high-speed operations such as determination of commands input from the outside, overall management as a storage device, and the like. Therefore, the control logic circuit LTC operates with a clock having a high frequency corresponding to the operating frequency of the semiconductor volatile memory, for example. In contrast, the central processing unit CPU is set to a relatively low frequency at which heat generation does not become a problem and low power consumption is achieved. That is, the operating frequency of the control logic circuit LTC is set to be higher than the operating frequency of the central processing unit CPU. As a result, the storage device can be speeded up and downsized with a simple configuration.

  In this embodiment, a portion surrounded by a dotted line constitutes a controller unit, which is constituted by one semiconductor integrated circuit device (system LSI). In other words, the storage device of this embodiment includes one system LSI, one SDRAM chip, and a plurality of multi-level flash memory chips, switches, and capacitors provided according to the storage capacity.

  The storage device SSD has, for example, the same outer size (70.0 × 100.0 × 9.5 mm) as that of a 2.5-inch hard disk drive device or the same outer size (101. 6 × 146.0 × 25.4 mm), and the connector pin connected to the interface circuit INF is the same as the 2.5 inch hard disk drive device or the 3.5 inch hard disk drive device. It is done. Thus, the storage device SSD of this embodiment is an HDD (Hard Disk Drive) compatible storage device.

  FIG. 2 shows a specific block diagram of an embodiment of the storage device SSD according to the present invention. In this embodiment, an SDRAM that operates at 132 MHz × 16 bits is used as the volatile memory. In addition, the flash memory (hereinafter referred to as FLSH) has a configuration in which eight memory chips MC operating at 33 MHz × 8 bits are arranged in parallel, for example, 4 units (32) or 8 units (64). And so on.

  It is necessary to write / read data to / from the SDRAM with a clock synchronized with the 132 MHz. When data transfer is performed in units of 16 bits as described above, the control logic circuit LTC needs to operate at a high frequency such as 132 MHz. In this embodiment, the control logic circuit LTC is designed to operate at 66 MHz, which is half of the above 132 MHz, by performing data transfer in 32 bits.

  An SDRAM control circuit SDRAMC is disposed on the SDRAM side, and memory access is performed in units of 132 MHz × 16 bits. The memory control circuit SDC has a data buffer DB, receives 132 MHz × 16 bit data read through the SDRAM control circuit SDRAMC, and stores the data for 2 cycles (2 × 16 bit). From the output circuit out, the data is transmitted to the control logic circuit LTC as data in units of 66 MHz × 32 bits. On the other hand, since data is input in units of 66 MHz × 32 bits from the logic control circuit LTC to the memory control circuit SDC as described above, half of the 16 bits are converted into the SDRAM control circuit in the first cycle of 132 MHz. The remaining 16 bits are input to the SDRAM through the SDRAMC in the same manner as described above in the next second cycle. The DMA provided in the memory control circuit SDC performs such SDRAM control.

  It is necessary to write / read data to / from the FLSH with a clock synchronized with the 33 MHz. However, since it is necessary to exchange data with the control logic circuit LTC in units of 66 MHz × 32 bits, a flash memory interface FI / F is provided. The output circuit out of the flash memory interface FI / F outputs data to the control logic circuit LTC in units of 66 MHz × 32 bits. The input circuit in inputs data from the control logic circuit LTC in units of 66 MHz × 32 bits.

  The flash memory FLSH inputs / outputs data in units of 33 MHz × 8 × 8 (64) bits by using eight memory chips MC arranged in parallel. The memory chip MC is a flash memory formed as one semiconductor integrated circuit device. The flash memory interface FI / F is provided with a buffer BUF for four channels toward the flash memory FLSH. One channel includes two buffers BUF that temporarily store data in units of 8 bits corresponding to the two memory chips MC. As a result, 32-bit data corresponding to 66 MHz from the control logic circuit LTC is sequentially stored in the buffer BUF of the flash memory interface FI / F through the input circuit in, and the clock of 33 MHz is stored. Synchronously, 64-bit data is divided into 8 bits and input to 8 memory chips MC of the flash memory FLSH.

  On the other hand, a total of 64 bits of data output from 8 flash memories FLSH in synchronization with a 33 MHz clock are stored in each buffer BUF of the flash memory interface FI / F. Half of the 32-bit data is output to the control logic circuit LTC through the output circuit out in synchronization with the first clock of the first half of 66 MHz, and the remaining half of the 32-bit data is synchronized with the second clock of the second half. It is output to the control logic circuit LTC. The controller FLSHC controls the input circuit in, the output circuit out, and the buffer BUF that input and output data as described above.

  FIG. 3 is a waveform diagram for explaining the data transfer operation. On the SDRAM side, 16-bit data is input / output in synchronization with the 132 MHz clock. On the other hand, on the LTC side, 16 bits × 2 = 32 bits of data is transferred at 66 MHz. On the FLSH side, 8 bits × 8 = 64 bits of data is input / output at 33 MHz. Between SDRAM and LTC, 16 bits synchronized with the first clock of the first half of 132 MHz are stored in one buffer DB by the buffer DB and DMA of the memory control circuit SDC, and synchronized with the second clock of the second half. 16 bits are stored in the other buffer DB and processed as 32-bit data in synchronization with the 66 MHz clock.

  Between the LTC and the FLSH, the 32 bits synchronized with the first clock of the first half of 66 MHz are divided into 4 channels by 8 bits by the buffers BUF and FLSHC of the flash memory interface FI / F, and the four first The 64 bits stored in the buffer BUF and synchronized with the second clock of the latter half are also divided into 4 channels by 8 bits and stored in the 4 second buffers BUF, and 8 by 8 bits in synchronization with the 33 MHz clock. Is input to FLSH. Data transfer in the reverse direction is omitted in the figure, but can be easily understood from the above description.

  In FIG. 2, the control logic circuit LTC has selectors SEL1 to SEL5, and these selectors SEL1 to SEL5 send SDRAM data to the ECC, a signal path for directly transmitting data between the SDRAM and FLSH. A signal path to which the generated parity is added and transmitted to the FLSH, a data path to which the data read from the FLSH is sent to the ECC, and the error-detected / corrected data is stored in the SDRAM, or directly to the interface ATA A signal path corresponding to the operation mode, such as a path to be output to the outside via the, is configured. The switching operation of the selectors SEL1 to SEL5 is performed by the logic circuit LOG. The logic circuit LOG has various settings and control registers, and forms a control signal that forms a signal transmission path corresponding to the operation mode corresponding to the various registers in synchronization with the 66 MHz clock.

  The logic control circuit LTC controls various transfer operations by firmware. For example, it has registers for transfer start, transfer mode, end, error, and interrupt mask. The activation instruction for the transfer start register and the setting for the transfer mode register are executed by the logic circuit LOG (firmware). Control of selectors SEL5, SEL2, SEL3, SEL4, and SEL1 that connect the control logic circuit LTC to each of the SDRAM (SDC), FLSH (FI / F), ECC, ATAC, and SRAM (SRAMC), which are blocks. Is executed by the logic circuit LOG in accordance with the transfer rate.

  The control logic circuit LTC receives a processing end flag and an error presence / absence notification from each block. If it is desired to interrupt the transfer process for some reason, an interrupt signal is transmitted to each block. The control logic circuit LTC performs processing end and error notification to the central processing unit CPU by polling. In addition, the control logic circuit LTC has a signal for distinguishing redundant data and normal data between each block except the ATA block. Each block has a buffer, and exchanges data through the buffer.

  The power detection register PMCR is a register for notifying the central processing unit CPU and the control logic circuit LTC of an interrupt signal for performing a power shutdown process when the power supply voltage drops below a certain value by the power detection circuit PDT of FIG. It is. In the figure, the power supply detection circuit PDT, the switch SW and the capacitor CP in FIG. 1 are omitted. The operation for turning off and on the power is the same as described in the embodiment of FIG. Transfer of the saved data of the SDRAM to the FLSH when the power is shut off can be performed at high speed by adopting the control logic circuit LTC. As a result, the capacitance value of the capacitor CP can be made smaller than when the data is saved by the central processing unit CPU, so that the storage device can be reduced in size and cost.

  The external input / output interface includes an ATA-I / F and its controller ATAC. The photo system HOST is not particularly limited, but data input / output operations are performed in units of 25 MHz × 16 bits.

  The central processing unit CPU is connected to the bus CPU-BUS. This bus CPU-BUS performs data transfer at 16.5 MHz × 32 bits. Therefore, the central processing unit CPU operates at a slower frequency than the slowest flash memory FLSH, such as 16.5 MHz as described above, and heat generation by itself becomes a problem. There is no.

  The central processing unit CPU receives a command such as an operation instruction from the host via the register REG, although not particularly limited. Further, the data exchange between the interface controller ATAC and the ECC or the control logic circuit LTC is different such as 16.5 MHz and 66 MHz in clock frequency and is asynchronous, so that the SRAM (static memory) that operates as a work memory is used. • Random access memory). In other words, the data transfer circuit DMA built in the SRAM controller SRAMC is used to access the storage areas determined in advance. That is, the data written from the central processing unit CPU is read by the control logic circuit LTC, whereby the data can be transmitted from the CPU to the LTC. Conversely, the data written from the control logic circuit LTC can be read by the central processing unit CPU so that the data can be transmitted from the LTC to the CPU.

  In this embodiment, the central processing unit CPU is operated at a low frequency such as 16.5 MHz to avoid the problem of heat generation, and the control logic circuit LTC can be configured with a small circuit scale specialized for a specific data transfer operation. , And operating it at a high frequency such as 66 MHz, it is possible to realize high speed as a storage device. Even if the control logic circuit LTC is operated at a high frequency as described above, the control logic circuit LTC can be configured with a small circuit scale specialized for the specific data transfer operation. An FDM or SSD can be configured using a system LSI including a CPU, LTC, and other circuits, and the storage device can be increased in speed and size.

  In the embodiment of FIG. 2, data input / output is performed in units of 25 MHz × 16 bits by the ATA-I / F. However, as described above, the control logic circuit LTC has 32 bits × 66 MHz. Therefore, the SDRAM can be accessed at 132 MHz × 16 bits, so that it is possible to realize a write / read operation comparable to that of a high-speed HDD.

  The flash memory FLSH is not particularly limited, but a quaternary flash memory is used to increase the storage capacity. When 2 bits can be stored in one memory cell, 2 bits stored in one memory cell are allocated as data of different pages. For example, in a NAND flash memory, data is written and read for each page unit such as 2 kilobytes or 4 kilobytes. When storing the two bits, data corresponding to two row addresses is stored in one memory cell. It is divided into two, such as a lower page (or first page) and an upper page (second page). Depending on the product, it may be called A page or B page.

  In the storage device of this embodiment, a mode for accessing the flash memory FLSH only by the lower page is provided. When the flash memory FLSH is accessed only in the lower page, it can be used as a binary memory cell. As described above, when the memory cell is operated to write in binary, it is known that the write time is reduced to about 30% as compared with the case where the operation speed is quaternary, that is, when the lower page and the upper page are used. ing. This means that the flash memory FLSH can be operated at 66 MHz × 8 bits.

  The control logic circuit LTC can also be operated at 132 MHz × 32 bits. However, since the SDRAM operates at 132 MHz × 16 bits as described above, it does not make sense when data from the SDRAM is written to the FLSH, but 132 MHz × 32 with respect to the external input / output interface ATA-I / F. If a function for inputting high-speed data corresponding to a bit is added, it is possible to take advantage of the high speed due to the binary operation of FLSH. That is, it is possible to realize an ultra-high-speed direct writing function in which the high-speed mode in which the LTC is operated at 132 MHz and the FLSH is 66 MHz and high-speed data is directly written into the FLSH than when externally written into the SDRAM. In this case, such a high-speed input function may be added to the ATA-I / F or ATAC. As for the clock, the SDRAM clock may be diverted to LTC, and the LTC clock may be diverted to FLSH.

  FIG. 4 shows a specific block diagram of another embodiment of the storage device SSD according to the present invention. In this embodiment, the interface I / F is changed to a SCSI (Small Computer System Interface). Correspondingly, the controller is also changed like SCSIC. Other configurations are the same as those of the embodiment of FIG.

  FIG. 5 shows a specific block diagram of still another embodiment of the storage device SSD according to the present invention. In this embodiment, the interface is changed to an interface SATA-I / F such as SATA (Serial Advanced Technology Attachment). SATA is an interface standard for connecting a hard disk or an optical drive to a personal computer. Correspondingly, the controller is also changed to SATAC. Other configurations are the same as those of the embodiment of FIG.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the flash memory may be a NAND flash memory or a NOR flash memory. The operating frequency of SDRAM and FLSH varies depending on the product used. The number of input / output bits is also different. Therefore, in the control logic circuit LTC, it is only necessary to select the combination that provides the highest speed corresponding to the operating frequency and the number of input / output bits of the SDRAM or FLSH connected thereto. A method for inputting a command, an address, and the like for writing / reading data to / from the flash memory is determined corresponding to the flash memory to be used. The storage device of this embodiment is one that is mounted in the same package as the HDD package having an outer size smaller than 2.5 or 3.5 inches, such as 1 inch or 1.8 inches, or originally developed. Various embodiments such as a package or simply mounted on a mounting substrate can be adopted.

  The present invention can be widely used for a storage device using a semiconductor nonvolatile memory such as a flash memory.

1 is a schematic block diagram of an embodiment of a storage device according to the present invention. It is a specific block diagram of an embodiment of a storage device according to the present invention. FIG. 3 is a waveform diagram for explaining a data transfer operation of the storage device of FIG. 2. It is a specific block diagram of another embodiment of the storage device according to the present invention. It is a specific block diagram of another embodiment of the storage device according to the present invention.

Explanation of symbols

  SW ... switch, CP ... capacitor, PDT ... power supply detection circuit, CPU ... central processing unit, SDRAM ... synchronous dynamic random memory (semiconductor volatile memory), FLSH ... flash memory (semiconductor non-volatile memory), MC ... Memory chip, LTC ... control logic circuit, SEL1-5 ... selector, LOG ... logic circuit (firmware), ECC ... error detection / correction circuit, SDC ... memory control circuit, DB ... data buffer, FI / F ... flash memory Interface, BUF ... Buffer, FLSHC ... Controller, SRAM ... Static random access memory (work memory), SRAMC ... SRAM control circuit, PMCR ... Power supply detection register, ATA, SCSI, SATA-I / F ... External input / output interface , A AC, SCSIC, SATAC ... interface controller,

Claims (10)

A semiconductor nonvolatile memory;
Semiconductor volatile memory,
A controller that performs memory access to the semiconductor nonvolatile memory and the semiconductor volatile memory,
The controller
A central processing unit;
Control logic circuit,
The control logic circuit shares a memory control corresponding to a first frequency for a data transfer operation between the semiconductor nonvolatile memory and the semiconductor volatile memory,
The central processing unit shares memory control operations other than memory control performed by the control logic circuit in response to a second frequency lower than the first frequency.
Storage device In claim 1,
It also has a hard disk drive compatible input / output interface,
The semiconductor nonvolatile memory is a NAND flash memory capable of a four-value storage operation,
The semiconductor volatile memory is a synchronous dynamic random access memory.
Storage device. In claim 2,
The controller further comprises an ECC circuit;
The control logic circuit has a signal path for transferring data between the semiconductor nonvolatile memory and the semiconductor volatile memory through the ECC circuit.
Storage device. In claim 2 or 3,
In the semiconductor nonvolatile memory, the first word page sharing one memory cell and the second word page in which the writing time to the first page is longer than the first word page are written in four values. Mode and a second mode for writing in binary only by the first word page,
The operation frequency of the control logic circuit in the second mode performs the data transfer operation corresponding to a frequency higher than the first frequency.
Storage device. In claim 4,
The data transfer operation in the second mode is performed when data input from the input / output interface is written to the semiconductor nonvolatile memory.
Storage device. In claim 4 or 5,
A power detection circuit;
A voltage holding circuit;
The controller
When the power is cut off, the holding voltage of the voltage holding circuit is switched to the operating voltage of the controller, the semiconductor volatile memory, and the semiconductor nonvolatile memory by the power cutoff detection signal of the power detection circuit, and the save target data of the semiconductor volatile memory Read and write to the semiconductor nonvolatile memory,
When the power is turned on, the power supply detection signal of the power supply detection circuit supplies the power supply voltage as the input voltage of the voltage holding circuit, the operation voltage of the controller, the semiconductor volatile memory, and the semiconductor nonvolatile memory, and the semiconductor nonvolatile memory Reading the save target data held in the memory and writing to the semiconductor volatile memory,
Storage device. In claim 6,
In the semiconductor volatile memory, data is input and output in units of 16 bits in synchronization with the first clock.
The semiconductor nonvolatile memory is configured to input and output data in units of 8 bits in synchronization with a second clock corresponding to a quarter of the frequency of the first clock.
The control logic circuit is
Data is transferred in units of 32 bits in synchronization with the third clock corresponding to the frequency of 1/2 of the first clock,
Between the semiconductor volatile memory and the semiconductor volatile memory, there is a memory control circuit that performs data input / output operations in two divided by 16 bits in synchronization with the first clock,
A flash memory interface that performs data input / output operations in units of 64 bits in synchronization with the second clock is provided between the semiconductor nonvolatile memories and the eight semiconductor nonvolatile memories.
Storage device. In claim 7,
The controller, the input / output interface, the memory control circuit, and the flash memory interface are formed in a one-chip semiconductor integrated circuit.
Storage device. In claim 8,
Data exchange between the control logic circuit and the central processing unit is performed via a static random access memory that is formed in the semiconductor integrated circuit and also operates as a work memory of the central processing unit.
Storage device. In claim 9,
The semiconductor nonvolatile memory, the semiconductor volatile memory, the controller, and the input / output interface are mounted in a package having an outer mold size and a connector pin corresponding to a hard disk drive device of 1 inch to 3.5 inch,
Compatible with the above 1 inch to 3.5 inch hard disk drive device,
Storage device.

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