JP2009117774A - Failure analysis method and its device of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique of shortening a TAT of analysis and reducing a burden of an operator by making association of an access to a probing object and a coordinate on layout data easy, in failure analysis of a semiconductor device. <P>SOLUTION: In confirmation of a probing position on an SEM image of real time, after carrying out coordinate system locking to correspond a coordinate system on an SEM image side and a coordinate system on a layout image side, the information specifying the probing position on a layout coordinate system side is displayed on the SEM image side, and, with it as a mark, the analysis system is configured so as to carry out the probing operation. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a failure analysis method and failure analysis apparatus for a semiconductor device, and more particularly to a probing technique in failure analysis of a semiconductor device using an electron beam absorption current (EBAC) analysis technique.

  As a technique examined by the present inventor, for example, the following techniques can be considered in the failure analysis of a semiconductor device.

  As LSI (Large Scale Integrated Circuit) is miniaturized and multi-layered, it is necessary to proceed with failure analysis of LSI using various methods. As one of the methods, the use of electron beam absorption current (hereinafter referred to as “EBAC (Electron Beam Absorbed Current)”) analysis is progressing.

  FIG. 1 is an explanatory diagram showing the principle of EBAC analysis. In the EBAC analysis, as shown in FIG. 1, when the electron beam 101 is irradiated onto the LSI 102, electrons penetrate from the surface to a certain depth and are absorbed by the wiring 103 of the LSI 102 to become a current. This current is detected by the probe (needle) 104 and works on the principle of displaying it as a current image synchronized with the scanning of the electron beam 101. At this time, if there is an open defect in the wiring 103 that detects the current, even if the electron beam 101 is irradiated from the open position first, the current does not flow, and if it is irradiated before, the current flows, It is possible to detect that a contrast is generated in an image displayed at the boundary of the open portion and that there is a defect in the portion. Further, when there is a wiring that is short-circuited with respect to the wiring 103 to be analyzed, when an electron beam is irradiated onto the wiring, the electrons are absorbed and a current flows into the probe 104 through the shorted portion. Wiring detection is also possible.

  FIG. 2A is an image of an EBAC analysis example of an open failure, and FIG. 2B is a diagram illustrating an image of an EBAC analysis example of a short failure. In the actual analysis example, as shown in FIG. 2, the EBAC image and the wiring image on the layout are compared and contrasted to investigate the open defect position and the short partner wiring. As a result, it is possible to physically specify an open location or a short-circuit partner, and it has come to be widely used in failure analysis of semiconductor devices.

  In the procedure so far, a connection hole was formed in the wiring to be analyzed by a focused ion beam to embed a metal film, and the current was detected by probing there. If the wiring or through hole can be directly probed, the focused ion beam process can be omitted, and the analysis TAT (Turn Around Time) can be shortened. In the case of such an apparatus with improved probing accuracy, a function for promptly accessing a wiring or a through hole to be probed based on layout data is indispensable for a recent large-scale LSI. In the absence of this function, a specific pattern in a fine and complicated pattern is visually searched, but this is a complicated operation that imposes a great burden on the operator. In addition, designating the open position detected by EBAC analysis or the coordinates on the layout data of the short partner is the physical analysis of the next process, for example, shape observation by SEM (Scanning Electron Microscope) or TEM (Transmission Electron Microscope). It is also necessary for elemental analysis by AES (Auger Electron Spectroscopy) and EELS (Electron Energy Loss Spectroscopy).

  In addition, as a technique regarding such failure analysis of a semiconductor device, for example, techniques described in Patent Documents 1 to 3 can be cited. Patent Documents 1 to 3 disclose a method of displaying layout data and navigating (guiding) a probe (needle) to an analysis position based on the layout data. However, the following parts are insufficient for each technique, and it is considered that there is a problem in operability in the current analysis.

  Japanese Patent Application Laid-Open No. H10-228667 describes that the probing position can be quickly found by displaying layout data in a window and highlighting a wiring to be analyzed therein. Although this system is described assuming an analysis device such as an EB (Electron Beam) tester, there is no description about a method of correlating with an image actually obtained by the device such as an SEM image. There is no mention of the operator assist function. Therefore, the operator needs to look at the highlighted wiring on the layout image and search for the wiring in the SEM image corresponding to the wiring. In recent LSIs, wiring is crowded, and this work is actually troublesome, and some assistance is indispensable.

  In Patent Document 2, a layout image and an SEM image (in the case of an EB tester) or a SIM (Scanning Ion Microscope) image (in the case of an FIB (Focused Ion Beam) processing apparatus) are operated in conjunction with each other so as to match the visual field and position. It states that the software is organized as follows. However, in Patent Document 2, there is no description about the assist function on the SEM image, and similarly to Patent Document 1, an operator is required to perform troublesome work. When analyzing a large number of LSIs, the burden on the operator is further increased.

Patent Document 3 discloses a system aimed at prompt access to an analysis position using layout data in a charged particle beam (electron beam / ion beam) apparatus similar to the above. In this document, there is a description of a method for clearly indicating an analysis position by displaying a layout image superimposed on an SEM image. Although the access to the analysis position is facilitated by the method of Patent Document 3, it is necessary to go one step further to the operator assist as in Patent Document 1 and Patent Document 2.
Japanese Patent Laid-Open No. 7-240446 Japanese Patent Laid-Open No. 8-054474 Japanese Patent Laid-Open No. 2005-210067

  By the way, as a result of examination by the present inventor on the defect analysis technique of the semiconductor device as described above, the following has been clarified.

  For example, as described above, the conventional technique employs a method in which a layout image is highlighted or displayed in a superimposed manner when a probe is accessed to an analysis target. However, a method for clearly indicating an object to be accessed on an SEM image that is actually observed in real time is not disclosed, and the access position largely depends on the operator's eyes and determination. For this reason, the probing position may be wrong depending on the skill level of the operator. At least it takes time to confirm the probing position, and it takes a burden on the operator. Moreover, in the literature published as a prior art, it is not assumed that the result obtained with the analysis apparatus is further analyzed, and only the place to perform probing is disclosed.

  On the other hand, in the EBAC analysis apparatus targeted by the present invention, after accessing the wiring to be analyzed and obtaining an image of the current, according to the result, the position is determined to be an open defect and the short partner is determined to be a short defect. It is necessary to specify layout wiring data that can specify the location to be analyzed in the next physical analysis process. In this case, if a layout tool different from the analysis device is used, it is possible to proceed with the specific work, but it is time consuming and labor intensive compared to the work associated with the EBAC image on the spot, which is inefficient.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to facilitate the association between the access to the probing target and the coordinates on the layout data in the failure analysis of the semiconductor device, thereby shortening the TAT of the analysis and reducing the burden on the operator. It is to provide the technology that can.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  For confirmation of the probing position in the real-time SEM image, after performing the coordinate system lock that associates the coordinate system on the SEM image side with the coordinate system on the layout image side, the information specifying the probing position on the layout coordinate system side is The analysis system is configured to display on the image side and execute the probing operation using it as a mark.

  For open position specification and short wiring specification after reaction detection, the open position specifies the coordinates of the position specified on the SEM image side, and the short wiring specifies the reaction position specified on the SEM image side and the wiring passing through that position. Extract as a candidate. Repeat this by specifying multiple reaction positions to narrow down the short wiring. The analysis system is equipped with a function to perform this operation.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  (1) By displaying the probing support mark on the real-time SEM image, the operator only has to approach the probe toward the mark, and the probing operation is facilitated. For this reason, it is possible to reduce operation mistakes and reduce the operation burden.

  (2) It is possible to specify the open position and display the layout coordinates on the spot, which is effective in shortening the analysis TAT.

  (3) The wiring of the short partner can be identified and displayed in the layout coordinates on the spot, which is effective in shortening the analysis TAT.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 3 is an external view showing a configuration of a semiconductor device failure analysis apparatus according to an embodiment of the present invention.

  First, an example of the configuration of the failure analysis apparatus according to the present embodiment will be described with reference to FIG. The defect analysis apparatus according to the present embodiment is, for example, an EBAC analysis apparatus, and includes an SEM (Scanning Electron Microscope) 301, an SEM controller 302, an SEM monitor 303, an EBAC amplifier 304, an EBAC processor 305, an EBAC processor monitor 306, It comprises a stage controller 307, a stage monitor 308, a prober controller 309, a blower monitor 310, and the like. As the EBAC processor 305 and the EBAC processor monitor 306, the stage controller 307 and the stage monitor 308, the prober controller 309 and the blower monitor 310, etc., a personal computer or the like is used. Each component is connected by a communication line such as RS232C or Ethernet (registered trademark).

  Based on the principle of analysis shown in FIG. 1, the actual analysis apparatus has a configuration in which an SEM 301 is equipped with an in-vacuum probing mechanism and an EBAC amplifier 304 that amplifies the current detected by the prober is provided, as shown in FIG. ing. For this reason, as hardware of this apparatus, an SEM 301, a prober (equipped in the SEM 301), an EBAC amplifier 304, and a stage (equipped in the SEM 301) on which an analysis target is placed are interlocked. Software installed in the SEM controller 302, the EBAC processor 305, the stage controller 307, the prober controller 309, and the like controls those hardware. Furthermore, a layout viewer (401 in FIG. 4) is required which is software that clearly indicates the probing target based on the layout data, or is equipped with a function of extracting data on open positions and short wiring. In this apparatus, the EBAC amplifier 304 is configured only by hardware. The SEM 301 further includes a vacuum exhaust system.

  FIG. 4 is a diagram showing a data exchange path between software in the failure analysis apparatus according to the present embodiment. In the failure analysis apparatus according to the present embodiment, the system is configured to support analysis through data exchange as shown in FIG. In this system, each controller is manufactured as a separate personal computer due to restrictions on device development. However, as a final configuration, it is desirable to use a system in one personal computer. In that case, various control methods can be considered such as communication between modules instead of communication between personal computers, or control by simply writing and reading data to an appropriate file.

  FIG. 5 is a diagram illustrating an example of a GUI screen displayed on the EBAC processor monitor 306. The GUI (Graphical User Interface) of the analysis support system by the EBAC processor 305 is designed as shown in FIG. 5, for example. Although various operations can be executed here, the main operations are coded so as to enable the following operations in accordance with the respective area divisions.

  (A) SEM image display (SEM / EBAC Image): A stored SEM image or a real-time SEM image captured by a capture board is displayed.

  (B) Layout image display (Layout Image): A layout image captured from the layout viewer 401 is displayed.

  (C) Image adjustment (B / C): Adjusts the brightness and contrast of the SEM image and the layout image.

  (D) Coordinate system lock (Coordination Lock): By sequentially specifying the coordinates of appropriate three marks of the SEM image and the layout image, the two coordinate systems can be mutually contrasted.

  (E) Image operation (Image Display & Save): A wiring name and a comment are added to the displayed SEM image and layout image, and stored and read as necessary.

  (F) Stored SEM image capture (SEM Image Load): Captures the latest stored SEM image or an image in a designated folder.

  (G) Real-time SEM image capture (SEM Image Capture): SEM images are captured from the SEM hard image output via the capture board.

  (H) Position magnification adjustment (Site & FOV Adjust): The position and magnification of each other image are matched.

  (I) Region & Box Operation: A circle (circle) is written in the SEM image. The written circle is also displayed on the layout image at the same position and size. Alternatively, a box (rectangle) is written in the layout image. The written box is displayed at the same position and the same size on the SEM image. Buttons are provided that can store, read, erase one by one, or erase all at once.

  (J) Wiring / position designation (Net / Site Assign): Designates a wiring to be probed or designates wiring layout coordinates. Displays the target wiring and position at the display center of the layout viewer as specified. Here, both specification by key input and specification by file reading are possible.

  (K) Layout viewer operation (CAD Image Operation): A layout viewer screen operation (enlargement / reduction / movement / all-chip display / operation return) is executed.

  (L) Wiring analysis: (i) The wiring passing through the circle set by the area designation is extracted by the layout viewer, and the information of the information is analyzed to identify the wiring of the short partner.

  FIG. 6 is a flowchart showing a schematic flow of EBAC analysis. When the actual analysis is advanced by operating the GUI in which each of the above areas is set, the schematic flow of the EBAC analysis is as shown in FIG. 6, and the details are as follows.

(1) Coordinate system lock (step S601)
In the coordinate system lock, a coordinate conversion coefficient is obtained in order to align the coordinates of the SEM image and the layout image. Using the coordinate system lock operation unit (d), a mark whose position can be set on the SEM image and a position on the layout image corresponding to the position are alternately designated by three points. FIG. 7 is a flowchart showing the flow of the coordinate system lock (step S601). FIG. 8 is a diagram showing an image of the coordinate system lock (step S601). FIG. 7 shows the flow of the locking operation, and FIG. 8 shows an actual image. By this procedure, a primary conversion coefficient between the SEM image coordinate system and the layout image coordinate system is obtained. Even when the tip is tilted by the 3-point lock, it can be dealt with. When the coordinate system lock is completed, all coordinates can be handled in the layout coordinate system.

(2) Analysis target wiring specification (step S602)
(J) The wiring or position information to be analyzed is input to the wiring / position specifying operation unit by key input or file, and a predetermined target can be selected from a plurality of targets by a pull-down menu. When an object is selected, a highlight button is pressed. By this operation, the target wiring is highlighted on the layout viewer, and the image is captured and displayed in the layout image display unit (b).

  FIG. 9 is a flowchart showing the flow from the analysis target wiring specification (step S602) to the EBAC image analysis (step S606). FIG. 10 is a diagram showing image images from the analysis target wiring specification (step S602) to the probing (step S604).

(3) SEM image acquisition (step S603)
The FOV (Field of View) of the layout image display unit (b) displaying the highlighted target wiring can be recognized when the layout image is taken in, and sets the magnification of the SEM displayed in agreement with or close to this FOV. Also, the center coordinates of the target wiring can be captured, and the stage is moved to the stage coordinates obtained by converting the layout coordinates into SEM coordinates. In this state, the stored SEM image capture operation unit (f) is operated to capture the SEM image into the SEM image display unit (a). Thereby, an image at the same position and the same (or close) magnification as the layout image can be displayed.

(4) Probing (step S604)
(4-1) Probing position setting The position to be probed on the layout image can be recognized by the highlight of the wiring or the coordinates being at the center of the image, and if the operator compares the left and right images in the SEM image, Recognizable. However, in order to perform probing more reliably, the probing position is marked with a rectangle in the layout image by operating the mouse. The marked rectangle is displayed with the same size at the same position on the SEM image.

(4-2) Probing The SEM image stored in the SEM controller 302 is captured by operating the real-time SEM image capturing operation unit (g). That is, the NTSC signal output from the SEM is input via the video capture board provided in the EBAC processor 305, and a real-time SEM image is displayed on the SEM image display unit (a). At this time, the marked rectangle is displayed at the same position during the real-time SEM image display while being displayed on a separate layer above the real-time SEM image.

  FIG. 11 is a diagram showing an image of probing. In the above state, the prober is moved closer to the probing position indicated by the rectangular mark as shown in FIG. Since this state displays a real-time SEM image, it can be monitored every moment. When the probe is finally touched down (contacted with the target location), the movement of the probe is stopped. For a touchdown determination, if a large target such as a pad is used, a thick prober may be used to detect contact with a strain gauge or the like. When touching down directly on wiring or through-holes, a thin prober is used, so detection with a strain gauge is almost impossible, so the operator makes a decision by observing the contrast change between the probe tip image and the SEM image. To do.

(5) EBAC image acquisition (step S605)
The EBAC image is an image acquired by inputting a detection current at the probe instead of the secondary electron signal in the SEM image. The image to be read is an image stored in a specific folder in the SEM controller 302, similar to the SEM image, and is displayed on the SEM image display unit (a). For the design shape on the layout of the wiring to be analyzed, if the open is defective, detect the shape in which the wiring response has been interrupted, and if the short is defective, also detect the shape of the short partner wiring become.

  FIG. 12 is a flowchart showing the flow of EBAC image analysis. The flow from EBAC image detection to analysis is as shown in FIG.

(6) EBAC image analysis (step S606)
Analysis in the case of an open failure is a detailed analysis of the open location. FIG. 13 is a diagram showing an image image of open defect analysis. If the portion where the EBAC reaction is interrupted as shown in FIG. 13 is expanded and a through hole exists at that position of the target wiring, there is a high possibility of disconnection / high resistance of the through hole. Observation of the cross section of the hole is a common procedure. On the other hand, if the EBAC reaction is interrupted in the middle of the wiring, there is a high possibility that the wiring is disconnected / high resistance due to foreign matter, and the film is peeled from the upper layer to the target wiring, and the target wiring is observed in a plane. There are many cases. In any case, the layout image is enlarged and the layout is examined in detail, and then the layout coordinates to be observed are designated as an analysis for an open defect.

  On the other hand, in the case of short circuit failure, the shape of the wiring of the short circuit partner can be observed on the EBAC image, but it is unclear to which wiring on the layout image the wiring corresponds. Therefore, it is necessary to first identify the wiring.

  FIG. 14 is a diagram showing an image image of the short defect analysis. An image of the short defect analysis procedure is as shown in FIG. 14, and the area designation operation unit (i) is used for this purpose. Here, the operator selects an appropriate position on the wiring of the short partner that can be observed on the EBAC image, and draws a circle (circle) using the mouse. Usually, two to three circles are sufficient for drawing, but if the number of circles cannot be narrowed down, a circle may be added. If a very large circle is drawn, the number of wirings included in the circle increases, and analysis may take time. Therefore, drawing is performed with an appropriate size in consideration of stage stop accuracy. The drawing position is not particularly limited, and an appropriate position on the reacting wiring may be selected to some extent.

  As analysis after this, you may extract the wiring which passes all the circles set at once. If it takes time to execute the operation, that is, instead of extracting the wiring by the name of the wiring, the method of tracking and extracting the wiring route for each wiring will result in starting the extraction. It may take some time to get out. In that case, it is possible that more circles than necessary are set. Therefore, it is often the case that the analysis is advanced for each circle.

  FIG. 15 is an explanatory diagram showing a procedure for narrowing the short partner wiring. As shown in FIG. 15, after listing the wiring that passes through the initially set circle, the wiring that passes through the next circle is listed, and the common wiring is left. Alternatively, the wiring analysis operation unit (l) is used by a method of arranging at the top of the list. This operation is repeated sequentially for the set circle. In that case, the operator can confirm how many wires have been narrowed at each stage, and select whether or not to enter the next analysis when the number of wires that the operator deems appropriate.

  Furthermore, the hardware analysis such as the EBAC analyzer has been described so far. However, a software failure analysis method for pointing out a wiring or cell having a possibility of failure by interpreting a tester's failure log has been recently developed. It has been developed, and the result of such software analysis can be compared with the result of EBAC analysis that has been narrowed down to some extent by the above operation, so that the wiring of the short partner can be finally narrowed down to one. It becomes possible.

  The next stage is to investigate the relationship between the wiring of the short circuit partner narrowed down by performing such an operation and the wiring originally targeted. Even if the wiring runs side by side, there is almost no probability of a short if the layers are different. In addition, even when the wiring intersects vertically, the probability of short-circuiting there is low. The search target is a search for the closest point in the same layer. In fact, there is one point that happens to be close, and a short circuit may occur there, but the most suspicious part is the part where the wires run side by side in the same layer. If only one point is closest, there is a high probability of a short at that point, so in physical analysis, the upper layer film is peeled off and the closest part is observed.

  On the other hand, in the case of the parallel wiring portion, it is impossible to detect which part is short-circuited by the EBAC analysis, and therefore, the short-circuit position is specified by another analysis device. At this time, the analysis technique used is generally OBIRCH (Optical Beam Induced Resistance Change) analysis. In OBIRCH, an infrared laser with a wavelength of 1.3 μm that does not generate electron-hole pairs is irradiated to a current-carrying wiring, and the wiring resistance that changes due to heating is changed into a two-dimensional image so that the wiring flows. This is a method of visualizing the route. When the OBIRCH analysis is executed by probing the wiring to be analyzed and the wiring of the short-circuited partner to carry out an OBIRCH analysis, if the resistance of the shorted portion is high and it easily reacts to heat, a strong OBIRCH reaction can be detected at the shorted portion. If the wiring is short-circuited, such as in a corridor, the wiring route will react. This is done by selecting the probing position appropriately, confirming the turnover point of the OBIRCH reaction of both wirings, and specifying the short-circuit position. It becomes possible.

  An EBAC processor 305 is operated as a system for executing the above analysis procedure. Although detailed adjustment is not described above, various adjustments for interlocking other than adjustment of the SEM 301, the prober, and the stage itself can be performed by the operation units described above.

  Therefore, according to the failure analysis apparatus and failure analysis method for a semiconductor device according to the present embodiment, the following operations and effects can be obtained.

  In proceeding with the analysis procedure described above, a system such as an EBAC processor is assembled, so that the coordinate system of the SEM image and the coordinate system of the layout can be easily combined, and the analysis target can be quickly accessed according to the layout coordinate system. .

  Furthermore, the wiring to be analyzed is marked with reference to the wiring highlighted on the layout image, and the mark is reflected on the SEM image, and then the probing can be performed while monitoring the real-time SEM image. That is, by displaying the probing support mark on the real-time SEM image, the operator only has to approach the prober toward the mark, and the probing operation is facilitated. For this reason, it is possible to reduce operation mistakes, and it is not necessary to pay attention to both patterns to distinguish between objects that are not necessarily specified and other wirings or through-holes, and it is not necessary to concentrate on probing, thus burdening the operation. Can be reduced.

  After probing, an EBAC reaction is acquired, and based on the acquired EBAC reaction, the open position and the layout structure at that position are investigated. Alternatively, it becomes possible at the time of analysis to specify the wiring of the short partner as a common wiring that passes through the EBAC reaction and to investigate the layout structure in detail.

  Equipped with these functions makes it possible to conduct layout surveys at the analysis site and shorten analysis TAT. In addition, it can reduce the burden on the operator as analysis support software, and it is not necessary to become familiar with different types of CAD tool operation methods, and layout surveys are possible, so even a non-technical engineer can achieve a certain level. Analysis results can be presented, and the range of analysis operators can be expanded.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the defect analysis using the EBAC analysis has been described. However, the present invention is not limited to this, and can be applied to other defect analysis using an electron beam, charged particles, or the like.

  The present invention can be applied to a failure analysis apparatus using an electron beam in failure analysis of a semiconductor device. Furthermore, as the charged particles, there are those in which a focused ion beam apparatus is similarly probed to detect a reaction, and application development is possible for the apparatus. In addition, considering that the wiring is simply narrowed down from the reaction, this is a general failure analysis method, and there is a possibility of development to general failure analysis devices that extract wiring.

It is explanatory drawing which shows the principle of EBAC analysis. (A) is an image of an EBAC analysis example of an open failure, and (b) is a diagram showing an image of an EBAC analysis example of a short failure. 1 is an external view showing a configuration of a failure analysis apparatus for a semiconductor device according to an embodiment of the present invention. It is a figure which shows the data transmission / reception path | route between software in the defect analysis apparatus by one embodiment of this invention. It is a figure which shows an example of the GUI screen displayed on an EBAC processor monitor. It is a flowchart which shows the general | schematic flow of EBAC analysis. It is a flowchart which shows the flow of a coordinate system lock | rock. It is a figure which shows the image image of coordinate system lock. It is a flowchart which shows the flow from analysis object wiring clear to EBAC image analysis. It is a figure which shows the image image from analysis object wiring clear to probing. It is a figure which shows the image image of probing. It is a flowchart which shows the flow of EBAC image analysis. It is a figure which shows the image image of an open defect analysis. It is a figure which shows the image image of a short defect analysis. It is explanatory drawing which shows the narrowing-down procedure of short other party wiring.

Explanation of symbols

101 electron beam 102 LSI
103 Wiring 104, 105 Probe 106 Secondary electron detector 107, 304 EBAC amplifier 108 Pad 301 SEM
302 SEM controller 303 SEM monitor 305 EBAC processor 306 EBAC processor monitor 307 Stage controller 308 Stage monitor 309 Prober controller 310 Blover monitor 401 Layout viewer

Claims (5)

An SEM mechanism, SEM image display means for displaying an SEM image acquired by the SEM mechanism, layout image display means for displaying a layout image to be analyzed, and a probing mechanism for bringing a probe into contact with the analysis object. A failure analysis method in an analysis device,
Lock the coordinate system of the SEM image and the coordinate system of the layout image;
The layout image display means draws a first mark on the layout image;
The SEM image display means draws a second mark of substantially the same size as the first mark at a corresponding position in the SEM image;
A defect analysis method for a semiconductor device, characterized by probing the wiring to be analyzed with the second mark as a reference. The failure analysis method for a semiconductor device according to claim 1,
During the probing, the SEM image is monitored in real time via a capture board,
2. The defect analysis method for a semiconductor device, wherein the second mark is set on a display layer different from a real-time SEM image and is always displayed on an upper layer at the time of monitoring. The failure analysis method for a semiconductor device according to claim 1,
The SEM image display means draws a plurality of third marks on the SEM image;
The layout image display means draws a fourth mark having substantially the same size as the third mark at a corresponding position in the layout image;
The wiring passing through the fourth mark is analyzed and extracted and stored, and the designation of the fourth mark is sequentially advanced so that the common wiring is sorted and displayed at the top of the callable list. Semiconductor device failure analysis method. The failure analysis method for a semiconductor device according to claim 1,
By locking the coordinate system of the SEM image and the coordinate system of the layout image, indicating the wiring and coordinates of the analysis target, highlighting the analysis target, marking the analysis target, probing the analysis target, and probing A failure analysis method for a semiconductor device, comprising performing a series of operations of acquiring a current image and analyzing the acquired image. A computer,
An analysis support program for causing the computer to execute the semiconductor device failure analysis method according to any one of claims 1 to 4,
SEM mechanism,
In-vacuum probing mechanism,
A stage on which the object to be analyzed is placed;
An evacuation system,
A failure analysis apparatus for a semiconductor device, comprising: a SEM controller that controls a SEM mechanism.