JP2008262162A - Semiconductor integrated circuit design method, semiconductor integrated circuit design apparatus, recording medium, and mask manufacturing method - Google Patents

Abstract

The design of a semiconductor integrated circuit is simplified without reducing the screening accuracy.
In a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data, a cell placement and wiring process for placing and wiring a cell for generating the physical layout, and a design rule A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to the rule library for checking, and a mask of the second physical layout that is a verification target when the design rule is not satisfied A mask data processing step for performing data processing, a mask data generation step for generating mask data using the second physical layout that has been subjected to mask data processing in the mask data processing step, and the second physical when the design rule is satisfied Using the layout, create mask data corresponding to the physical layout. And having the mask data creation step of.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit design method, a semiconductor integrated circuit design apparatus, a recording medium, and a mask manufacturing method in which the design method is simplified.

In recent years, the progress of semiconductor device manufacturing technology is very remarkable, and semiconductor devices having a minimum processing dimension of 0.1 μm or less are mass-produced. Such miniaturization is realized by a dramatic advancement of fine pattern formation technology and various EDA (Electronic Design Automation) tools for circuit pattern generation. In an era when the pattern size is sufficiently large, the planar shape of a large-scale integrated circuit (LSI) pattern to be formed on the wafer is directly drawn as a design pattern, a mask pattern faithful to the design pattern is created, and the mask pattern is projected optically. A pattern almost identical to the designed pattern could be formed on the wafer by transferring it onto the wafer by the system and etching the underlayer.
However, as the pattern becomes finer, it has become difficult to faithfully form the pattern in each process, and a problem has arisen that the final finished dimension does not match the design pattern.

Particularly in the lithography and etching processes that are most important for achieving microfabrication, other pattern layout environments arranged around the pattern to be formed greatly affect the dimensional accuracy of the pattern.
Therefore, in order to reduce these influences, optical proximity effect correction (OPC) or process proximity effect correction (OPC) in which an auxiliary pattern is added to the design pattern in advance so that the dimension after processing is formed into a desired pattern. There is a PPC (Process proximity Correction) technique (hereinafter referred to as a PPC technique) (see, for example, Patent Document 1).

  On the other hand, the layout design flow performed upstream of the mask data processing is a timing driven design. In other words, it is necessary to use a design method in which a cell having an unreasonable driving force is used to keep the operation speed of the transistor within the margin, and the buffer is frequently inserted and the timing verification is performed on the resulting layout. There is no state.

As the optical proximity effect correction (OPC) and process proximity effect correction (PPC) techniques become more complicated with the above-described technology, the pattern created by the designer and the mask pattern used during exposure differ greatly, so There is a problem that the finished pattern shape cannot be easily predicted.
Also, in layout design, the insertion of a buffer for converging timing results in an increase in chip area, and timing closure is usually performed with transistors written in the worst (worst) dimensions. For this reason, the problem that an iterative load for converging the timing is increased.

As described above, since the load is doubled in the layout design and the mask data processing (OPC / OPC verification processing) after the design data is completed, verification using a process simulator is indispensable before shipping the design pattern. It has become.
However, since the process verification of the design pattern is performed at the final stage of the design process, the feedback of the verification result is a backtrack of the design process, and there is a problem that the TAT is heavily loaded.
In order to solve the TAT problem, a method has been proposed in which a design pattern that causes a problem in OPC is stored in a database in advance and dealt with by design data, OPC, or lithography rule check (see, for example, Patent Document 2). . In addition, there has been proposed a method of detecting and correcting a pattern that causes a problem in OPC and a pattern that reduces the yield according to the vertex density of the pattern at high speed (for example, see Patent Document 2). Furthermore, a design method for arranging cells that have been subjected to OPC in advance has been proposed (see, for example, Patent Document 3).

  For example, in the conventional placement and routing method, layout prefiltering (extraction of a small margin pattern) is performed when the functional cells of the semiconductor integrated circuit are placed and roughly routed. This pre-filter performs process verification on the layout, and mainly extracts and removes patterns that do not satisfy a predetermined process margin, that is, causes a decrease in yield. Next, a transfer simulation is performed on the mask pattern created by performing proximity effect correction (OPC) processing on the extracted pattern, and if there is a problem as a result of the simulation, the pattern is corrected. The process margin unachieved pattern is subjected to a process verification of a layout at a full chip level in advance before performing placement and routing, and a categorization of a layout having a small process margin is performed based on the result, thereby creating a database and a library. Further, it is necessary to perform verification again when process conditions, OPC, OPC verification processing, and the like change. Therefore, a great load is applied to the preparation for the placement and routing process.

However, with the miniaturization and complication of patterns, problems that cannot be dealt with by the above-described method have occurred. In other words, the technique disclosed in Patent Document 2 has a problem that if the correction is performed at the artwork stage, TAT is increased.
On the other hand, with the technique disclosed in Patent Document 3, there is a problem that a load is applied to the OPC applied in advance, and further, with the technique disclosed in Patent Document 2, screening accuracy cannot be obtained only by information on the vertex density of the pattern. There is a problem.
Furthermore, pattern matching and database creation for TAT shortening has a problem that it takes time to set up the library and database because there are too many variations of the process margin unachieved pattern that becomes a problem as a result of process verification. It becomes tough for practical use.
Furthermore, as the pattern becomes finer, the pattern that does not satisfy the process margin becomes enormous and the categorization itself may fail.

JP-A-9-319067 JP 2006-126745 A US Pat. No. 6,425,117

  The problem to be solved is that, as the pattern becomes finer and more complex, if it is corrected at the artwork stage, TAT will increase, the proximity effect correction itself will be burdened, and the accuracy of screening will not be obtained. The problem is occurring.

  It is an object of the present invention to simplify or eliminate the design of a semiconductor integrated circuit without reducing screening accuracy by relaxing or excluding verification of a pattern having a margin.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit design method comprising: a cell for generating a physical layout in a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data; A cell placement and routing process for placing and wiring, a design rule check process for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check, and the design rule check When the design rule is satisfied in the process, the second physical layout is used to create mask data corresponding to the physical layout, and the design rule check process does not satisfy the design rule. Second physical layout mask to be verified A mask data processing step for performing data processing, and a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout subjected to the mask data processing in the mask data processing step. It is characterized by.

  In the method of designing a semiconductor integrated circuit according to the first aspect of the present invention, the design rule check process after the cell placement and wiring process is performed on a full chip scale, and a pattern having a margin is excluded from the verification target. By making use of the work of proximity effect correction and process margin verification that was performed in advance when creating the library and database for pattern matching, the processing flow is improved by removing those that do not require verification from the processing flow. Can do. Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  According to a third aspect of the present invention, there is provided a semiconductor integrated circuit design method according to a third aspect of the present invention, wherein a semiconductor integrated circuit design method generates a physical layout of a semiconductor integrated circuit based on semiconductor integrated circuit design data. A cell placement and routing process for placing and wiring, a design rule check process for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check, and the design rule check A correction determination step for determining whether or not proximity effect correction is to be performed on the second physical layout that satisfies the design rule in the step; and if the correction determination step determines that no correction is necessary, the correction is determined to be unnecessary. Mask data corresponding to the physical layout is generated using the second physical layout. A proximity effect correction step for performing proximity effect correction on the second physical layout that is a determination target when correction is determined to be necessary in the mask data creation step and the correction determination step, and correction in the proximity effect correction step The second physical layout that has been subjected to verification when the design rule is not satisfied in the mask data creation step that creates mask data corresponding to the physical layout using the second physical layout that has been performed, and the design rule check step A proximity effect correction step of correcting a physical layout for a proximity effect; a process margin verification step of verifying whether or not the second physical layout subjected to the proximity effect correction in the proximity effect correction step has a predetermined process margin; If it is determined in the process margin verification step that there is a process margin, the second physical that is the determination target A process of adding a second physical layout rule to the rule library and generating mask data of the physical layout corresponding to the second physical layout; and a process margin verification process. When it is determined that there is no margin, the correction / correction / verification process for correcting the pattern of the second physical layout, the artwork, the proximity effect correction, and the proximity effect correction verification, and the correction / correction / verification process And a mask data creating step of creating mask data corresponding to the physical layout using the second physical layout subjected to the process.

  In the method of designing a semiconductor integrated circuit according to the third aspect of the present invention, the design rule check process after the cell placement and routing process is performed on a full chip scale, and a pattern having a margin in margin has conditions for proximity effect correction and proximity effect correction verification. Because it is mitigated or excluded from the verification target, it makes use of the work of proximity effect correction and process margin verification that has been performed in advance when creating the library and database for pattern matching so far, but verification is unnecessary By removing from the processing flow, processing efficiency can be improved. Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit design method according to the present invention, wherein a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data is a cell for generating the physical layout. A cell placement and wiring step for placing and wiring, a step for setting a threshold value for image contrast and coverage on a semiconductor substrate, and a contrast of the layout, and a layout obtained by placing and wiring the cells. A contrast check step for comparing with the contrast calculation result with reference to the contrast threshold value, and when the contrast calculation result is equal to or less than the contrast threshold value in the contrast check step, the contrast is a threshold value. Acquisition of transcription information for the area below the value, physics of that area A correction process for performing correction of artwork, artwork processing, a proximity effect correction for the physical layout subjected to the correction process, a correction / verification process for verifying proximity effect correction, and a physical layout subjected to the correction / verification process. When the calculation result of the contrast of the layout is larger than the threshold value related to the contrast in the mask data generating step using the mask data generating step and the contrast check step, the threshold value related to the coverage ratio of the physical layout is referred to. In the coverage ratio checking step for comparing with the information on the coverage ratio of the extracted layout and the coverage ratio checking process, if the information on the coverage ratio satisfies the threshold value on the coverage ratio, A layout extraction step for extracting a layout, and the layout extraction process If the physical layout obtained in step 4 after the correction / verification step is performed, and the information on the coverage does not satisfy the threshold on the coverage in the coverage check step, the physical layout is corrected. -The process after the correction / verification process is performed.

  In the method for designing a semiconductor integrated circuit according to the ninth aspect of the present invention, the contrast check process after the cell placement and wiring process is performed on a full-chip scale, and a pattern having a margin in the margin relaxes the condition for proximity effect correction, or is a verification target Therefore, we take advantage of the work of proximity effect correction and process margin verification that have been performed in advance when creating the library and database for pattern matching, while removing unnecessary processing from the processing flow. Thus, the processing efficiency can be improved. Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  According to a thirteenth aspect of the present invention, there is provided a semiconductor integrated circuit design method according to a thirteenth aspect of the present invention, wherein a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data is a cell for generating the physical layout. Referring to a cell placement and routing process for placing and wiring and a rule library for design rule check, it is verified whether or not the second physical layout of the portion of the physical layout including the cell has a predetermined process margin. When there is a process margin in the design rule check step, and in the design rule check step, a correction determination step for determining whether or not the second physical layout having a margin is subjected to proximity effect correction, and correction is performed in the correction determination step. If it is determined that the correction is unnecessary, the second physical layout determined that the correction is unnecessary is used. A mask data creation step for creating mask data corresponding to the physical layout, and a proximity effect correction and a proximity effect correction for the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step. A correction / verification step to verify, and a mask data creation step to create mask data corresponding to the physical layout using the second physical layout that has been subjected to proximity effect correction and proximity effect correction verification in the correction / verification step; When there is no process margin in the design rule check step, a correction / verification step for performing proximity effect correction and proximity effect correction verification on the second physical layout to be verified, and a threshold value related to the yield of the second physical layout A step of setting and referring to the threshold value and comparing with information on the yield of the second physical layout In the yield evaluation step and the yield evaluation step, when the yield information satisfies the yield threshold, the second physical layout that is the determination target is extracted, and the rule of the second physical layout is the rule. In the rule addition step to be added to the library and the yield evaluation step, if the yield information does not satisfy the yield threshold value, the transfer information of the region where the yield is equal to or less than the threshold value is acquired, 2 correction process for performing physical layout correction and artwork processing, correction / verification process for performing proximity effect correction and proximity effect correction verification on the second physical layout that has been subjected to the correction process, and correction / verification process And a mask data creation step for creating mask data using the second physical layout. To do.

  In the semiconductor integrated circuit design method of the present invention according to claim 13, the design rule check process after the cell placement and routing process is performed on a full chip scale, and a pattern having a margin in the margin has conditions for proximity effect correction and proximity effect correction verification. Because it is mitigated or excluded from the verification target, it makes use of the work of proximity effect correction and process margin verification that has been performed in advance when creating the library and database for pattern matching so far, but verification is unnecessary By removing from the processing flow, processing efficiency can be improved. Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  A semiconductor integrated circuit design method according to a twenty-first aspect of the present invention is the semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data. A yield evaluation is performed by referring to a threshold value relating to a yield of the second physical layout of the portion including the cells of the physical layout, and comparing with information relating to the yield of the second physical layout A physical layout obtained in the layout extraction step, and a layout extraction step of extracting a physical layout that is a determination target when the yield information satisfies a threshold value related to the yield in the yield evaluation step Correction / verification process for proximity effect correction, proximity effect correction verification, In the yield evaluation step, when the yield information does not satisfy the yield threshold, the transfer information of the area where the yield is equal to or less than the threshold is acquired, the second physical layout of the area is corrected, the artwork processing A correction process for performing correction, a verification / verification process for performing proximity effect correction and proximity effect correction verification on the second physical layout subjected to the correction process, and a mask using the second physical layout subjected to the correction / verification process. And a mask data creation step for creating data.

  According to the semiconductor integrated circuit design method of the present invention according to claim 21, a yield evaluation step of referring to a threshold value related to the yield of the second physical layout and comparing it with information related to the yield of the second physical layout is provided. As a result, the design time of the semiconductor integrated circuit can be shortened.

  According to a twenty-second aspect of the present invention, there is provided a design apparatus for performing a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data, wherein the semiconductor integrated circuit design method includes: The shape of the second physical layout including the cells of the physical layout is verified with reference to a cell placement and wiring process for arranging and wiring the cells for generating the physical layout and a rule library for design rule check A design rule check step, a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout when the design rule is satisfied in the design rule check step, and the design rule check If the process does not meet the design rules, Mask data corresponding to the physical layout is created using the mask data processing step for performing the mask data processing of the second physical layout and the second physical layout for which the mask data processing has been performed in the mask data processing step. And a mask data creation step.

  According to the semiconductor integrated circuit design apparatus of the present invention according to claim 22, since the semiconductor integrated circuit design method of the present invention is used, the design rule after the cell placement and wiring process is the same as described above. Since the check process is performed on a full chip scale, and a pattern having a margin is excluded from the verification target, the processing efficiency can be improved.

  A recording medium according to a twenty-third aspect of the present invention is a recording medium on which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data is recorded. The method refers to a cell placement and routing step of placing and wiring cells for generating the physical layout, and a rule library for design rule check, and determines the shape of the second physical layout including the cells of the physical layout. A design rule check step to be verified; a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout when the design rule is satisfied in the design rule check step; and the design If the design rule is not satisfied in the rule check process, Mask data corresponding to the physical layout is created using the mask data processing step for performing the mask data processing of the second physical layout and the second physical layout for which the mask data processing has been performed in the mask data processing step. And a mask data creation step.

  According to the recording medium of the present invention according to claim 23, since the semiconductor integrated circuit design method of the present invention is used, the design rule check process after the cell placement and wiring process is performed as a full chip as described above. Since it is performed on a scale and a pattern having a margin is excluded from the verification target, the processing efficiency can be improved.

  A semiconductor integrated circuit mask manufacturing method according to a twenty-fourth aspect of the present invention is a mask manufacturing method manufactured by using a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data. The semiconductor integrated circuit design method includes the cell of the physical layout with reference to a cell library wiring process for arranging and wiring a cell for generating the physical layout, and a rule library for design rule check A design rule check process for verifying the shape of the second physical layout, and a mask for creating mask data corresponding to the physical layout using the second physical layout when the design rule is satisfied in the design rule check process In the data creation process and the design rule check process, the design The mask data processing step for performing the mask data processing of the second physical layout to be verified and the second physical layout for which the mask data processing was performed in the mask data processing step. And a mask data creating step for creating mask data corresponding to the layout.

  According to the semiconductor integrated circuit mask manufacturing method of the present invention according to claim 24, since the semiconductor integrated circuit design method of the present invention is used, the design after the cell placement and wiring process is performed as described above. Since the rule check process is performed on a full chip scale, and a pattern having a margin is excluded from the verification target, the processing efficiency can be improved.

  According to a 25th aspect of the present invention, there is provided a design apparatus for performing a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data, wherein the semiconductor integrated circuit design method includes: The shape of the second physical layout including the cells of the physical layout is verified with reference to a cell placement and wiring process for arranging and wiring the cells for generating the physical layout and a rule library for design rule check It is determined that no correction is necessary in the design rule check step, the correction determination step for determining whether or not the proximity effect correction is performed on the second physical layout satisfying the design rule in the design rule check step, and the correction determination step. If the physical layout is determined using the second physical layout determined to be unnecessary. A mask data creation step for creating mask data corresponding to the out, and a proximity effect correction step for performing proximity effect correction on the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step And a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout corrected in the proximity effect correction step, and the design rule is not satisfied in the design rule check step A proximity effect correction step for correcting the proximity effect of the second physical layout to be verified, and whether or not the second physical layout subjected to the proximity effect correction in the proximity effect correction step has a predetermined process margin. A process margin verification process for verifying and determining that there is a process margin in the process margin verification process If so, the second physical layout to be determined is extracted, the rule of the second physical layout is added to the rule library, and the mask data of the physical layout corresponding to the second physical layout is created. When it is determined that there is no process margin in the rule addition step and the process margin verification step, the correction of the second physical layout pattern to be determined, artwork, proximity effect correction, and proximity effect correction verification are performed. A correction / verification step and a mask data generation step for generating mask data corresponding to the physical layout using the second physical layout subjected to the correction / correction / verification step are provided.

  According to the semiconductor integrated circuit design apparatus of the present invention according to claim 25, since the semiconductor integrated circuit design method of the present invention is used, the design rule after the cell placement and wiring process is the same as described above. Since the check process is performed on a full-chip scale and the pattern with sufficient margin is relaxed or excluded from the verification target for proximity effect correction and proximity effect correction verification, a pattern matching library and database have been created so far. By making use of the work of proximity effect correction and process margin verification that are sometimes performed in advance, on the other hand, those that do not require verification can be excluded from the processing flow, thereby improving processing efficiency.

  A recording medium according to a twenty-sixth aspect of the present invention is a recording medium on which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data is recorded, and the design of the semiconductor integrated circuit The method refers to a cell placement and routing step of placing and wiring cells for generating the physical layout, and a rule library for design rule check, and determines the shape of the second physical layout including the cells of the physical layout. A design rule check step to be verified; a correction determination step that determines whether or not proximity effect correction is performed on the second physical layout that satisfies the design rule in the design rule check step; and a determination that correction is unnecessary in the correction determination step The physical layout using the second physical layout determined to be unnecessary. A mask data creation step for creating mask data corresponding to a target, and a proximity effect correction step for performing proximity effect correction on the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step And a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout corrected in the proximity effect correction step, and the design rule is not satisfied in the design rule check step A proximity effect correction step for correcting the proximity effect of the second physical layout to be verified, and whether or not the second physical layout subjected to the proximity effect correction in the proximity effect correction step has a predetermined process margin. A process margin verification step for verifying the process margin, and the process margin verification step determines that there is a process margin. The second physical layout as a determination target is extracted, the rule of the second physical layout is added to the rule library, and the mask data of the physical layout corresponding to the second physical layout is created When it is determined that there is no process margin in the additional step and the process margin verification step, correction / correction is performed to correct the pattern of the second physical layout that is the determination target, artwork, proximity effect correction, and proximity effect correction verification A verification process and a mask data generation process for generating mask data corresponding to the physical layout using the second physical layout subjected to the correction / correction / verification process.

  According to the recording medium of the present invention of claim 26, since the method for designing a semiconductor integrated circuit of the present invention is used, the design rule check process after the cell placement and wiring process is performed as a full chip as described above. Patterns with a margin and margin are relaxed, or the conditions for proximity effect correction and proximity effect correction verification are relaxed or excluded from verification. So far, this has been done in advance when creating a pattern matching library and database. By taking advantage of the proximity effect correction and the process margin verification, while removing unnecessary ones from the processing flow, the processing efficiency can be improved.

  A mask manufacturing method according to a twenty-seventh aspect of the present invention is a mask manufacturing method manufactured by using a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data. The circuit design method includes a cell placement and routing step of placing and wiring cells for generating the physical layout, and a second physical layout including the cells of the physical layout with reference to a rule library for design rule check A design rule check step for verifying the shape of the image, a correction determination step for determining whether or not proximity effect correction is performed on the second physical layout satisfying the design rule in the design rule check step, and correction in the correction determination step. If it is determined that the second physical layout is determined to be unnecessary, A mask data creation step for creating mask data corresponding to the physical layout, and proximity that performs proximity effect correction on the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step. An effect correction step, a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout corrected in the proximity effect correction step, and the design rule in the design rule check step If not, a proximity effect correction step for correcting the proximity effect of the second physical layout to be verified, and a predetermined process margin for the second physical layout subjected to the proximity effect correction in the proximity effect correction step A process margin verification process for verifying whether or not the process margin and the process margin verification process When it is determined that there is a gin, the second physical layout that is the determination target is extracted, the rule of the second physical layout is added to the rule library, and the physical layout corresponding to the second physical layout is extracted. When it is determined that there is no process margin in the rule addition step for creating mask data and the process margin verification step, correction of the pattern of the second physical layout that is the determination target, artwork, proximity effect correction, proximity effect correction A correction / correction / verification step for performing verification, and a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout subjected to the correction / correction / verification step. Features.

  According to the mask manufacturing method of the present invention of claim 27, since the semiconductor integrated circuit design method of the present invention is used, the design rule check process after the cell placement and wiring process is performed as described above. Patterns with sufficient margins are relaxed, and the conditions for proximity effect correction and proximity effect correction verification are relaxed or excluded from the verification target. By making use of the proximity effect correction and the process margin verification that are being performed, those that do not require verification can be excluded from the processing flow, thereby improving the processing efficiency.

  A design apparatus according to a twenty-eighth aspect of the present invention is a design apparatus for performing a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data. A cell placement and wiring step for placing and wiring the cells for generating the physical layout, and a contrast of an image on the semiconductor substrate of the layout obtained by calculating and contrasting the layout and placing and routing the cells. A contrast check step for comparing with the calculation result of the contrast with reference to a threshold value, and a region in which the contrast is not more than the threshold value when the calculation result of the contrast is not more than the threshold value for the contrast in the contrast check step. The transcription information of the area, correcting the physical layout of the area, art Mask data using a correction process for performing a correction process, a correction / verification process for performing proximity effect correction and proximity effect correction verification on the physical layout subjected to the correction process, and a physical layout subjected to the correction / verification process When the calculation result of the contrast of the layout is larger than the threshold value related to the contrast in the mask data generating step and the contrast check step, the extraction is performed with reference to the threshold value related to the coverage ratio of the physical layout. In the coverage ratio checking step for comparing with the information regarding the coverage ratio of the layout, and the coverage ratio checking process, when the information regarding the coverage ratio satisfies the threshold value regarding the coverage ratio, the physical layout that is the determination target is extracted. Layout extraction process, and the physical layout obtained in the layout extraction process Then, the steps after the correction / verification step are performed, and the information after the correction / verification step is performed when the information regarding the coverage does not satisfy the threshold value regarding the coverage in the coverage rate check step. It is characterized by.

  According to the semiconductor integrated circuit design apparatus of the present invention according to the twenty-eighth aspect, since the semiconductor integrated circuit design method of the present invention is used, the contrast check after the cell placement and wiring process is performed as described above. Processes are performed on a full chip scale, and patterns with sufficient margin are relaxed or excluded from verification targets, so this has been done in advance when creating a library and database for pattern matching. By making use of the work of proximity effect correction and lithography verification, on the other hand, those that do not need verification can be removed from the processing flow, so that the processing efficiency can be improved.

  According to a recording medium for a semiconductor integrated circuit of the present invention according to claim 29, there is provided a recording medium recording a method for designing a semiconductor integrated circuit when generating a physical layout of the semiconductor integrated circuit from semiconductor integrated circuit design data, The semiconductor integrated circuit design method includes a cell placement and wiring step for placing and wiring the cells for generating the physical layout, a semiconductor having a layout obtained by calculating the contrast of the layout and arranging and wiring the cells. A contrast check step for comparing with a contrast calculation result with reference to a threshold value for contrast of an image on a substrate, and when the contrast calculation result in the contrast check step is equal to or less than a threshold value for the contrast, Acquisition of transfer information for areas where the contrast is below the threshold, Correction process for performing out correction, artwork processing, proximity effect correction for the physical layout subjected to the correction process, correction / verification process for verifying proximity effect correction, and physical layout subjected to the correction / verification process. When the calculation result of the contrast of the layout is larger than the threshold value related to the contrast in the mask data generating step using the mask data generating step and the contrast check step, the threshold value related to the coverage ratio of the physical layout is referred to. In the coverage ratio checking step for comparing with the information on the coverage ratio of the extracted layout and the coverage ratio checking process, if the information on the coverage ratio satisfies the threshold value on the coverage ratio, A layout extracting step for extracting a layout, and the layout extracting step When the obtained physical layout is subjected to the steps after the correction / verification step, and the information regarding the coverage does not satisfy the threshold value regarding the coverage in the coverage check step, the correction / verification step and later The process is performed.

  According to the recording medium of the present invention according to claim 29, since the method for designing a semiconductor integrated circuit of the present invention is used, the contrast check process after the cell placement and wiring process is performed on a full chip scale as described above. In the case of a pattern with margin, the proximity effect correction condition is relaxed or excluded from the verification target, so the proximity effect correction that has been performed in advance when creating the pattern matching library and database, By making use of the lithography verification work, on the other hand, those that do not need verification can be removed from the processing flow, so that the processing efficiency can be improved.

  A mask manufacturing method according to a thirty-third aspect of the present invention is a mask manufacturing method manufactured by using a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data. The circuit design method includes a cell placement and wiring step of placing and wiring the cells for generating the physical layout, and calculating the contrast of the layout and placing the respective cells on the semiconductor substrate in the layout obtained by placement and wiring. A contrast check step for comparing with a contrast calculation result with reference to a threshold value for contrast of an image, and when the contrast calculation result in the contrast check step is less than or equal to the threshold value for contrast, the contrast is reduced. Acquisition of transfer information in the area below the threshold, physical ray in that area A correction process for performing out correction, artwork processing, a proximity effect correction for the physical layout subjected to the correction process, a correction / verification process for verifying proximity effect correction, and a physical layout subjected to the correction / verification process. When the calculation result of the contrast of the layout is larger than the threshold value related to the contrast in the mask data generating step using the mask data generating step and the contrast check step, the threshold value related to the coverage ratio of the physical layout is referred to. In the coverage ratio checking step for comparing with the information on the coverage ratio of the extracted layout and the coverage ratio checking process, if the information on the coverage ratio satisfies the threshold value on the coverage ratio, A layout extraction step for extracting a layout, and the layout extraction step If the information regarding the coverage does not satisfy the threshold regarding the coverage in the coverage check step, the steps after the correction / verification step are performed. A process is performed.

  According to the mask manufacturing method of the present invention according to claim 30, since the semiconductor integrated circuit design method of the present invention is used, the contrast check process after the cell placement and wiring process is performed as a full chip as described above. Since the pattern with a margin and margin is relaxed, the proximity effect correction conditions are relaxed or excluded from the verification target, so the proximity effect correction that has been performed in advance when creating the pattern matching library and database so far Taking advantage of the work of lithography verification, on the other hand, those that do not need verification can be removed from the processing flow, so that the processing efficiency can be improved.

  A semiconductor integrated circuit design apparatus according to a thirty-first aspect of the present invention is a design apparatus for implementing a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data. The design method includes a cell placement and routing process for placing and wiring the cells for generating the physical layout, and a rule library for checking design rules, and a second physical portion of the portion of the physical layout including the cells. A design rule check step for verifying whether or not the layout has a predetermined process margin, and if there is a process margin in the design rule check step, it is determined whether or not to correct the second physical layout having a margin When it is determined that correction is unnecessary in the correction determination step and the correction determination step, the correction The mask data creation process for creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary, and the correction determination process determines that the correction is necessary, the determination target Corresponding to the physical layout by using the correction / verification process for proximity effect correction and proximity effect correction verification of the second physical layout, and the second physical layout subjected to the proximity effect correction and proximity effect correction verification in the correction / verification process A mask data creation step for creating mask data to be performed, and a correction / verification step for verifying proximity effect correction and proximity effect correction for the second physical layout that is a verification target when there is no process margin in the design rule check step; Referring to the threshold value related to the yield of the second physical layout, the yield related to the yield of the second physical layout In the yield evaluation process to be compared with information and in the yield evaluation process, when the yield information satisfies the yield threshold, the second physical layout to be determined is extracted, and the second physical layout rules In the rule adding step and the yield evaluating step, when the yield information does not satisfy the yield threshold value, the transfer information of the area where the yield is equal to or less than the threshold value, Correction process for correcting the second physical layout of the region, performing artwork processing, correction of the proximity effect for the second physical layout that has been subjected to the correction process, correction / verification process for verifying proximity effect correction, and the correction / verification And a mask data creation step for creating mask data using the second physical layout in which the steps are performed. It is characterized by that.

  According to the semiconductor integrated circuit design apparatus of the present invention according to claim 31, the design rule check process after the cell placement and routing process is performed on a full chip scale, and a pattern having a margin in the margin is subjected to proximity effect correction and proximity effect correction verification. Since the conditions are relaxed or excluded from the verification target, the effects of proximity effect correction and lithography verification that have been performed in advance at the time of creating the pattern matching library and database are utilized, but verification is unnecessary. By removing things from the processing flow, processing efficiency can be improved. Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  A recording medium according to a thirty-second aspect of the present invention is a recording medium on which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data is recorded. The method includes a cell placement and routing step for placing and wiring the cells for generating the physical layout, and a rule library for design rule check, and a second physical layout of the portion of the physical layout including the cells is determined. A design rule check step for verifying whether or not a predetermined process margin is present, and a correction determination for determining whether or not the second physical layout having a margin is to be corrected when there is a process margin in the design rule check step And when it is determined that correction is unnecessary in the correction determination step, the correction is determined to be unnecessary. A mask data creation step for creating mask data corresponding to the physical layout using the second physical layout, and the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step. Proximity effect correction, correction / verification process for verifying proximity effect correction, and mask data corresponding to the physical layout are created using the second physical layout subjected to proximity effect correction and proximity effect correction verification in the correction / verification process. A mask data creation step to be performed, and a second physical layout to be verified when there is no process margin in the design rule check step, a proximity effect correction, a correction / verification step for verifying proximity effect correction, and the second physical layout Compared with the information on the yield of the second physical layout with reference to the threshold value of the yield of the second physical layout In the yield evaluation step and in the yield evaluation step, when the yield information satisfies the yield threshold, the second physical layout that is the determination target is extracted, and the rules of the second physical layout are extracted from the rule library. In the rule adding step to be added to and the yield evaluating step, if the yield information does not satisfy the yield threshold, the transfer information of the area where the yield is less than or equal to the threshold is obtained. A correction process for performing physical layout correction and artwork processing, a correction / verification process for performing proximity effect correction and proximity effect correction verification on the second physical layout that has performed the correction process, and the correction / verification process were performed. And a mask data creation step of creating mask data using the second physical layout. .

  According to the recording medium of the present invention according to claim 32, the design rule check process after the cell placement and routing process is performed on a full chip scale, and a pattern with a margin in margin relaxes conditions for proximity effect correction and proximity effect correction verification. Because it is excluded from the verification target, it uses the proximity effect correction and lithography verification work that has been performed in advance when creating the library and database for pattern matching so far. The efficiency of processing can be improved by removing from the above. Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  A mask manufacturing method according to a thirty-third aspect of the present invention is a mask manufacturing method manufactured by using a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data. The circuit design method refers to a cell placement and routing step for placing and wiring the cells for generating the physical layout, and a second rule for the portion of the physical layout including the cells with reference to a rule library for design rule check. A design rule check step for verifying whether or not the physical layout has a predetermined process margin, and if there is a process margin in the design rule check step, whether to correct the second physical layout having a margin is determined. When the correction determination step and the correction determination step determine that correction is not necessary, A mask data creation process for creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary, and a determination target when correction is determined to be necessary in the correction determination process. The physical layout using the second physical layout subjected to proximity effect correction and proximity effect correction verification, and the second physical layout subjected to proximity effect correction and proximity effect correction verification in the correction and verification step. Mask data creation step for creating mask data corresponding to the above, and a correction / verification step for proximity effect correction and proximity effect correction verification of the second physical layout to be verified when there is no process margin in the design rule check step And the second physical layout yield with reference to a threshold value related to the yield of the second physical layout. In the yield evaluation step for comparing with the information to be performed and in the yield evaluation step, when the information on the yield satisfies the threshold on the yield, the second physical layout that is the determination target is extracted, and the second physical layout In the rule addition step of adding a rule to the rule library and the yield evaluation step, if the yield information does not satisfy the yield threshold value, acquisition of transcription information of the area where the yield is equal to or less than the threshold value; A correction process for correcting the second physical layout of the area, performing an artwork process, a correction / verification process for performing proximity effect correction and proximity effect correction verification on the second physical layout that has been subjected to the correction process, And a mask data creation step for creating mask data using the second physical layout subjected to the verification step. It is characterized by that.

  In the mask manufacturing method according to the thirty-third aspect of the present invention, the design rule check process after the cell placement and wiring process is performed on a full-chip scale, and a pattern with a margin margin relaxes the conditions for proximity effect correction and proximity effect correction verification. Or, since it will be excluded from the verification target, we will make use of the proximity effect correction and lithography verification work that has been performed in advance when creating the library and database for pattern matching so far. By removing it, processing efficiency can be improved. Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  According to the semiconductor integrated circuit design method of the present invention according to claim 1, the load of the pattern matching library can be reduced, the data of the full chip processing is reduced, and the verification of the pattern having a margin is excluded. Thus, there is an advantage that the total processing load can be reduced and the design of the semiconductor integrated circuit can be simplified without reducing the screening accuracy.

  According to the semiconductor integrated circuit design method of the present invention according to claim 3, the load of the pattern matching library can be reduced, the data for full-chip processing can be reduced, and verification of a pattern having a margin can be eased or excluded. Thus, there is an advantage that the total processing load can be reduced and the design of the semiconductor integrated circuit can be simplified without reducing the screening accuracy.

  According to the semiconductor integrated circuit design method of the present invention according to claim 9, the design of the semiconductor integrated circuit can be simplified without reducing the screening accuracy. Further, as compared with the semiconductor integrated circuit design method of the present invention according to claim 3, since the library is not created, there is an advantage that the load for creating the library can be reduced.

  According to the semiconductor integrated circuit design method of the present invention according to the thirteenth aspect, since the layout screening is performed using the yield evaluation value, all processes are judged from the viewpoint of yield, and the yield is improved even if the process margin is small. There is an advantage that it is possible to determine that it should be taken, and that the processing of the entire design flow can be made more efficient and simplified without lowering the screening accuracy from different viewpoints.

  According to the semiconductor integrated circuit design method of the present invention according to claim 21, since the layout screening is performed using the yield evaluation value, all processes are judged from the viewpoint of yield, and the yield is improved even if the process margin is small. There is an advantage that it is possible to determine that it should be taken, and that the processing of the entire design flow can be made more efficient and simplified without lowering the screening accuracy from different viewpoints.

  According to the semiconductor integrated circuit design apparatus of the present invention according to claim 22, since the semiconductor integrated circuit design method of the present invention according to claim 1 is used, there is an advantage that the same effect as described above can be obtained.

  According to the recording medium of the present invention of claim 23, since the semiconductor integrated circuit design method of the present invention of claim 1 is used, there is an advantage that the same effect as described above can be obtained.

  According to the mask manufacturing method of the present invention of claim 24, since the semiconductor integrated circuit design method of the present invention of claim 1 is used, there is an advantage that the same effect as described above can be obtained.

  According to the semiconductor integrated circuit design apparatus of the present invention according to claim 25, since the semiconductor integrated circuit design method of the present invention according to claim 3 is used, there is an advantage that the same effect as described above can be obtained.

  According to the recording medium of the present invention of claim 26, since the semiconductor integrated circuit design method of the present invention of claim 3 is used, there is an advantage that the same effect as described above can be obtained.

  According to the mask manufacturing method of the present invention of claim 27, since the semiconductor integrated circuit design method of the present invention of claim 3 is used, there is an advantage that the same effect as described above can be obtained.

  According to the semiconductor integrated circuit design apparatus of the present invention according to claim 28, since the semiconductor integrated circuit design method of the present invention according to claim 9 is used, there is an advantage that the same effect as described above can be obtained.

  According to the recording medium of the present invention of claim 29, since the semiconductor integrated circuit design method of the present invention of claim 9 is used, there is an advantage that the same effect as described above can be obtained.

  According to the mask manufacturing method of the present invention of claim 30, since the semiconductor integrated circuit design method of the present invention of claim 9 is used, there is an advantage that the same effect as described above can be obtained.

  The semiconductor integrated circuit design apparatus according to the thirty-first aspect of the present invention uses the semiconductor integrated circuit design method according to the thirteenth aspect of the present invention, and therefore has the advantage that the same effect as described above can be obtained.

  According to the recording medium of the present invention of claim 32, since the semiconductor integrated circuit design method of the present invention of claim 13 is used, there is an advantage that the same effect as described above can be obtained.

  According to the mask manufacturing method of the present invention of claim 33, since the semiconductor integrated circuit design method of the present invention of claim 13 is used, there is an advantage that the same effect as described above can be obtained.

  An embodiment (first example) of a method for designing a semiconductor integrated circuit according to a first aspect of the present invention will be described with reference to the flowchart of FIG.

  As shown in FIG. 1, in a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data, in a “cell placement and wiring step” S11, functional cells and wiring of the semiconductor integrated circuit are arranged. Arrange to form a physical layout.

Next, referring to the rule for design rule check from “rule library” 21, in “design rule check step” S 12, the second physical layout of the portion including the cell of the physical layout has a predetermined process margin. It is verified whether or not it has. For example, a pattern having a sufficiently large process margin is extracted from the physical layout by design rule check (DRC) with reference to the “rule library” 21.
In this embodiment, as a pattern having a sufficient process margin, for example, an arrangement of short line patterns shown in FIG. 2A, a pattern in which a part of parallel line patterns shown in FIG. The design rule corresponding to the pattern of the long line pattern shown in (4) and the pattern such as the arrangement of the long line pattern and the short line pattern shown in (4) are used.

  Since all the patterns shown in FIGS. 2A to 2D have sufficiently large process margins, for example, proximity effect correction and proximity effect correction verification are not performed.

  As a result, when there is a process margin in the “design rule check process” S12 (in the case of Yes), since the margin is extracted as a sufficiently large pattern, the subsequent process is performed after the “design rule check process” S12. In step S14, mask data corresponding to the physical layout is created using the second physical layout.

On the other hand, when there is no process margin (in the case of No) in the “design rule check process” S12, the “mask data processing process” S13 is performed.
In the “mask data processing step” S13, for example, the proximity effect correction is performed on the second physical layout that is the verification target in the “proximity effect correction step” S13-1.
Next, in the “proximity effect correction verification process” S13-2, the proximity effect correction of the pattern of the second physical layout subjected to the proximity effect correction is verified.
Further, the proximity effect correction, proximity effect correction verification optical conditions, proximity effect correction relaxation conditions, and the like can be changed according to the layout to be processed.

  Next, in the “mask data creation step” S14, mask data corresponding to the physical layout is created using the second physical layout in which the “proximity effect correction verification step” S13-2 is performed.

  In the “mask data processing step” S13, when it is not necessary to perform proximity effect correction on the data of the second physical layout, for example, when a proximity effect correction process is included in the processing flow after creating mask data. The above “proximity effect correction step” S13-1 is not performed, and the “proximity effect correction verification step” S13-2 is performed.

The design rules used in the present embodiment are set variously depending on the product and process.
FIG. 1 shows an example of this embodiment, and the flow of FIG. 1 is not limited as long as a pattern having a sufficiently large process margin can be extracted and mask data can be taped out. For example, instead of design rules, design data may be checked using design data contrast, MEEF (Mask Error Enhancement Factor), and combinations thereof.

  An embodiment (second embodiment) of the semiconductor integrated circuit design method of the present invention according to claim 3 will be described with reference to the flowchart of FIG.

  As shown in FIG. 3, in the method of designing a semiconductor integrated circuit when generating the physical layout of the semiconductor integrated circuit from the semiconductor integrated circuit design data, in the “cell placement and wiring step” S11, the functional cells and wiring of the semiconductor integrated circuit are arranged. Arrange to form a physical layout.

  Next, referring to the rule for design rule check from “rule library” 21, in “design rule check step” S 12, the second physical layout of the portion including the cell of the physical layout has a predetermined process margin. It is verified whether or not it has. For example, a pattern having a sufficiently large process margin of the physical layout is prefiltered by design rule check (DRC) with reference to the “rule library” 21.

  First, as shown in Table 1, a design rule (DR) for a product (provisionally acceptable if there is no official one) is prepared, and a predetermined bias is added to the design rule for matching. Create design rules. Table 1 is a rule for the dimension Lnm and the space Snm of a certain pattern represented by the patterns 1 and 2, and it is determined that the margin is large if a certain pattern in the layout to be verified satisfies the conditions of the L and S dimensions. The In this embodiment, this bias is 30 nm. Next, a layout design rule check (DRC) is performed based on the matching DR.

  Next, when there is a process margin in the “design rule check step” S12 (in the case of Yes), in the “correction determination step” S13, a comparison is made with a predetermined process margin specification, and the second physical with a margin is provided. It is determined whether or not to correct the layout.

  When it is determined in the “correction determination step” S13 that no correction is necessary (in the case of No), the physical layout is added to the physical layout using the second physical layout that is determined to be unnecessary in the “mask data creation step” S14. Create the corresponding mask data.

  When it is determined that correction is necessary in the “correction determination step” S13 (in the case of Yes), the second physical layout that is the determination target is corrected in “correction step” S16. For example, proximity effect correction (for example, OPC) and proximity effect correction verification are performed.

  Next, in the “mask data creation step” S14, mask data corresponding to the physical layout is created using the second physical layout corrected in the “correction step” S16.

  On the other hand, when there is no process margin in the “design rule check process” S12 (in the case of No), the proximity effect correction is performed on the second physical layout to be verified in the “proximity effect correction process” S17.

Next, in “process margin verification step” S18, it is verified whether or not the second physical layout subjected to the proximity effect correction in the proximity effect correction step has a predetermined process margin.

  When it is determined in the “process margin verification step” S18 that there is a process margin (in the case of Yes), “rule addition step” S19, the second physical layout that is the determination target is extracted, and the second physical layout is extracted. Are added to the “rule library” 21.

  On the other hand, if it is determined in the “process margin verification step” S18 that there is no process margin (in the case of No), the correction of the pattern of the second physical layout that is the determination target in the “correction / correction / verification step” S20 is performed. , Artwork, proximity effect correction, proximity effect correction verification.

  Next, in the “mask data creation step” S14, mask data corresponding to the physical layout is created using the second physical layout subjected to the “correction / correction / verification step” S20.

  Further, when pattern matching is performed again in “design rule check” S12, the added pattern is extracted by “extracting margin small pattern”, “proximity effect correction”, “transfer simulation”, “layout correction”. "Is omitted.

  The rule library is obtained as follows.

  For example, as shown in the flowchart of FIG. 4, first, in the “layout creation step”, a first physical layout in which cells constituting the physical layout are arranged and wired is created.

  Next, in the “transfer information creation step”, a proximity effect correction is performed on the first physical layout to perform a simulation of transferring the first physical layout onto the semiconductor substrate, thereby creating transfer information.

  Next, in a “pattern extraction step”, a pattern larger than the process margin of the first physical layout is extracted based on the transfer information.

  Next, in the “rule creating step”, the design rule check rule including the extracted pattern information of the first physical layout is created, and the created rule is stored in the “rule library”.

  In this way, by extracting the second physical layout and adding the rules of the second physical layout to the rule library, the conditions for optical proximity effect correction can be relaxed, the lithography verification conditions can be relaxed, Either relax the proximity effect correction condition and remove it from the lithography verification target, remove the optical proximity effect correction, relax the lithography verification condition, or remove it from the optical proximity effect correction and lithography verification target As a result, the design time of the semiconductor integrated circuit can be shortened.

  In the second embodiment, since the matching bias is set to be large, all layouts written with rules larger than the design rules shown in Table 1 are excluded from the verification target area. That is, the process is performed when “Design Rule Check” is “Yes”. The determination as to whether or not to be the verification target region can be adjusted by changing the bias applied to the design rule in this way. Alternatively, screening can be performed only with the design rules, and the transfer simulation can be performed again under relaxed conditions.

When cutting out a layout, the layout attributes are changed to distinguish them from others, and after verification, the attributes are returned again and taped out.
Further, in the “correction determination step” S13, whether the correction is performed or not is determined when the design rule bias is large and there is clearly a process margin, the process proceeds directly to the “mask data creation step” S14, and the design rule bias is small. In this case, the process proceeds before “correction step” S16, and proximity effect correction and proximity effect correction verification are performed in “correction step” S16. Here, full chip verification can be performed.

  In the second embodiment, for example, when the design rule bias is 10 nm or more, the process directly proceeds to the “mask data creation process” S14, and when the design rule bias is less than 10 nm, the process proceeds to the process before the “correction process” S16. The design rule bias value can be set without limitation.

  The design rule shown in Table 1 used in the second embodiment is an excerpt of a rule regarding a certain pattern, and any design rule can be used as long as it is a design rule.

  In the second embodiment, the bias for creating the matching design rule is 30 nm. However, the value of the design rule bias is not limited to 30 nm and can be set freely.

  Further, as a result of the verification in the “design rule check process” S12, when the “proximity effect correction” S17 and the “process margin verification process” S18 are performed, processing conditions can be set according to the purpose. For example, optical conditions for transfer simulation of proximity effect correction and process margin check were set to an exposure wavelength of 193 nm, NA = 0.75, σ = 0.85, and 2/3 ring zone. On the other hand, the exposure amount was changed by 13.5 mJ and 0.5 mJ steps at the center, and the defocus amount was calculated in a range of ± 0.2 μm in 0.05 μm steps. The set values of the dose and focus conditions were set to 100 nm line and space as target values. In addition, the processing flow “correction step” S16 after tape out includes proximity effect correction (OPC) processing, but proximity effect correction processing may or may not be applied. In the “correction, correction and verification step” S20, although not shown, a tape-out is included between the artwork and the proximity effect correction, and the proximity effect correction (OPC) after this tape-out is performed. Processing may or may not be applied.

  The optical conditions for proximity effect correction, process margin check and proximity effect correction verification, and relaxation conditions for proximity effect correction can be changed according to the layout to be processed without being limited to the method of this embodiment.

  Moreover, each said condition can respond | correspond to various conditions from the starting time of a product until process conditions mature. Furthermore, in the processing of this embodiment, processing priority may be given in consideration of electrical characteristics. In other words, it is possible to always perform a transfer simulation for the portion corresponding to the critical path of the circuit and to perform normal verification processing for the other areas.

In the semiconductor integrated circuit design method according to the second embodiment, the design rule check process after the cell placement and routing process is performed on a full chip scale, and the pattern with a margin in the margin relaxes the conditions for proximity effect correction and proximity effect correction verification. Because it is excluded from the verification target, it uses the proximity effect correction and lithography verification work that has been performed in advance when creating the library and database for pattern matching so far. The efficiency of processing can be improved by removing from the above.
Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  Therefore, the load on the library for pattern matching can be reduced, the data for full-chip processing can be reduced, and the verification of patterns with margins can be relaxed or excluded, thereby reducing the total processing load and screening. There is an advantage that the design of the semiconductor integrated circuit can be simplified without degrading the accuracy.

  An embodiment (third embodiment) of the semiconductor integrated circuit design method of the present invention according to claim 9 will be described with reference to the flowchart of FIG.

  As shown in FIG. 5, in the method of designing a semiconductor integrated circuit when generating the physical layout of the semiconductor integrated circuit from the semiconductor integrated circuit design data, in the “cell placement and wiring step” S31, the functional cells and wiring of the semiconductor integrated circuit are arranged. Arrange to form a physical layout.

  Next, in the “contrast check step” S32, the contrast of the layout is calculated, and the “contrast threshold value” 41 of the image on the semiconductor substrate of the layout obtained by arranging and wiring the cells is referred to. Compare with the contrast calculation result. For example, in the “contrast check step” S32, the slope of the optical image is calculated for each edge of the pattern, and a pattern surrounded by a predetermined contrast specification, for example, a slope value larger than 55 is extracted.

  When the calculation result of the contrast is equal to or less than the threshold value related to the contrast in the “contrast check process” S32 (in the case of No), transfer information of the area where the contrast is equal to or less than the threshold value is acquired in the “correction process” S33. The physical layout of the area is corrected and the artwork is processed.

  Subsequently, in a “correction / verification step” S34, proximity effect correction and proximity effect correction verification are performed on the physical layout subjected to the correction step.

  In the “mask data creation step” S35, mask data is created using the physical layout subjected to the “correction / verification step” S34.

  In the “contrast check process” S32, when the calculation result of the contrast is larger than the threshold value related to the contrast (in the case of Yes), in the “coverage check process” S36, the “threshold value related to the coverage ratio” of the physical layout. ”42 and compared with the information regarding the coverage ratio of the extracted layout. For example, a layout portion having a slope value larger than a predetermined value and a coverage ratio larger than a predetermined coverage ratio specification value (for example, 45%) is extracted.

  In the “coverage check step” S36, when the information on the coverage satisfies the threshold value on the coverage (in the case of Yes), the physical layout that is the determination target is extracted in the “layout extraction step” S37. .

  Then, the processes after the “correction / verification process” S34 are performed on the physical layout obtained in the layout extracting process. In this case, the pattern extracted by the combination of the slope value and the coverage can be processed while relaxing the proximity effect correction (for example, OPC) and proximity effect correction (for example, OPC) verification conditions.

  If the information regarding the coverage does not satisfy the threshold regarding the coverage in the “coverage check step” S36 (in the case of No), the steps after the “correction step” S33 are performed.

  In the third embodiment, the proximity effect correction (OPC) process is omitted, so that processing time is not required. However, when the physical layout is extracted, the transfer simulation using the mask data after the proximity effect correction (OPC) is performed. Since it is not performed, the proximity effect correction (OPC) and the proximity effect correction (OPC) verification in the “correction / verification step” S34 are not omitted, and the “contrast check step” S32 and the “coverage rate check step” S36 are verified. Based on the result, the processing conditions of the “correction / verification step” S34 are determined.

  On the other hand, for a pattern that does not satisfy the specifications in the process of “contrast check step” S32 or “coverage rate check step” S36, in the “correction step” S33, transfer information of an area where the contrast is equal to or less than a threshold value is acquired. The physical layout of the area is corrected, and reprocessing such as artwork processing is performed.

  In this way, by performing the contrast check and coverage check, the conditions for optical proximity correction can be relaxed, the conditions for lithography verification can be relaxed, the conditions for optical proximity correction can be relaxed, and the target for lithography verification The design time of the semiconductor integrated circuit can be removed by removing the optical proximity effect correction, reducing the lithography verification condition, or removing the optical proximity effect correction from the lithography verification target. Can be shortened.

Here, an example of the pattern extracted based on the slope and the coverage is shown in FIG. As an example, the arrangement of the short line patterns shown in FIG. 6 (1), the pattern in which a part of the parallel line patterns shown in (2) is connected, the arrangement of the long line patterns shown in (3), ( An array in which the long line pattern and the short line pattern shown in 4) are mixed was extracted.
Since all the patterns shown in FIGS. 6A to 6D have sufficiently large process margins as a result of the transfer simulation, proximity effect correction and proximity effect correction verification are verification tolerance and proximity effect correction. The number of adjustments can be performed under relaxed conditions.

  Further, as an example, the optical conditions of the transfer simulation of proximity effect correction and process margin check were set to an exposure wavelength of 193 nm, NA = 0.75, σ = 0.85, and 2/3 annular zone. On the other hand, the exposure amount was changed by 13.5 mJ and 0.5 mJ steps at the center, and the defocus amount was calculated in a range of ± 0.2 μm in 0.05 μm steps.

  Note that the set values of the dose amount and the focus condition are, for example, 100 nm line and space as target values.

  Further, the processing flow after tape-out includes the proximity effect correction process, but the proximity effect correction process may or may not be applied.

  Further, the optical conditions for proximity effect correction, process margin check and proximity effect correction verification, the relaxation conditions for proximity effect correction, and the like are not limited to the above conditions, and can be changed according to the layout to be processed.

  In the third embodiment, the slope value is 55 or more and the coverage is 45% or more as the extraction condition, but the extraction condition is not limited to this, and can be set as appropriate. Moreover, you may extract by the combination of not only a slope and a coverage but a CD (critical dimension) value, for example. Further, the proximity effect correction, proximity effect correction verification optical conditions, proximity effect correction relaxation conditions, and the like can be changed according to the layout to be processed.

  Also, these conditions can correspond to various conditions from the time of product launch until the process conditions mature. Furthermore, in the processing of this embodiment, processing priority may be given in consideration of electrical characteristics. In other words, it is possible to always perform a transfer simulation for a portion corresponding to a critical path of the circuit, and use a normal verification process for other areas.

In the method of designing a semiconductor integrated circuit according to the third embodiment, the contrast check process after the cell placement and wiring process is performed on a full chip scale, and the pattern having a margin is relaxed or excluded from the verification target. By using the proximity effect correction and lithography verification work that has been performed in advance when creating the library and database for pattern matching so far, processing that does not require verification is removed from the processing flow. Can be made more efficient.
Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  Therefore, the design of the semiconductor integrated circuit can be simplified without reducing the screening accuracy. Further, as compared with the semiconductor integrated circuit design method of the present invention according to claim 2, there is an advantage that the library creation load can be reduced because the library creation is not performed.

  Next, an embodiment (fourth example) of the semiconductor integrated circuit design method according to the thirteenth aspect of the present invention will be described with reference to the flowchart of FIG.

  As shown in FIG. 7, in the method of designing a semiconductor integrated circuit when generating a physical layout of the semiconductor integrated circuit from the semiconductor integrated circuit design data, in the “cell placement and wiring process”, functional cells and wiring of the semiconductor integrated circuit are placed. To form a physical layout.

  Next, referring to the rule for design rule check from “rule library” 21, in “design rule check step” S 12, the second physical layout of the portion including the cell of the physical layout has a predetermined process margin. It is verified whether or not it has. For example, a pattern having a sufficiently large process margin of the physical layout is prefiltered by design rule check (DRC) with reference to the “rule library”.

  First, as shown in Table 1, a design rule (DR) for a product (provisionally available if there is no official one) is prepared, and a predetermined bias is added to the design rule for matching. Create design rules for Table 1 is a rule for the dimension Lnm and the space Snm of a certain pattern represented by the patterns 1 and 2, and it is determined that the margin is large if a certain pattern in the layout to be verified satisfies the conditions of the L and S dimensions. The In this embodiment, this bias is 30 nm. Next, a layout design rule check (DRC) is performed based on the matching DR.

  Next, when there is a process margin in the “design rule check step” S12 (in the case of Yes), in the “correction determination step” S13, a comparison is made with a predetermined process margin specification, and the second physical with a margin is provided. It is determined whether or not to correct the layout.

  When it is determined in the “correction determination step” S13 that no correction is necessary (in the case of No), the physical layout is added to the physical layout using the second physical layout that is determined to be unnecessary in the “mask data creation step” S14. Create the corresponding mask data.

  When it is determined that correction is necessary in the “correction determination step” S13 (in the case of Yes), the second physical layout that is the determination target is corrected in “correction / verification step” S16. For example, proximity effect correction (for example, OPC) and proximity effect correction verification are performed.

  Next, in the “mask data creation step” S14, mask data corresponding to the physical layout is created using the second physical layout corrected in the “correction / verification step” S16.

  On the other hand, when there is no process margin in the “design rule check process” S12 (in the case of No), the second physical layout that is the verification target is subjected to proximity effect correction and proximity effect correction verification in the “correction / verification process” S16. To do.

  Next, in the “yield evaluation step” S51, the “threshold value related to yield” 61 of the second physical layout is referred to and compared with the information related to the yield of the second physical layout.

  In the “yield evaluation step” S51, when the information on the yield satisfies the threshold value on the yield (in the case of Yes), the second physical layout that is the determination target is extracted in the “rule addition step” S19. The rule of the second physical layout is added to the “rule library” 21.

  On the other hand, in the “yield evaluation step” S51, when the information on the yield does not satisfy the threshold value on the yield (in the case of No), in the “correction step” S52, the transfer information of the area where the yield is not more than the threshold value. Acquisition, correction of the second physical layout of the area, and artwork processing.

  Next, in the “correction / verification step” S53, proximity effect correction and proximity effect correction verification are performed on the second physical layout subjected to the “correction step” S52.

  Next, in the “mask data creation step” S14, mask data corresponding to the physical layout is created using the second physical layout subjected to the “correction / verification step” S53.

  The yield evaluation value in the “yield evaluation step” S51 is as shown in FIG. 8 in the probability density calculated based on the exposure amount variation and the defocus amount variation value of the exposure apparatus as shown in Table 2, for example. In addition, it can be obtained by convolving and integrating a function of the actual number of errors.

  The results are shown in Table 3.

  As shown in Table 3, the left column shows the probability density corresponding to the dimension value of the pattern formed on the wafer when a certain pattern is exposed under exposure conditions within the set range of exposure amount and defocus amount. The right column shows the result of convolution integration of the function of the number of errors shown in FIG. 8 in% notation corresponding to the probability density in the left column. Since this corresponds to the defect probability of the yield, the processing can be determined based on the defect probability value.

In general, the probability density is expressed by equation (3).

  When P in the above equation (3) is a probability that X is continuous and X enters the intervals a and b, if f (x) given by the above equation (3) is a probability density function, there are two variables. The function f (x, y) is as shown in equation (4).

  In the above equation (4), f (x, y) is a simultaneous density variable of a two-dimensional random variable (X, Y) and can be expressed as equation (5).

  That is, the probability density at which the probability density function f (x) of a certain exposure amount and the probability density function f (y) of a certain defocus amount occur simultaneously is given by the product of f (x) and f (y). Therefore, the probability density is obtained by setting the exposure amount variation of the exposure apparatus for processing the product to, for example, 1.5% and the defocus variation to, for example, 0.18%, and the product of the respective probability densities is obtained. The probability density in the case of the focus amount was obtained. Further, Table 2 shows an example of the result of obtaining the probability density in consideration of processing variation and misalignment. The function shown in FIG. 8 is a function indicating the yield of a product, the horizontal axis indicates a dimension (for example, line width) after transfer of a certain pattern, and the vertical axis indicates the yield by the number of errors.

  On the other hand, as shown in Table 3, the line width of the pattern is calculated when exposure is performed under a combination condition of each exposure amount and defocus amount, and a yield evaluation value corresponding to the line width and a predetermined yield evaluation value are calculated. The patterns were extracted by comparing the threshold values.

  In the fourth embodiment, a pattern having a defect probability smaller than 0.1% is extracted. Then, it was considered that the conditions of proximity effect correction and proximity effect correction verification after tape-out of the extracted pattern were relaxed, or the processing of proximity effect correction and proximity effect correction verification was finished.

  As an example, the optical conditions for the transfer simulation of the process margin check in the proximity effect correction and the design rule check were set to an exposure wavelength of 193 nm, NA = 0.75, σ = 0.85, and 2/3 annular zone. On the other hand, the exposure amount was changed by 13.5 mJ and 0.5 mJ steps at the center, and the defocus amount was calculated in a range of ± 0.2 μm in 0.05 μm steps. The set values of the dose and focus conditions were set to 100 nm line and space as target values.

  Further, the processing flow after tape-out includes the proximity effect correction process, but the proximity effect correction process may or may not be applied. In addition, optical conditions for proximity effect correction, process margin check and proximity effect correction verification in design rule check, relaxation conditions for proximity effect correction, and the like can be changed according to the layout to be processed.

  In the fourth embodiment, the exposure apparatus is assumed to be varied, the probability density is calculated assuming the variation function, and the yield evaluation value is calculated using the convolution integral with the actual measurement value. For each probability density, a yield evaluation value can be obtained by multiplying 1 if the yield is 100% in a step function and multiplying 0 if the yield is 0%. Various functions can be set for expressing the variation, the variation function, and the actual measurement value.

  Further, the fluctuation range of the exposure amount and the defocus amount shown in Table 3 is not limited to the described range.

The optical conditions for proximity effect correction, process margin check and proximity effect correction verification, and relaxation conditions for proximity effect correction in the fourth embodiment can correspond to various conditions from the time of product launch until the process conditions mature. it can. Furthermore, in the processing of the fourth embodiment, processing priority may be given in consideration of electrical characteristics.
In other words, it is possible to always perform a transfer simulation for a portion corresponding to a critical path of the circuit, and use a normal verification process for other areas.

  The rule library can be obtained in the same manner as in the second embodiment.

  As described above, in the fourth embodiment, by extracting the second physical layout and adding the rule of the second physical layout to the rule library, the conditions for correcting the optical proximity effect can be relaxed, and the conditions for the lithography verification. , Relax the conditions of optical proximity effect correction, remove from lithography verification target, remove optical proximity effect correction, relax lithography verification conditions, or from optical proximity effect correction and lithography verification target Since any one of them can be removed, the design time of the semiconductor integrated circuit can be shortened.

In the method of designing a semiconductor integrated circuit according to the fourth embodiment, the design rule check process after the cell placement and wiring process is performed on a full chip scale, and the pattern having a margin in the margin relaxes the conditions for proximity effect correction and proximity effect correction verification. Because it is excluded from the verification target, it uses the proximity effect correction and lithography verification work that has been performed in advance when creating the library and database for pattern matching so far. The efficiency of processing can be improved by removing from the above.
Even if the verification target is leaked from the database or library, a pattern with a margin is originally extracted, and the pattern is only subjected to normal processing.

  Therefore, since the screening of the layout was performed using the yield evaluation value, it is possible to judge all processes from the viewpoint of yield and to determine that the yield should be obtained even if the process margin is small. There is an advantage that the processing of the entire design flow can be made more efficient and simplified without dropping.

  In the fourth embodiment, a rule for layout extraction is created based on the result of the transfer simulation, the target layout is selected using the rule, and the determination based on the yield evaluation value is performed. The screening by is not necessarily required, and screening using the yield evaluation value directly may be performed. This will be described below as an embodiment corresponding to claim 21 and a fifth embodiment.

That is, in the semiconductor integrated circuit design method when generating the physical layout of the semiconductor integrated circuit from the semiconductor integrated circuit design data, the “cell placement and wiring process” is performed, and the “design rule check process” is not performed as described above. Then, referring to the “threshold value relating to the yield” of the second physical layout of the portion including the cell of the physical layout, a yield evaluation process for directly comparing with the information relating to the yield of the second physical layout is performed. In the “yield evaluation step”, when the yield information satisfies the yield threshold, the “layout extraction step” extracts the physical layout that is the determination target. Then, proximity effect correction and proximity effect correction verification are performed in the “correction / verification step” on the physical layout obtained in the “layout extraction step”.
On the other hand, in the “yield evaluation process”, when the yield information does not satisfy the yield threshold value, the “correction process” obtains the transfer information of the area whose yield is equal to or less than the threshold value, and the second physical layout of the area. Correction and artwork processing. In the “correction / verification step”, the proximity effect correction and the proximity effect correction verification are performed on the second physical layout subjected to the “correction step”. After that, in the “mask data creation process”, mask data is created using the second physical layout subjected to the “correction / verification process”.

  The rule library can be obtained in the same manner as in the second embodiment.

  According to the semiconductor integrated circuit design method of the fifth embodiment, referring to the threshold value related to the yield of the second physical layout, the “threshold value related to yield”, which is information related to the yield of the second physical layout, Since the “yield evaluation step” for comparison is provided, the design time of the semiconductor integrated circuit can be shortened.

  In addition, since conventional pattern matching is basically a two-dimensional figure matching process, a processing load is applied. However, the design rule check in each of the embodiments described above is a figure calculation process similar to the mask data process. Since the processing load is reduced as compared with the conventional pattern matching processing, there is an advantage that the processing speed can be improved.

Each of the semiconductor integrated circuit design methods of the first, second, third, fourth, and fifth embodiments generates a physical layout of the semiconductor integrated circuit from the semiconductor integrated circuit design data. The present invention can be applied to a design apparatus that performs a method for designing a semiconductor integrated circuit.
Further, the present invention can be applied to a recording medium on which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data is recorded.
Furthermore, the present invention can be applied to a mask manufacturing method manufactured using a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data.

5 is a flowchart showing an embodiment (first example) of a method for designing a semiconductor integrated circuit according to a first aspect of the present invention; It is the pattern layout figure which showed an example of the extracted pattern. 6 is a flowchart showing an embodiment (second embodiment) of a method for designing a semiconductor integrated circuit according to a third aspect of the present invention. It is the flowchart which showed an example which produces a design rule check. It is the flowchart which showed one Embodiment (3rd Example) of the design method of the semiconductor integrated circuit of this invention concerning Claim 9. It is the pattern layout figure which showed an example of the pattern extracted based on the slope and the coverage. It is the flowchart which showed one Embodiment (4th Example) of the design method of the semiconductor integrated circuit of this invention concerning Claim 13. It is a drawing showing the product yield, and is a diagram showing the relationship between the dimension after pattern transfer and the number of errors.

Explanation of symbols

  S11 ... cell placement and routing process, S12 ... design rule check process, S13 ... correction determination process, S14 ... mask creation process, S16 ... correction process, S17 ... proximity effect correction process, S18 ... process margin verification process, S19 ... rule addition process , S20 ... correction / correction / verification step, 21 ... rule library

Claims (33)

In a method of designing a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check;
When the design rule is satisfied in the design rule check step, a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout;
A mask data processing step of performing mask data processing of the second physical layout that has been verified when the design rule is not satisfied in the design rule check step;
A method of designing a semiconductor integrated circuit, comprising: a mask data creation step of creating mask data corresponding to the physical layout using the second physical layout subjected to mask data processing in the mask data processing step. The mask data processing step includes
A proximity effect correction step of performing proximity effect correction of the second physical layout;
The method for designing a semiconductor integrated circuit according to claim 1, further comprising: a proximity effect correction verification step of verifying the second physical layout subjected to the proximity effect correction. In a method of designing a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check;
A correction determination step for determining whether or not proximity effect correction is performed on the second physical layout that satisfies the design rule in the design rule check step;
A mask data creation step of creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary when the correction determination step determines that the correction is unnecessary;
A correction step of performing proximity effect correction on the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step;
Using the second physical layout corrected in the correction step, a mask data creation step of creating mask data corresponding to the physical layout;
When the design rule check process does not satisfy the design rule, a proximity effect correction process for correcting a proximity effect on the second physical layout that is a verification target;
A process margin verification step of verifying whether or not the second physical layout subjected to the proximity effect correction in the proximity effect correction step has a predetermined process margin;
When it is determined in the process margin verification step that there is a process margin, a second physical layout that is a determination target is extracted, a rule of the second physical layout is added to the rule library, and the second physical layout A rule adding step of creating mask data of the physical layout corresponding to
A correction / correction / verification step for performing correction of the pattern of the second physical layout to be determined, artwork, proximity effect correction, and proximity effect correction verification when it is determined in the process margin verification step that there is no process margin; ,
A method for designing a semiconductor integrated circuit, comprising: a mask data creation step of creating mask data corresponding to the physical layout using the second physical layout subjected to the correction / correction / verification step. A layout creating step for creating a first physical layout in which the cells constituting the physical layout are arranged and wired;
A transfer information creating step for creating transfer information by performing a simulation of transferring the first physical layout onto a semiconductor substrate by performing proximity effect correction on the first physical layout;
A pattern extraction step of extracting a pattern larger than the predetermined process margin according to claim 1 of the first physical layout based on the transfer information;
A rule creation step of creating a rule for design rule check according to claim 1 including the extracted pattern information of the first physical layout, and storing the created rule in the rule library. Item 3. A method for designing a semiconductor integrated circuit according to Item 2. The method for designing a semiconductor integrated circuit according to claim 2, wherein the rule is a design rule related to a dimension and a space of a pattern included in the first physical layout, and a rule obtained by adding or subtracting a bias to the design rule. The method of designing a semiconductor integrated circuit according to claim 2, wherein the correction determination step determines whether or not to perform proximity effect correction and proximity effect correction verification as a subsequent correction step. The pattern extraction step includes
Selecting a threshold for a process margin of the second physical layout;
Extracting a pattern having a large process margin of the first physical layout from the threshold value, the transfer information, and the rule,
4. The semiconductor integrated circuit design method according to claim 3, wherein the second physical layout is verified with reference to the extracted first physical layout. The extraction of the second physical layout is as follows:
The method for designing a semiconductor integrated circuit according to claim 2, further comprising: changing an attribute of the layout and creating a small area layout including a layout to be extracted. In a method of designing a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A step of setting a threshold value regarding the contrast and coverage of an image on a semiconductor substrate; and calculating the contrast of the layout, with reference to the threshold value regarding the contrast of the layout obtained by arranging and wiring the cells, A contrast check step for comparing with the calculation result of the contrast;
If the contrast calculation result in the contrast check step is less than or equal to a threshold value related to the contrast, the transfer information of the area where the contrast is less than the threshold value is acquired, the physical layout of the area is corrected, and the artwork processing is corrected. Process,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the physical layout subjected to the correction step;
A mask data creation step of creating mask data using the physical layout subjected to the correction / verification step;
In the contrast check step, if the calculation result of the contrast of the layout is larger than a threshold value related to the contrast, the threshold value related to the coverage ratio of the physical layout is referred to and compared with the information related to the coverage ratio of the extracted layout. Covering coverage check process,
In the coverage rate check step, when the information on the coverage rate satisfies a threshold value related to the coverage rate, the layout extraction step of extracting a physical layout that is a determination target,
For the physical layout obtained in the layout extraction step, perform the steps after the correction / verification step,
In the coverage check step, when the information regarding the coverage does not satisfy the threshold regarding the coverage, the steps after the physical layout correction / correction / verification step are performed. Method. 9. The method of designing a semiconductor integrated circuit according to claim 8, wherein the contrast threshold value is obtained by evaluating a layout of a target generation in advance or using an empirical value. The method for designing a semiconductor integrated circuit according to claim 8, wherein the information related to the contrast is a single derivative of light intensity of an optical image. 9. The method of designing a semiconductor integrated circuit according to claim 8, wherein the extraction of the physical layout includes changing layout attributes and creating a small area layout including the layout to be extracted. In a method of designing a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying whether or not the second physical layout of the portion including the cell of the physical layout has a predetermined process margin with reference to a rule library for design rule check;
When there is a process margin in the design rule check step, a correction determination step for determining whether to perform proximity effect correction on the second physical layout with a margin;
A mask data creation step of creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary when the correction determination step determines that the correction is unnecessary;
When it is determined in the correction determination step that correction is necessary, the correction step of verifying proximity effect correction and proximity effect correction of the second physical layout that has been determined;
Using the second physical layout subjected to proximity effect correction and proximity effect correction verification in the correction step, a mask data creation step of creating mask data corresponding to the physical layout;
When there is no process margin in the design rule check process, the correction / verification process for verifying the proximity effect correction and the proximity effect correction for the second physical layout to be verified;
A yield evaluation step of referring to a threshold related to the yield of the second physical layout and comparing it with information related to the yield of the second physical layout;
In the yield evaluation step, when the yield information satisfies the yield threshold, a second physical layout that is a determination target is extracted, and a rule for adding the second physical layout rule to the rule library is added Process,
When the yield information does not satisfy the yield threshold value in the yield evaluation step, the transfer information of the area where the yield is less than the threshold value is acquired, the second physical layout of the area is corrected, and the artwork processing A correction process to perform,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the second physical layout that has been subjected to the correction step;
And a mask data creation step for creating mask data using the second physical layout subjected to the correction / verification step. A layout creating step for creating a first physical layout in which the cells constituting the physical layout are arranged and wired;
A transfer information creating step for creating transfer information by performing a simulation of transferring the first physical layout onto a semiconductor substrate by performing proximity effect correction on the first physical layout;
A pattern extraction step of extracting a pattern larger than a process margin of the first physical layout based on the transfer information;
The semiconductor device according to claim 13, further comprising: a rule creating step of creating a rule for checking the design rule including the extracted pattern information of the first physical layout and storing the created rule in the rule library. Integrated circuit design method. The verification of the information related to the yield of the second physical layout in the yield evaluation step is performed by determining a threshold related to the yield in advance and referring to the threshold related to the yield. A method for designing a semiconductor integrated circuit. The yield information is

P: When X is continuous and X is a probability of entering intervals a and b, a certain two-variable function f (x, y) is obtained by using f (x) given by the equation (1) as a probability density function.

14. The simultaneous probability density function given by the simultaneous density variable of the two-dimensional random variable (X, Y) given by the above, and the result obtained by taking into account the processing variation, the misalignment variation, and the experimental result. The semiconductor integrated circuit design method described. The method of designing a semiconductor integrated circuit according to claim 16, wherein the simultaneous probability density function is given by a product of probability densities related to an exposure amount and a defocus amount of an exposure apparatus that processes the second physical layout. The method of designing a semiconductor integrated circuit according to claim 16, wherein the experimental result is the number of defects in a pattern after transfer on a semiconductor substrate. The pattern extraction step includes
Selecting a threshold for a process margin of the second physical layout;
Extracting a pattern with a large process margin of the first physical layout from the threshold value related to the process margin of the second physical layout, the transfer information, and the rule library;
The method of designing a semiconductor integrated circuit according to claim 13, wherein the second physical layout is verified with reference to the extracted first physical layout. The extraction of the second physical layout is as follows:
The method for designing a semiconductor integrated circuit according to claim 13, comprising changing the attribute of the layout and creating a small area layout including the layout to be extracted. In a method of designing a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A yield evaluation step of referring to a threshold value related to a yield of a second physical layout of a portion including the cell of the physical layout and comparing with a threshold value related to a yield of the second physical layout;
A layout extraction step of extracting a physical layout that is a determination target when the yield information satisfies a threshold value related to the yield in the yield evaluation step;
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the physical layout obtained in the layout extraction step;
When the yield information does not satisfy the yield threshold value in the yield evaluation step, the transfer information of the area where the yield is less than the threshold value is acquired, the second physical layout of the area is corrected, and the artwork processing A correction process to perform,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the second physical layout that has been subjected to the correction step;
And a mask data creation step for creating mask data using the second physical layout subjected to the correction / verification step. In a design apparatus for implementing a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check;
A mask data processing step of performing mask data processing of the second physical layout that has been verified when the design rule is not satisfied in the design rule check step;
When the design rule is satisfied in the design rule check step, a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout;
A mask data processing step of performing mask data processing of the second physical layout that has been verified when the design rule is not satisfied in the design rule check step;
And a mask data creation step of creating mask data corresponding to the physical layout using the second physical layout that has been subjected to mask data processing in the mask data processing step. A recording medium recording a design method of a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check;
When the design rule is satisfied in the design rule check step, a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout;
A mask data processing step of performing mask data processing of the second physical layout that has been verified when the design rule is not satisfied in the design rule check step;
Using the second physical layout subjected to mask data processing in the mask data processing step, a mask data creation step for creating mask data corresponding to the physical layout and mask data creation for creating mask data corresponding to the physical layout A recording medium comprising the steps of: In a mask manufacturing method manufactured using a semiconductor integrated circuit design method when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check;
When the design rule is satisfied in the design rule check step, a mask data creation step for creating mask data corresponding to the physical layout using the second physical layout;
A mask data processing step of performing mask data processing of the second physical layout that has been verified when the design rule is not satisfied in the design rule check step;
And a mask data creating step for creating mask data corresponding to the physical layout using the second physical layout subjected to mask data processing in the mask data processing step. . In a design apparatus for implementing a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check;
A correction determination step for determining whether or not proximity effect correction is performed on the second physical layout that satisfies the design rule in the design rule check step;
A mask data creation step of creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary when the correction determination step determines that the correction is unnecessary;
A correction step of performing proximity effect correction on the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step;
Using the second physical layout corrected in the correction step, a mask data creation step of creating mask data corresponding to the physical layout;
When the design rule check process does not satisfy the design rule, a proximity effect correction process for correcting a proximity effect on the second physical layout that is a verification target;
A process margin verification step of verifying whether or not the second physical layout subjected to the proximity effect correction in the proximity effect correction step has a predetermined process margin;
When it is determined in the process margin verification step that there is a process margin, a second physical layout that is a determination target is extracted, a rule of the second physical layout is added to the rule library, and the second physical layout is A rule adding step of creating mask data of the physical layout corresponding to
A correction / correction / verification step for correcting the pattern of the second physical layout, the artwork, the proximity effect correction, and the proximity effect correction verification when it is determined in the process margin verification step that there is no process margin; ,
A design apparatus comprising: a mask data creation step of creating mask data corresponding to the physical layout using the second physical layout subjected to the correction / correction / verification step. A recording medium recording a design method of a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check;
A correction determination step for determining whether or not proximity effect correction is performed on the second physical layout that satisfies the design rule in the design rule check step;
A mask data creation step of creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary when the correction determination step determines that the correction is unnecessary;
A correction step of performing proximity effect correction on the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step;
Using the second physical layout corrected in the correction step, a mask data creation step of creating mask data corresponding to the physical layout;
When the design rule check process does not satisfy the design rule, a proximity effect correction process for correcting a proximity effect on the second physical layout that is a verification target;
A process margin verification step of verifying whether or not the second physical layout subjected to the proximity effect correction in the proximity effect correction step has a predetermined process margin;
When it is determined in the process margin verification step that there is a process margin, a second physical layout that is a determination target is extracted, a rule of the second physical layout is added to the rule library, and the second physical layout is A rule adding step of creating mask data of the physical layout corresponding to
A correction / correction / verification step for performing correction of the pattern of the second physical layout to be determined, artwork, proximity effect correction, and proximity effect correction verification when it is determined in the process margin verification step that there is no process margin; ,
And a mask data creation step of creating mask data corresponding to the physical layout using the second physical layout subjected to the correction / correction / verification step. In a mask manufacturing method manufactured using a semiconductor integrated circuit design method when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying the shape of the second physical layout including the cells of the physical layout with reference to a rule library for design rule check;
A correction determination step for determining whether or not proximity effect correction is performed on the second physical layout that satisfies the design rule in the design rule check step;
A mask data creation step of creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary when the correction determination step determines that the correction is unnecessary;
A correction step of performing proximity effect correction on the second physical layout that is a determination target when it is determined that correction is necessary in the correction determination step;
Using the second physical layout corrected in the correction step, a mask data creation step of creating mask data corresponding to the physical layout;
When the design rule check process does not satisfy the design rule, a proximity effect correction process for correcting a proximity effect on the second physical layout that is a verification target;
A process margin verification step of verifying whether or not the second physical layout subjected to the proximity effect correction in the proximity effect correction step has a predetermined process margin;
When it is determined in the process margin verification step that there is a process margin, a second physical layout that is a determination target is extracted, a rule of the second physical layout is added to the rule library, and the second physical layout is A rule adding step of creating mask data of the physical layout corresponding to
A correction / correction / verification step for performing correction of the pattern of the second physical layout to be determined, artwork, proximity effect correction, and proximity effect correction verification when it is determined in the process margin verification step that there is no process margin; ,
A mask manufacturing method for a semiconductor integrated circuit comprising: a mask data creating step for creating mask data corresponding to the physical layout using the second physical layout subjected to the correction / correction / verification step. In a design apparatus for implementing a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A contrast check step of calculating a contrast of the layout, referring to a threshold value regarding a contrast of an image on a semiconductor substrate of a layout obtained by arranging and wiring the cells, and comparing the calculation result of the contrast;
If the contrast calculation result in the contrast check step is less than or equal to a threshold value related to the contrast, the transfer information of the area where the contrast is less than the threshold value is acquired, the physical layout of the area is corrected, and the artwork processing is corrected. Process,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the physical layout subjected to the correction step;
A mask data creation step of creating mask data using the physical layout subjected to the correction / verification step;
In the contrast check step, if the calculation result of the contrast of the layout is larger than a threshold value related to the contrast, the threshold value related to the coverage ratio of the physical layout is referred to and compared with the information related to the coverage ratio of the extracted layout. Covering coverage check process,
In the coverage rate check step, when the information on the coverage rate satisfies a threshold value related to the coverage rate, the layout extraction step of extracting a physical layout that is a determination target,
For the physical layout obtained in the layout extraction step, perform the steps after the correction / verification step,
In the covering ratio check step, when the information regarding the covering ratio does not satisfy the threshold regarding the covering ratio, the design apparatus performs the steps after the correction / verification step. A recording medium recording a design method of a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A contrast check step of calculating a contrast of the layout, referring to a threshold value regarding a contrast of an image on a semiconductor substrate of a layout obtained by arranging and wiring the cells, and comparing the calculation result of the contrast;
If the contrast calculation result in the contrast check step is less than or equal to a threshold value related to the contrast, the transfer information of the area where the contrast is less than the threshold value is acquired, the physical layout of the area is corrected, and the artwork processing is corrected. Process,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the physical layout subjected to the correction step;
A mask data creation step of creating mask data using the physical layout subjected to the correction / verification step;
In the contrast check step, if the calculation result of the contrast of the layout is larger than a threshold value related to the contrast, the threshold value related to the coverage ratio of the physical layout is referred to and compared with the information related to the coverage ratio of the extracted layout. Covering coverage check process,
In the coverage rate check step, when the information on the coverage rate satisfies a threshold value related to the coverage rate, the layout extraction step of extracting a physical layout that is a determination target,
For the physical layout obtained in the layout extraction step, perform the steps after the correction / verification step,
The recording medium, wherein, in the coverage check step, if the information regarding the coverage does not satisfy a threshold regarding the coverage, the steps after the correction / verification step are performed. In a mask manufacturing method manufactured using a semiconductor integrated circuit design method when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A contrast check step of calculating a contrast of the layout, referring to a threshold value regarding a contrast of an image on a semiconductor substrate of a layout obtained by arranging and wiring the cells, and comparing the calculation result of the contrast;
If the contrast calculation result in the contrast check step is less than or equal to a threshold value related to the contrast, the transfer information of the area where the contrast is less than the threshold value is acquired, the physical layout of the area is corrected, and the artwork processing is corrected. Process,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the physical layout subjected to the correction step;
A mask data creation step of creating mask data using the physical layout subjected to the correction / verification step;
In the contrast check step, if the calculation result of the contrast of the layout is larger than a threshold value related to the contrast, the threshold value related to the coverage ratio of the physical layout is referred to and compared with the information related to the coverage ratio of the extracted layout. Covering coverage check process,
In the coverage rate check step, when the information on the coverage rate satisfies a threshold value related to the coverage rate, the layout extraction step of extracting a physical layout that is a determination target,
For the physical layout obtained in the layout extraction step, perform the steps after the correction / verification step,
A method of manufacturing a mask for a semiconductor integrated circuit, comprising performing the steps after the correction / verification step when the information on the coverage does not satisfy a threshold on the coverage in the coverage check step. In a design apparatus for implementing a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying whether or not the second physical layout of the portion including the cell of the physical layout has a predetermined process margin with reference to a rule library for design rule check;
A correction determination step of determining whether to correct the second physical layout having a margin when there is a process margin in the design rule check step;
A mask data creation step of creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary when the correction determination step determines that the correction is unnecessary;
When it is determined in the correction determination step that correction is necessary, the second physical layout that is the determination target is proximity effect correction, a correction / verification step for verifying proximity effect correction,
Mask data creation step of creating mask data corresponding to the physical layout using the second physical layout that has been subjected to proximity effect correction and proximity effect correction verification in the correction / verification step;
When there is no process margin in the design rule check process, the correction / verification process for verifying the proximity effect correction and the proximity effect correction for the second physical layout to be verified;
A yield evaluation step of referring to a threshold related to the yield of the second physical layout and comparing it with information related to the yield of the second physical layout;
In the yield evaluation step, when the yield information satisfies the yield threshold, a second physical layout that is a determination target is extracted, and a rule for adding the second physical layout rule to the rule library is added Process,
When the yield information does not satisfy the yield threshold value in the yield evaluation step, the transfer information of the area where the yield is less than the threshold value is acquired, the second physical layout of the area is corrected, and the artwork processing A correction process to perform,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the second physical layout that has been subjected to the correction step;
And a mask data creation step of creating mask data using the second physical layout subjected to the correction / verification step. A recording medium recording a design method of a semiconductor integrated circuit when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying whether or not the second physical layout of the portion including the cell of the physical layout has a predetermined process margin with reference to a rule library for design rule check;
A correction determination step of determining whether to correct the second physical layout having a margin when there is a process margin in the design rule check step;
A mask data creation step of creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary when the correction determination step determines that the correction is unnecessary;
When it is determined in the correction determination step that correction is necessary, the second physical layout that is the determination target is proximity effect correction, a correction / verification step for verifying proximity effect correction,
Mask data creation step of creating mask data corresponding to the physical layout using the second physical layout that has been subjected to proximity effect correction and proximity effect correction verification in the correction / verification step;
When there is no process margin in the design rule check process, the correction / verification process for verifying the proximity effect correction and the proximity effect correction for the second physical layout to be verified;
A yield evaluation step of referring to a threshold related to the yield of the second physical layout and comparing it with information related to the yield of the second physical layout;
In the yield evaluation step, when the yield information satisfies the yield threshold, a second physical layout that is a determination target is extracted, and a rule for adding the second physical layout rule to the rule library is added Process,
When the yield information does not satisfy the yield threshold value in the yield evaluation step, the transfer information of the area where the yield is less than the threshold value is acquired, the second physical layout of the area is corrected, and the artwork processing A correction process to perform,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the second physical layout that has been subjected to the correction step;
And a mask data creation step of creating mask data using the second physical layout subjected to the correction / verification step. In a mask manufacturing method manufactured using a semiconductor integrated circuit design method when generating a physical layout of a semiconductor integrated circuit from semiconductor integrated circuit design data,
The semiconductor integrated circuit design method includes:
A cell placement and wiring step for placing and wiring cells for generating the physical layout;
A design rule check step for verifying whether or not the second physical layout of the portion including the cell of the physical layout has a predetermined process margin with reference to a rule library for design rule check;
A correction determination step of determining whether to correct the second physical layout having a margin when there is a process margin in the design rule check step;
A mask data creation step of creating mask data corresponding to the physical layout using the second physical layout determined to be unnecessary when the correction determination step determines that the correction is unnecessary;
When it is determined in the correction determination step that correction is necessary, the second physical layout that is the determination target is proximity effect correction, a correction / verification step for verifying proximity effect correction,
Mask data creation step of creating mask data corresponding to the physical layout using the second physical layout that has been subjected to proximity effect correction and proximity effect correction verification in the correction / verification step;
When there is no process margin in the design rule check process, the correction / verification process for verifying the proximity effect correction and the proximity effect correction for the second physical layout to be verified;
A yield evaluation step of referring to a threshold related to the yield of the second physical layout and comparing it with information related to the yield of the second physical layout;
In the yield evaluation step, when the yield information satisfies the yield threshold, a second physical layout that is a determination target is extracted, and a rule for adding the second physical layout rule to the rule library is added Process,
When the yield information does not satisfy the yield threshold value in the yield evaluation step, the transfer information of the area where the yield is less than the threshold value is acquired, the second physical layout of the area is corrected, and the artwork processing A correction process to perform,
A correction / verification step for performing proximity effect correction and proximity effect correction verification on the second physical layout that has been subjected to the correction step;
And a mask data creation step of creating mask data using the second physical layout subjected to the correction / verification step.

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