JP2007334563A - Vector processing device with mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vector processing device with a mask which can improve performance by shortening the TAT of executing a vector processing with a mask. <P>SOLUTION: The vector processing device with the mask comprises a vector register 100, vector processor 110, vector mask register 140, position calculator 4, and address converter 3. The vector register 100 stores vector data. The vector mask register 140 stores vector mask data which have mask bits for controlling processing by every element of the vector data. The position calculator 4 sequentially calculates positions where the effective mask bits appear. The address converter 3 converts the positions of the effective mask bits obtained by the position calculator 4 to the address of the vector register 100. The vector processor 110 executes processing of only the elements of the vector data corresponding to the effective mask bits. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a vector arithmetic processing device, and more particularly to a vector arithmetic processing device with a mask.

  In a vector processor, in order to improve the effective performance of an application program, it is necessary to use vector instructions as much as possible during compilation. Such vectorization is relatively easy in normal loop processing. However, in the loop processing with an IF statement, the processing content to be executed changes depending on the result of the IF statement processing, and therefore cannot be converted into a normal vector instruction. Therefore, in order to vectorize such a loop process with an IF statement, a vector operation instruction with a mask exists.

An example of the loop processing with IF statement is shown below. In such a loop statement processing, the execution result of “A (I) .LT.0” is set as a vector mask, and a vector with a mask of “U (I) = X (I) −Y (I)” After executing the operation, the vector mask is inverted, and a vector operation with a mask of “U (I) = X (I) + Y (I)” is executed, thereby enabling vectorization.
DO I = 1, N
IF (A (I) .LT.0) THEN
U (I) = X (I) -Y (I)
ELSE
U (I) = X (I) + Y (I)
CONTINUE

  FIG. 1 is a block diagram showing a configuration for executing a masked vector operation instruction. A vector operation instruction with a mask is generally executed and processed in such a configuration. The vector computing unit 710 reads the source operand from the vector registers VR # 0_700 and VR # 1_701 in which two source operands are stored. Then, the operation result is written back to the vector register VR # 2_702 that stores the destination operand. At this time, the read addresses of the vector registers VR # 0_700 and VR # 1_701 are specified by the value of the address register 720. The value of the address register 720 is counted up by the incrementer 730 every clock cycle. The write address of the vector register VR # 2_702 in which the operation result is stored is specified by the value of the address register 722. The value in the address register 722 is counted up by the incrementer 732 every clock cycle. As described above, the vector data of a plurality of elements stored in the vector registers (VR # 0_700, VR # 1_701) are sequentially read out to perform arithmetic processing for each element, and the operation result is stored in another vector register (VR # 2_702). You can write back every time.

  The vector mask register 740 stores a vector mask that is a bit string for identifying validity / invalidity for each element at the time of executing a vector operation process. The bit length of the vector mask is equal to the number of vector data elements in the vector operation process. The vector mask stored in the vector mask register 740 is taken out one bit at a time in order from the first bit by the parallel-serial converter 760 in synchronization with the calculation result of the vector calculator 710 being stored in the vector register VR # 2_702. The bit is supplied to a write control input (WE: Write Enable) of the vector register VR # 2_702. When the vector mask is a bit value indicating invalidity, when the address register 722 designates an address for writing back the operation result of the vector element corresponding to the entry, the write control input of the vector register VR # 2_702 designates write invalidity. To do. As a result, the calculation result of this vector element is not written into the vector register VR # 2_702. In this way, only the vector element of the bit value indicating that the vector mask is valid is written to the vector register VR # 2_702, and the other vector elements are masked by storing the original value of the vector register VR # 2_702. A vector operation instruction is executed.

  2 and 3 show a calculation TAT (Turn Around Time) for normal and masked vector calculation processing. FIG. 2 shows a case of a normal vector operation (corresponding to a vector mask being valid for all bits), and FIG. 3 shows a case of a vector operation with a mask. In FIG. 3, the case where the value of the vector mask is “0” is regarded as an invalid element, and the calculation for the element is represented by shading in the drawing. The TAT of the vector operation in FIG. 2 is the sum of the TAT of the arithmetic unit alone and the number of elements. On the other hand, the TAT of the masked vector operation of FIG. 3 is the sum of the TAT of the arithmetic unit alone and the number of elements, as in the case of FIG. This is because the operation itself is executed even when the vector mask is a bit value representing an invalid element, and the operation result is not written into the vector register. Therefore, if the number of vector elements is equal, the TAT of the vector operation becomes equal regardless of the presence or absence of the vector mask and the difference in the value of the vector mask.

By the way, recently, the loop description as shown below is increasing in the source program. When such a loop process is executed by a masked vector operation, the number of elements from the execution result of “A (I) .LT.0” to the element that satisfies the condition is counted, and the elements counted from the first bit are counted. Generate a vector mask that only makes the number valid. Then, a masked vector operation of “U (I) = X (I) + Y (I)” is executed. At this time, even if the number of valid elements from the first bit in the vector mask is very small (in the most extreme case, the condition may be satisfied at the first element and jump out of the loop may occur). Is equal to the TAT of the vector operation when all elements are valid.
DO I = 1, N
IF (A (I) .LT.0) THEN
GOTO <outside loop>
ELSE
U (I) = X (I) + Y (I)
CONTINUE

  Therefore, the masked vector calculation process for such a loop process has the following problems. The first problem is that conventional vector arithmetic processing devices with masks perform arithmetic processing on all elements even when there is little effective element data on the mask bits, so the arithmetic TAT cannot be shortened and it is difficult to improve performance. It is a thing. The second problem is that the arithmetic processing is performed even on the element data that is invalid on the mask bit, so that the power consumption for the arithmetic processing which is not originally necessary occurs. A technique capable of improving the performance by shortening the operation execution TAT in the vector operation processing with mask is desired. There is a demand for a technology that realizes low power consumption by avoiding unnecessary power consumption by not performing arithmetic processing on invalid element data.

  As a related technique, a vector mask calculation control unit is disclosed in Japanese Patent Application Laid-Open No. 62-276668. The vector mask arithmetic control unit includes a counting means, a generating means, and an address generating means in a data processing system that executes a masked vector instruction process decoded by a preceding control device. The counting means counts the number of consecutive operation suppression bits in the plurality of bits masking the vector operands one to one. The generating means generates one or two values of the address increment value multiplied by 2 using the value counted by the counting means. The address generating means adds the power-increment value of 2 raised from the generating means and the vector address to obtain the operand address.

  Japanese Patent Laid-Open No. 58-22446 discloses a vector mask arithmetic control system. This vector mask operation control method sequentially reads array operands and mask vectors, and controls the operation of corresponding operands according to the bit values of the mask vectors. Means for detecting that a certain number of operation suppression bits are continuous in the mask vector and means for updating storage addresses so as to skip over the operands and mask bits for the number are provided. When the suppression bit is detected, control is performed so as to skip reading of the corresponding operand and invalid operation.

  Japanese Patent Application Laid-Open No. 7-219928 discloses a vector data processing apparatus. This vector data processing apparatus has a vector register and a mask register having a mask bit corresponding to each element of vector data stored in the vector register. It has an interval counter, an interval buffer, a write address register, a mask read register, an interval buffer read counter, and a cumulative adder. When performing an operation with a mask, the interval counter reads a mask bit bit by bit from the mask register before executing the operation with a mask, and counts the bit interval between effective mask bits. The interval buffer stores the value of the interval counter when a valid mask bit appears. The write address register counts the number of valid mask bits and generates a write address for the interval buffer. The mask read register reads the mask register and generates an interval buffer write enable signal, an interval counter control signal, and an interval buffer write address control signal. The interval buffer read counter generates a read address of the interval buffer when the vector register is read in the masked operation. The cumulative adder sequentially accumulates and adds the mask effective bit intervals read from the interval buffer, and generates a read address of only vector data having mask bits valid among the vector data stored in the vector register.

JP-A-62-276668 JP 58-22446 A JP-A-7-219928

  An object of the present invention is to provide a masked vector arithmetic processing apparatus capable of improving the performance by shortening the arithmetic execution TAT in the masked vector arithmetic processing.

  Another object of the present invention is to perform a masked vector operation capable of reducing power consumption by avoiding unnecessary power consumption by not performing an operation process on invalid element data in a masked vector operation process. It is to provide a processing apparatus.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the best mode for carrying out the invention. These numbers and symbols are added with parentheses to clarify the correspondence between the description of the claims and the best mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

  In order to solve the above problems, a vector operation processing apparatus with a mask according to the present invention includes a vector register (100, 101, 102), a vector operation unit (110), a vector mask register (140), a position calculation unit ( 4) and an address conversion unit (3). The vector registers (100, 101, 102) store vector data. The vector mask register (140) stores vector mask data having mask bits for controlling the execution of each element of vector data. The position calculation unit (4) sequentially calculates the positions where the effective mask bits of the vector mask data appear when performing the vector operation. The address conversion unit (3) converts the effective mask bit position obtained by the position calculation unit (4) into the address of the vector register (100). The vector computing unit (110) performs vector computation only on the elements of the vector data for the effective mask bits of the vector mask data.

In the above-described vector arithmetic processing apparatus with a mask,
The position calculation unit (4) includes a zero count unit (160), a left shift unit (170), and a vector mask register output unit (150). The zero count unit (160) counts consecutive zero values from the first bit of the vector mask data. The left shift unit (170) shifts the bit string of the vector mask data to the left by a predetermined number of bits based on the result of the zero count unit (160). The vector mask register output unit (150) replaces the value of the vector mask data with the result of the left shift unit (170) and outputs the result to the zero count unit (160).

  In the above-described vector calculation processing apparatus with mask, the position calculation unit (4) repeatedly executes the processes performed by the zero count unit (160), the left shift unit (170), and the vector mask register output unit (150) a predetermined number of times. .

  The vector processing apparatus with a mask described above further includes a coincidence detection unit (190) that detects that the result of the zero count unit (160) matches the number of elements of the vector data. When the coincidence detection unit (190) detects a coincidence, the repetition is finished and the execution of the vector operation is completed.

  In the masked vector arithmetic processing apparatus, the address conversion unit (3) includes adders (130, 132) for adding the current address value and the result of the zero count unit (160).

  The masked vector operation processing apparatus further includes a completion timing output unit (2) that outputs a vector operation execution completion timing in advance based on a count result of the number of effective mask bits of the vector mask data.

In the above-described vector arithmetic processing apparatus with a mask,
The completion timing output unit (2) includes a counting unit (570) for counting, a count value holding unit (580), and a completion determining unit (590). The count unit (570) counts the number of effective mask bits of the vector mask data. The count value holding unit (580) holds the count result of the count unit (570). The completion determination unit (590) reads the count result of the number of valid mask bits when executing the vector operation and outputs the execution completion timing of the vector operation in advance.

  In order to solve the above-described problems, the present invention is an operation method of the following vector arithmetic processing apparatus with a mask. Here, the masked vector operation processing apparatus has a vector register (100, 101, 102) for storing vector data, a vector operation unit (110), and a mask bit for controlling the execution of each element of the vector data. A vector mask register (140) for storing vector mask data, a position calculation unit (4), and an address conversion unit (3) are provided. The operation method of the vector operation processing apparatus with a mask includes the steps of: (a) a vector mask register (140) storing vector mask data having a mask bit corresponding to each element of vector data when executing a vector operation; ) A step in which the position calculation unit (4) sequentially calculates the positions where the effective mask bits of the vector mask data appear; and (c) the effective mask obtained by the address conversion unit (3) by the position calculation unit (4). Converting a bit position into an address of the vector register (100); and (d) a vector operator (110) performing a vector operation only on an element of the vector data with respect to an effective mask bit of the vector mask data. To do.

  In the operation method of the vector arithmetic processing apparatus with a mask, the position calculation unit (4) includes a zero count unit (160), a left shift unit (170), and a vector mask register output unit (150). The (b) step includes (b1) a step in which the zero count unit (160) counts a continuous zero value from the first bit of the vector mask data, and (b2) the left shift unit (170) performs a zero count unit (160 And (b3) the vector mask register output unit (150) converts the value of the vector mask data to the result of the left shift unit (170) based on the result of And outputting to the zero count unit (160).

  In the above-described operation method of the vector arithmetic processing apparatus with a mask, the vector arithmetic processing apparatus with a mask further includes a coincidence detection unit (190). (E) a step in which the match detection unit (190) detects a match between the result of the zero count unit (160) and the number of elements of the vector data; and (f) when the match detection unit (190) detects a match, And a step of ending the iteration and completing the execution of the vector operation.

  According to the present invention, it is possible to improve the performance by shortening the operation execution TAT in the masked vector operation processing. In addition, by not performing arithmetic processing on invalid element data, unnecessary power consumption can be avoided and low power consumption can be realized.

(First embodiment)
A first embodiment of a vector arithmetic processing apparatus with a mask according to the present invention will be described below with reference to the accompanying drawings. FIG. 4 is a block diagram showing an example of the configuration of the first embodiment of the vector arithmetic processing apparatus with mask according to the present invention. The vector operation processing apparatus 1 with mask includes a vector operation unit 110, vector registers VR # 0_100, VR # 1_101, vector register VR # 2_102, address register 120, address adder 130, address register 122, write address adder 132, vector A mask register 140, a selection circuit 150, a Leading Zero circuit 160 (hereinafter abbreviated as “LDZ circuit 160”), a left shift circuit 170, a temporary save register 180, and a comparator 190 are provided.

The vector registers VR # 0_100 and VR # 1_101 store source operands, respectively. The vector register VR # 2_102 stores the destination operand. The vector calculator 110 reads two source operands from the vector registers VR # 0_100 and VR # 1_101. Then, the operation result is written back to the vector register VR # 2_102. The address register 120 stores a value for designating read addresses of the vector registers VR # 0_100 and VR # 1_101 when the vector computing unit 110 reads two source operands. The read address adder 130 updates the value of the address register 120 every clock cycle. The address register 122 stores a value that specifies the write address of the vector register VR # 2_102 in which the operation result is stored. The write address adder 132 updates the value of the address register 122 every clock cycle.

  The vector mask register 140 stores a vector mask that is a bit string for identifying validity / invalidity for each element at the time of vector operation processing. The bit length of the vector mask is equal to the number of vector data elements in the vector operation process. The vector mask register 140 outputs the value (vector mask) of the vector mask register 140 to the selection circuit 150. The selection circuit 150 selects the output of the vector mask register 140 immediately after the start of the operation, selects the output of the temporary save register 180 thereafter, and outputs it to the LDZ circuit 160 and the left shift circuit 170. The LDZ circuit 160 calculates the number of bits in which the logical value zero continues from the beginning of the input bit string (hereinafter abbreviated as “zero value continuous numerical value”). The LDZ circuit 160 outputs the zero value continuous numerical value to the read address adder 130 and the write address adder 132 described above.

  The read address adder 130 is supplied with the continuous zero value of the LDZ circuit 160 as one input and the value of the current read address register 120 as the other input. The read address adder 130 always adds the carry input as “+1”. Thereby, when the output of the LDZ circuit 160 has a zero value, the read address adder 130 operates as an incrementer. That is, the read address adder 130 counts up the read address register 120 every clock cycle. When the output of the LDZ circuit 160 is other than a zero value, the read address adder 130 adds the value of the continuous zero value + 1 from the head in the input bit string of the LDZ circuit 160 to the current read address register 120.

  Similarly, the write address adder 132 is supplied with the continuous zero value of the LDZ circuit 160 as one input and the value of the current write address register 122 as the other input. The write address adder 132 always adds the carry input as “+1”. Thereby, when the output of the LDZ circuit 160 has a zero value, the write address adder 132 operates as an incrementer. That is, the write address register 122 is counted up every clock cycle. When the output of the LDZ circuit 160 is other than a zero value, the write address adder 132 adds the value of the zero value continuation number + 1 from the head in the input bit string of the LDZ circuit 160 to the current write address register 122.

  On the other hand, the LDZ circuit 160 further outputs a zero value continuous numerical value to the left shift circuit 170. The left shift circuit 170 shifts the input data output from the selection circuit 150 to the left by the output value (zero value continuous numerical value) +1 of the LDZ circuit 160. At this time, the left shift circuit 170 always shifts one bit to the left even when the output of the LDZ circuit 160 has a zero value. The left shift circuit 170 outputs the left shifted value to the temporary save register 180. The temporary save register 180 feeds back the value to the selection circuit 150.

  The LDZ circuit 160 further outputs a zero value continuous numerical value to the comparator 190. The comparator 190 compares the continuous zero value with the bit length (VL) of the vector mask register 140, that is, the number of operation elements of the vector operation. Here, the case where the zero value continuous numerical value that is the output of the LDZ circuit 160 matches the number of vector operation elements indicates that all the bit strings that are input to the LDZ circuit 160 have zero values. This means that there is no valid element data. Therefore, execution of the masked vector operation is finished when the comparator 190 outputs a coincidence. In this case, the completion of the operation execution is notified to a vector operation instruction control unit (not shown).

  When the bit value “1” is a bit value representing a valid element in the vector mask bit string, the vector element processing operand with mask 1 stores the source operand of the vector element corresponding to the entry. Only the read addresses of the vector registers VR # 0_100 and VR # 1_101 can be designated continuously every clock cycle. In addition, only the write address of the vector register VR # 2_102 that stores the destination operand of the vector element corresponding to the entry can be continuously specified every clock cycle. As a result, it is possible to realize a desired logical function of executing a vector operation only for effective elements of the vector mask.

  In the present invention, the read address adder 130, the write address adder 132, the LDZ circuit 160, the left shift circuit 170, and the comparator 190 are not limited to the configuration shown in FIG. That is, any configuration that realizes a function equivalent to a combination of these configurations may be used.

  For example, in FIG. 4, the read address register 120, the write address register 122, the read address adder 130, and the write address adder 132 are provided independently. Here, the value of the write address register 122 becomes the same value as the value of the read address register 120 after the number of clock cycles necessary for the operation has elapsed in the vector computing unit 110 after the value of the read address register 120 is obtained. . Accordingly, the write address adder 132 may not be provided, and the read address register 120 may be input to the write address register 122 after being delayed by a plurality of clocks.

  Next, the operation of the first embodiment of the masked vector arithmetic processing apparatus will be described. FIG. 5 is a timing chart showing the operation of the first embodiment of the masked vector operation processing apparatus. The leftmost vertical column indicates the cycle (time). The central vertical column shows the address values of the read address register 120 and the write address register 122. The rightmost vertical column shows the output of the selection circuit 150.

  Here, “1100111000001101” described as “at the start of execution” is taken as an example of a vector mask value, and an operation when such a vector mask value is set will be described. Here, the vector mask value is 16 bits wide. This number of bits corresponds to the number of elements (number of vector elements) in one vector operation. That is, the number of elements of the vector operation in this example is “16”. If the bit value “1” is a valid vector element in the vector mask value, the number of valid vector elements is 8 in the example of the vector mask value shown in FIG. The initial values of the read address register 120 and the write address register 122 are both “−1”.

  The LDZ circuit 160 outputs a zero value “0” from the vector mask value “at the start of execution” because the first bit of the vector mask value is the bit value “1” and the number of “0” is zero. . The adders 130 and 132 add the zero value “0” and “+1” to the initial address value “−1” (= “− 1” + “0” + “+ 1” = “0”). Is output as the address value of the next cycle. Therefore, the address value of the vector register (VR # 0_100, VR # 1_101, VR # 2_102) in the next cycle “1T” is “0”. Also, the vector mask value is shifted to the left by the left shift circuit 170 by the output value of the LDZ circuit 160 plus one bit (= “0” + 1 = 1 bit), and becomes the input to the LDZ circuit 160 in the next cycle. . Accordingly, the selection circuit 150 outputs the bit string “1001110000011010” to the LDZ circuit 160 in the cycle “1T”.

  From the vector mask value of the cycle “1T”, the LDZ circuit 160 outputs a zero value “0” because the first bit is the bit value “1”. The adders 130 and 132 add the zero value “0” and “+1” to the address value “0” in the previous cycle (= “0” + “0” + “+ 1” = “1”). ) Is output as the address value of the next cycle. Therefore, the address value of the vector register in the next cycle “2T” is “1”. Also, the vector mask value is shifted to the left by the left shift circuit 170 by the output value of the LDZ circuit 160 plus one bit (= “0” + 1 = 1 bit), and becomes the input to the LDZ circuit 160 in the next cycle. . Therefore, the selection circuit 150 outputs the bit string “0011100000110100” to the LDZ circuit 160 in the cycle “2T”.

  From the vector mask value of the cycle “2T”, the LDZ circuit 160 outputs “2” because the bit value “0” continues for 2 bits from the first bit. The adders 130 and 132 add the values “2” and “+1” to the address value “1” in the previous cycle (= “1” + “2” + “+ 1” = “4”). Is output as the address value of the next cycle. Accordingly, the address value of the vector register in the next cycle “3T” is “4”. Also, the vector mask value is shifted to the left by the output value + 1 bit (= “2” + 1 = 3 bits) of the LDZ circuit 160 and becomes an input to the LDZ circuit 160 in the next cycle. Therefore, the selection circuit 150 becomes the bit string “110000010100000” to the LDZ circuit 160 in the cycle “3T”.

  From the vector mask value of the cycle “3T”, the LDZ circuit 160 outputs a zero value “0” because the first bit is the bit value “1”. The adders 130 and 132 add the values “0” and “+1” to the address value “4” in the previous cycle (= “4” + “0” + “+ 1” = “5”) Is output as the address value of the next cycle. Therefore, the address value of the vector register in the next cycle “4T” is “5”. Also, the output value of the LDZ circuit 160 plus one bit (= “0” + 1 = 1 bit), the vector mask value is shifted left by the left shift circuit 170 and becomes the input to the LDZ circuit 160 in the next cycle. Therefore, the selection circuit 150 outputs the bit string “1000001101000000” to the LDZ circuit 160 in the cycle “4T”.

  From the vector mask value of cycle “4T”, the LDZ circuit 160 outputs a zero value “0” because the first bit is the bit value “1”. The adders 130 and 132 add the values “0” and “+1” to the address value “5” in the previous cycle (= “5” + “0” + “+ 1” = “6”) Is output as the address value of the next cycle. Accordingly, the address value of the vector register in the next cycle “5T” is “6”. Also, the output value of the LDZ circuit 160 plus one bit (= “0” + 1 = 1 bit), the vector mask value is shifted left by the left shift circuit 170 and becomes the input to the LDZ circuit 160 in the next cycle. Therefore, the selection circuit 150 outputs the bit string “0000011010000000000” to the LDZ circuit 160 in the cycle “5T”.

  From the vector mask value of the cycle “5T”, the LDZ circuit 160 outputs “5” because the bit value “0” continues for 5 bits from the first bit. The adders 130 and 132 add the value “5” and “+1” to the address value “6” in the previous cycle (= “6” + “5” + “+ 1” = “12”) Is output as the address value of the next cycle. Therefore, the address value of the vector register in the next cycle “6T” is “12”. Further, the output value of the LDZ circuit 160 plus one bit (= “5” + 1 = 6 bits) is shifted to the left by the left shift circuit 170 and becomes the input to the LDZ circuit 160 in the next cycle. Therefore, the selection circuit 150 outputs the bit string “1010000000000000” to the LDZ circuit 160 in the cycle “6T”.

  From the vector mask value of the cycle “6T”, the LDZ circuit 160 outputs a zero value “0” because the first bit is the bit value “1”. The adders 130 and 132 add the values “0” and “+1” to the address value “12” in the previous cycle (= “12” + “0” + “+ 1” = “13”) Is output as the address value of the next cycle. Accordingly, the address value of the vector register in the next cycle “7T” is “13”. Also, the output value of the LDZ circuit 160 plus one bit (= “0” + 1 = 1 bit), the vector mask value is shifted left by the left shift circuit 170 and becomes the input to the LDZ circuit 160 in the next cycle. Accordingly, the selection circuit 150 outputs the bit string “0100000000000000000” to the LDZ circuit 160 in the cycle “7T”.

  From the vector mask value of the cycle “7T”, the LDZ circuit 160 outputs “1” because the bit value “0” continues for one bit from the first bit. The adders 130 and 132 add a value (= “13” + “1” + “+ 1” = “15”) obtained by adding the values “1” and “+1” to the address value “13” in the previous cycle. And output as the address value of the next cycle. Therefore, the address value of the vector register in the next cycle “8T” is “15”. Also, the output value of the LDZ circuit 160 plus one bit (= “1” + 1 = 2 bits), the vector mask value is left-shifted by the left shift circuit 170 and becomes an input to the LDZ circuit 160 in the next cycle. Therefore, the selection circuit 150 outputs the bit string “0000000000000000000” to the LDZ circuit 160 in the cycle “8T”.

  From the vector mask value of the cycle “8T”, the LDZ circuit 160 outputs “16” because the bit value “0” continues for 16 bits from the first bit. At this time, since the output “16” of the LDZ circuit 160 and the number of elements of vector calculation “16” match, the comparator 190 sends a signal indicating that both match to a vector calculation command controller (not shown). ). Thereby, the vector operation instruction control unit ends the execution of the masked vector operation.

  From the above description regarding the timing chart, it can be seen that the vector operation apparatus with mask of the present invention can continuously execute operations only on valid vector elements in the bit string of the vector mask. In the vector mask value of FIG. 5 shown as an example, the number of elements of the vector operation is “16”, and the number of valid vector elements is “8”. At this time, the vector operation apparatus with mask of the present invention executes the vector operation processing with mask until 7 clock cycles after the start of execution, and determines the end of execution of the vector operation with mask after 8 clock cycles. Can do.

  6 and 7 show calculation TATs for normal and masked vector calculation processing using the masked vector calculation apparatus of the present invention. FIG. 6 shows a TAT for a normal vector calculation process, and FIG. 7 shows a TAT for a vector calculation process with a mask. In the normal vector operation processing of FIG. 6, all bits indicating that the vector mask value is valid for all elements are synonymous with the bit value “1”. Therefore, the arithmetic processing TAT is the sum of the TAT of the arithmetic unit alone and the number of elements. On the other hand, in the vector calculation process with a mask in FIG. Therefore, the shortened arithmetic processing TAT is the sum of the TAT of the arithmetic unit alone and the number of effective elements of the vector mask. The smaller the number of effective vector elements in the vector mask, the shorter the calculation processing TAT of the vector calculation processing with mask in the present invention.

  As described above, according to the present invention, in execution of a masked vector operation, a leading ZERO circuit 160 (a circuit that outputs the number of consecutive 0s from the beginning of a bit string) to the mask register 140 and each source / destination register Adders 130 and 132 for calculating read / write addresses for the ZERO, the output values of the Leading ZERO circuit 160 are accumulated by the adders 130 and 132, and the source / destination vector registers (VR # 0_100, VR # 1_101, VR # 2_102) is updated every cycle. At the same time, the mask register value (vector mask) is updated every cycle by shifting itself to the left by the left shift circuit 170 according to the output result of the Leading ZERO circuit 160. As a result, the read / write addresses for the source / destination registers where the element data corresponding to the valid bits of the mask register value exist can be accessed continuously. As a result, when the output result of the leading ZERO circuit 160 for the mask register value matches the vector length (the mask register value becomes All “0” data), the execution of the vector operation instruction is completed.

  That is, the present invention has the following effects. The first effect is that, in the vector calculation process with mask, only the operation for the element data effective on the mask bit is continuously executed, so that the TAT of the vector calculation process with mask can be shortened and the performance improvement can be realized. is there.

  The second effect is that, in the masked vector operation processing, the operation for the invalid element data on the mask bit is not executed, thereby avoiding unnecessary power consumption and reducing the power consumption of the masked vector operation processing device. It can be realized.

(Second Embodiment)
Hereinafter, a second embodiment of the masked vector arithmetic processing apparatus of the present invention will be described with reference to the accompanying drawings.

  The masked vector arithmetic processing apparatus 1 according to the second embodiment adds a new component (arithmetic unit busy time notifying unit 2) to be described later to the masked vector arithmetic processing apparatus 1 shown in FIG. This is different from the first embodiment.

  FIG. 8 and FIG. 9 show the respective computation TATs of the conventional masked vector arithmetic processing apparatus and the masked vector arithmetic processing apparatus 1 of the present invention. FIG. 8 shows a TAT in the case of executing a vector operation instruction using the same vector operation unit after executing a masked vector operation instruction once in the conventional masked vector operation processing apparatus. FIG. 9 shows a TAT in the case of executing a vector operation instruction using the same vector operation unit after executing a masked vector operation instruction once in the masked vector operation processing apparatus 1 according to the present invention. . In FIG. 8, in the conventional masked vector arithmetic processing apparatus, it is known that the sum of the TAT of the arithmetic unit alone and the number of elements is the arithmetic TAT necessary for execution regardless of the value of the vector mask. This period is a period during which the corresponding vector calculator is processing execution of an operation instruction. Therefore, it is not possible to process other arithmetic instructions that use the same vector arithmetic unit. Therefore, this operation TAT is called the busy time of the vector operation unit. If the Busy time of this vector calculator is known in advance, it is possible to easily determine when to start execution when executing a vector calculation instruction using the same vector calculator. . In the conventional vector arithmetic processing unit with mask, the issuance control unit of the vector arithmetic instruction determines the busy time of the vector arithmetic unit when the execution of the preceding masked vector arithmetic instruction is started. For this reason, it is possible to easily realize control for executing subsequent vector operation instructions continuously without any gaps. On the other hand, in the masked vector operation processing apparatus of the present invention shown in FIG. 9, the vector operation unit does not complete the operation processing of the last valid vector element of the vector mask by executing the preceding masked vector operation instruction during the busy time. Not known. For this reason, it is very difficult to control the subsequent vector operation instructions to be executed continuously without a gap.

  Therefore, in this embodiment, a new component is added to the masked vector arithmetic processing apparatus 1 (FIG. 4) described in the first embodiment. Thereby, the new component has a function capable of determining in advance the vector calculation busy time of the masked vector calculation processing apparatus according to the present invention. By adding such a new component, in the vector operation instruction issuance control unit (not shown) in the vector operation instruction control unit (not shown), subsequent vector operation instructions can be sent without any gaps. It is possible to easily realize control that is continuously executed.

  FIG. 4 is a block diagram showing the configuration of the second embodiment of the vector arithmetic processing apparatus with a mask according to the present invention, but since it is the same as that of the first embodiment, its description is omitted.

  FIG. 10 is a block diagram illustrating an example of a configuration related to a vector mask register in the vector arithmetic processing apparatus with a mask. Here, the configuration related to the vector mask register is the arithmetic unit busy time notification unit 2. That is, the masked vector calculation processing apparatus 1 includes a calculator busy time notification unit 2 shown in FIG. 10 in addition to the configuration of FIG.

  The arithmetic unit Busy time notification unit 2 includes a first selection circuit 520, a second selection circuit 530, a temporary save register file 500, a vector mask calculation unit 511, a vector mask generation calculation unit 510, a third selection circuit 550, a buffer 580, A fourth selection circuit 560, a population counter 570 (hereinafter referred to as a POP counter), and a fifth selection circuit 590 are provided. However, in this figure, the vector mask register 540 is the same as the vector mask register 140 in FIG.

  The third selection circuit 550 is one of an output of the vector mask register 540, a newly generated vector mask which is an output of the first selection circuit 520, and a bit string transferred from the scalar register existing outside FIG. Is output to the temporary save register file 500 as a vector mask composed of a plurality of entries. The temporary save register file 500 temporarily saves a vector mask composed of a plurality of entries. Then, the data is output to the vector mask calculator 511 and the second selection circuit 530. The vector mask generation calculator 510 generates a vector mask by condition determination processing according to the values of the vector registers (VR # 0_100, VR # 1_101, VR # 2_102). Then, the data is output to the first selection circuit 520. The vector mask calculator 511 performs a logical operation on any two entries of the temporary save register file (vector mask) to generate a new vector mask. Then, the data is output to the first selection circuit 520. The first selection circuit 520 selects one of the output of the vector mask calculator 511 and the output of the vector mask generation calculator 510 as a newly generated vector mask. Then, the data is output to the second selection circuit 530. The second selection circuit 530 selects one of the output of the first selection circuit 520 and the output of the vector mask register 540. Then, the data is output to the vector mask register 540.

  That is, the vector mask register 540 includes a vector mask stored in the temporary save register file 500, a vector mask newly generated by the vector mask calculator 511, and a vector mask newly generated by the vector mask generation calculator 510. Is selected and set.

  The temporary save register file 500 preferably has an entry number (word number) of 16 or more. Further, the output of the temporary save register file 500 may be transferred to a scalar register existing outside of FIG.

  The above is a general configuration example around the vector mask register 540. However, the present invention further includes a buffer 580, a fourth selection circuit 560, a POP counter 570, and a fifth selection circuit 590 as other new components.

  The fourth selection circuit 560 selects one of the output of the first selection circuit 520 and the output of the vector mask register 540 in parallel with the second selection circuit 530. Then, the data is output to the POP counter 570. The POP counter 570 receives the output of the fourth selection circuit 560 and counts the number of bits having the bit value “1” included in the bit string. Then, the data is output to the buffer 580 and the fifth selection circuit 590. The buffer 580 stores information corresponding to each entry of the temporary save register file 500. The output result of the POP counter 570 is stored. The fifth selection circuit 590 selects either the output of the buffer 580 or the output of the POP counter 570. And it outputs to a vector operation command control part.

  In the present embodiment, by the newly added components (buffer 580, fourth selection circuit 560, POP counter 570, and fifth selection circuit 590), the vector mask calculator 511 and the vector mask generation calculator 510 When a new vector mask is generated and stored in a specific entry of the temporary save register file 500, the number of bit values “1” of the vector mask generated by the POP counter 570, that is, the number of valid elements is counted. , Stored in the same entry of the buffer 580. When the newly generated vector mask described above is set in the vector mask register 540 as it is, the output result of the POP counter 570 is directly used as a vector operation existing outside of FIG. 10 via the fifth selection circuit 590. Notify the instruction vector operation instruction control unit. Alternatively, when the value read from the temporary save register file 500 is set in the vector mask register 540, if the POP count value exists in the corresponding entry of the buffer 580, the value is sent via the fifth selection circuit 590. , Notify the vector operation instruction control unit of the vector operation instruction existing outside of FIG. Alternatively, when the value read from the temporary save register file 500 is set in the vector mask register 540, if there is no POP count value in the corresponding entry of the buffer 580, the fourth selection circuit 560 causes the temporary save register The vector mask transferred from the register file 500 to the vector mask register 540 is input to the POP counter 570, and the output result is controlled via the fifth selection circuit 590 to the vector operation instruction of the vector operation instruction existing outside FIG. Notify the department. Thus, the vector operation instruction control unit can determine the busy time of the vector operation unit for the masked vector operation using the vector mask register 540 at the “start of execution”. As a result, when there is a subsequent vector operation instruction using the same vector operation unit, it is possible to realize control that is executed continuously without a gap.

  The operation on the main body side of the masked vector arithmetic processing apparatus 1 in FIG. 4 is the same as that in the first embodiment, and a description thereof will be omitted.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained. In addition, it is possible to perform control such that subsequent vector operation instructions are continuously executed without a gap.

  In the first and second embodiments, the case of a single vector operation processing pipeline configuration has been described. However, the present invention can be similarly executed in the case of a multi-vector pipeline in which vector elements are interleaved by a plurality of vector arithmetic processing pipelines to perform parallel execution processing. This will be described below.

  FIG. 11 shows an operation when the vector operation processing with mask of the present invention has a multi-vector pipeline configuration. Here, a case where four vector pipelines are arranged in parallel is illustrated. In the multi-vector pipeline configuration, since vector elements are interleaved and assigned to each vector pipeline, the busy time of the vector calculator varies for each vector pipeline due to the bits of the effective elements of the vector mask. Therefore, when only the arithmetic unit busy time notification unit 2 shown in FIG. 10 is provided for each vector pipeline, subsequent vector operation instructions are started to be executed separately for each vector pipeline. In the multi-vector pipeline configuration, it is very difficult to control the execution start timing of one vector operation instruction independently for each vector pipeline. Therefore, in such a case, the second arithmetic unit having a function of collecting the arithmetic unit busy time for each vector pipeline, obtaining the maximum value thereof, and setting the value as the arithmetic unit busy time for the corresponding masked vector arithmetic instruction. A Busy time notification unit may be additionally provided. The vector operation instruction control unit controls the execution start timing of the subsequent vector operation instruction based on the output of the second arithmetic unit Busy time notification unit, thereby applying the present invention to the multi-vector pipeline configuration. can do.

  In the present invention, regarding execution of a vector operation with a mask, it is possible to realize a performance improvement by shortening the operation execution TAT and a reduction in power consumption by avoiding an operation execution process for invalid element data.

FIG. 1 is a block diagram showing a configuration for executing a masked vector operation instruction. FIG. 2 shows an operation TAT of normal vector operation processing. FIG. 3 shows an operation TAT of the masked vector operation process. FIG. 4 is a block diagram showing an example of the configuration of the first embodiment of the vector arithmetic processing apparatus with mask according to the present invention. FIG. 5 is a timing chart showing the operation of the first embodiment of the masked vector operation processing apparatus of the present invention. FIG. 6 shows an operation TAT of normal vector operation processing using the masked vector operation device of the present invention. FIG. 7 shows a calculation TAT of a masked vector calculation process using the masked vector calculation apparatus of the present invention. FIG. 8 shows a calculation TAT of a conventional vector calculation processing apparatus with a mask. FIG. 9 shows an operation TAT of the vector operation processing apparatus with mask of the present invention. FIG. 10 is a block diagram illustrating an example of a configuration related to a vector mask register in the vector arithmetic processing apparatus with a mask. FIG. 11 shows an operation when the vector operation processing with mask of the present invention has a multi-vector pipeline configuration.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Vector operation processing apparatus with a mask 2 Operation unit Busy time notification part 110 Vector operation unit 100 Vector register VR # 0
101 Vector register VR # 1
102 Vector register VR # 2
DESCRIPTION OF SYMBOLS 120 Address register 130 Address adder 122 Address register 132 Write address adder 140 Vector mask register 150 Selection circuit 160 Leading Zero circuit (LDZ circuit)
170 Left shift circuit 180 Temporary save register 190 Comparator 520 First selection circuit 500 Temporary save register file 510 Vector mask generation calculator 511 Vector mask calculator 530 Second selection circuit 540 Vector mask register 550 Third selection circuit 560 Fourth Selection circuit 570 Population counter (POP counter)
580 Buffer 590 Fifth selection circuit 710 Vector computing unit 700 Vector register VR # 0
701 Vector register VR # 1
702 Vector register VR # 2
710 Vector calculator 720 Address register 722 Address register 730 Incrementer 732 Incrementer 740 Vector mask register 760 Parallel-serial converter

Claims (10)

A vector register for storing vector data;
A vector operator,
A vector mask register for storing vector mask data having a mask bit for controlling execution of each element of the vector data;
A position calculation unit that sequentially calculates the position where the effective mask bits of the vector mask data appear when performing a vector operation;
An address conversion unit that converts an effective mask bit position obtained by the position calculation unit into an address of the vector register; and
The vector computing unit performs a vector computation only on an element of the vector data with respect to an effective mask bit of the vector mask data. In the vector arithmetic processing apparatus with a mask according to claim 1,
The position calculation unit
A zero count unit that counts consecutive zero values from the first bit of the vector mask data;
A left shift unit that shifts the bit string of the vector mask data to the left by a predetermined number of bits based on the result of the zero count unit;
A vector arithmetic processing apparatus with a mask, comprising: a vector mask register output unit that replaces the value of the vector mask data with the result of the left shift unit and outputs the result to the zero count unit. In the vector arithmetic processing apparatus with a mask according to claim 2,
The position calculation unit repeats a process performed by the zero count unit, the left shift unit, and the vector mask register output unit a predetermined number of times. In the vector arithmetic processing apparatus with a mask according to claim 3,
Further comprising a coincidence detection unit for detecting that the result of the zero count unit coincides with the number of elements of the vector data;
A masked vector operation processing apparatus that ends the repetition and completes the execution of the vector operation when the match detection unit detects a match. In the vector arithmetic processing apparatus with a mask according to claim 2,
The said address conversion part is provided with the adder which adds the present address value and the result of the said zero count part, The vector arithmetic processing apparatus with a mask. In the vector arithmetic processing unit with a mask according to any one of claims 1 to 5,
A masked vector operation processing apparatus, further comprising: a completion timing output unit that outputs the execution timing of the vector operation in advance based on a count result of the number of effective mask bits of the vector mask data. In the vector arithmetic processing apparatus with a mask according to claim 6,
The completion timing output unit
A count unit that counts the number of effective mask bits of the vector mask data;
A count value holding unit for holding the count result of the counting unit;
A masked vector operation processing apparatus, comprising: a completion determination unit that reads out the count result of the number of effective mask bits when executing the vector operation and outputs the execution completion timing of the vector operation in advance. An operation method of a vector arithmetic processing apparatus with a mask,
Here, the vector arithmetic processing apparatus with mask is
A vector register for storing vector data;
A vector operator,
A vector mask register for storing vector mask data having a mask bit corresponding to each element of the vector data;
A position calculation unit;
An address translation unit, and
The operation method of the vector arithmetic processing apparatus with a mask is as follows.
(A) the vector mask register storing vector mask data having a mask bit for controlling execution of an operation for each element of the vector data;
(B) the position calculating unit sequentially calculating the position where the effective mask bit of the vector mask data appears;
(C) the address conversion unit converting the effective mask bit position obtained by the position calculation unit into an address of the vector register;
(D) The vector computing unit includes a step of executing a vector computation only on an element of the vector data with respect to an effective mask bit of the vector mask data. In the operation method of the vector arithmetic processing unit with a mask according to claim 8,
The position calculation unit
A zero count section;
A left shift part,
A vector mask register output section, and
The step (b)
(B1) the zero counting unit counting consecutive zero values from the first bit of the vector mask data;
(B2) the left shift unit shifts the bit string of the vector mask data to the left by a predetermined number of bits based on the result of the zero count unit;
(B3) The vector mask register output unit includes a step of replacing the value of the vector mask data with the result of the left shift unit and outputting the result to the zero count unit. In the operation method of the vector arithmetic processing unit with a mask according to claim 9,
The vector calculation processing apparatus with a mask further includes a coincidence detection unit,
(E) a coincidence detection unit detecting a coincidence between the result of the zero count unit and the number of elements of the vector data;
(F) A method of operating a masked vector operation processing device, further comprising: when the match detection unit detects a match, ending the repetition and completing the execution of the vector operation.

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