JP2007250907A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method therefor, which facilitate improvement in SIV (Stress Induced Voiding) resistance. <P>SOLUTION: The semiconductor device has a multilayer copper wire 55 on a semiconductor board 10 with circuit elements 20 and 30 formed thereon. In manufacturing the semiconductor device, the maximum hydrogen content at damascene copper wires, contact plugs, and barrier metal layers in each of inter-layer insulating films 35, 40, 45, and 50 composing the multilayer copper wire portion 55 is controlled depending on the ratio between the number of first damascene copper wires 48b that are connected to damascene copper wires 43b wider than the first damascene copper wires 48b via contact plugs formed in the inter-layer insulating film, and the number of second damascene copper wires 48c that are connected to damascene copper wires 43c wider than the second damascene copper wires 48c, except that the inter-layer insulating film 35 that is the lowermost layer in the multilayer copper wire portion 55 is excluded from the subjects of the control. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having damascene copper wiring and a method for manufacturing the same. The “damascene copper wiring” in the present invention means a copper wiring formed so as to fill a trench (groove) provided in an interlayer insulating film.

  Nowadays, in order to reduce the size and performance of electronic devices, a large number of circuit elements are formed on one semiconductor substrate, and the wirings that constitute the summing circuit together with these circuit elements are formed in multiple layers on the semiconductor substrate. Semiconductor devices formed in this way are often used. The integration density of circuit elements in such a semiconductor device is steadily increasing. With the high integration of circuit elements, the performance and miniaturization of individual circuit elements and the miniaturization of wiring have been achieved. ing. In order to form a fine and low electrical resistance wiring, a material having high conductivity such as copper and aluminum has been widely used as a wiring material, and the forming method is also formed on an interlayer insulating film. The method of patterning the conductive film into a predetermined shape has changed to the damascene method.

  The damascene method can be divided into a single damascene method and a dual damascene method. In either method, a wiring is formed by filling a trench formed in an interlayer insulating film with a conductive material. In the single damascene method, the embedding of the conductive material in the via hole and the embedding of the conductive material in the trench are performed in separate processes, and in the dual damascene method, the embedding of the conductive material in the via hole and the conductivity in the trench are performed. The material embedding is performed in the same process.

  Regardless of which method is used to form the contact plug and wiring, prior to the formation of the contact plug and wiring, a barrier metal layer for preventing the conductive material from diffusing into the interlayer insulating film is formed on the wall surface of the via hole, It is provided so as to cover the wall surface of the trench and the surface of the base layer exposed at the bottom of the via hole. Therefore, the barrier metal layer provided in one interlayer insulating film includes the side and lower surfaces of the contact plugs formed in the interlayer insulating film, and the side and lower surfaces of the wiring (except for the connection region with the contact plugs). Will cover.

  In the case of forming a damascene copper wiring, a damascene copper wiring is connected to another damascene copper wiring formed in an interlayer insulating film below the damascene copper wiring by either the single damascene method or the dual damascene method. When a via hole is formed in the interlayer insulating film, a natural oxide film (copper oxide film) is inevitably formed on the surface of the damascene copper wiring exposed from the bottom of the via hole. This natural oxide film is a factor that lowers the electrical characteristics of the finally obtained semiconductor device, and also a factor that lowers the stress migration resistance (SM resistance) and electromigration resistance (EM resistance) of the semiconductor device. Prior to the formation of the barrier metal layer, for example, hydrogen plasma treatment or hydrogen annealing treatment is performed to remove the barrier metal layer, and this treatment time is the same for the damascene copper wiring formed in any interlayer insulating film.

  However, after removing the natural oxide film generated in the damascene copper wiring, a barrier metal layer, a contact plug, and other damascene copper wiring are provided thereon to form a multilayer copper wiring portion in the multilayer wiring portion in the semiconductor device. In many cases, however, voids (voids) are formed in contact plugs and damascene copper wirings as the use time of the semiconductor device elapses, and these contact plugs and damascene copper wirings are often disconnected. This phenomenon is called stress induced voiding (SIV), and its cause has not yet been elucidated. In order to increase the reliability of the semiconductor device, it is desired to improve the SIV resistance.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a semiconductor device that easily improves SIV resistance and a method for manufacturing the same.

  A semiconductor device of the present invention that achieves the above object includes a semiconductor substrate, a circuit element formed on the semiconductor substrate, and a multilayer copper wiring portion formed on the semiconductor substrate so as to cover the circuit element. The multilayer copper wiring portion includes a plurality of interlayer insulating films, a plurality of damascene copper wirings formed on each of the plurality of interlayer insulating films, and at least one damascene copper wiring. Contact plugs for connecting copper wirings to wirings or circuit elements below the interlayer insulating film in which the damascene copper wirings are formed, one damascene copper wiring and one damascene copper wiring, A semiconductor device having a barrier metal layer covering a side surface and a lower surface of each contact plug connected to a damascene copper wiring, and each of the interlayer insulating films constituting the multilayer copper wiring portion Except for the lowermost interlayer insulating film in the multilayer copper wiring portion, the first type damascene copper wiring and the width are narrower than the lower layer damascene copper wiring connected via the contact plug formed in the interlayer insulating film. A damascene copper wiring, a contact plug, and a damascene copper wiring formed in an interlayer insulating film in which the number of first type damascene copper wirings is larger than the number of second type damascene copper wirings; The maximum hydrogen content in the barrier metal layer is that the number of first-type damascene copper wirings is less than the number of second-type damascene copper wirings in a damascene copper wiring, contact plug, and barrier metal It is characterized by being smaller than the maximum value of the hydrogen content in the bed.

  The inventors of the present invention, when the natural oxide film generated in the damascene copper wiring is removed by hydrogen plasma treatment, hydrogen atoms are taken into the damascene copper wiring, contact plug or barrier metal layer, and the first type damascene copper wiring. In the contact plug corresponding to the first type damascene copper wiring, the SIV resistance tends to decrease as the hydrogen content increases. In the second type damascene copper wiring and the contact plug corresponding to the second type damascene copper wiring, It was clarified that there was almost no correlation between the increase in hydrogen content and SIV tolerance.

  In the semiconductor device of the present invention, the hydrogen content in the damascene copper wiring, the contact plug, and the barrier metal layer according to the number of the first type damascene copper wiring with respect to the number of the second type damascene copper wiring in each interlayer insulating film Since the maximum value is controlled, it is easy to improve the SIV tolerance of the entire semiconductor device.

  Hereinafter, embodiments of the semiconductor device and the manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view schematically showing an example of the semiconductor device of the present invention. A semiconductor device 60 shown in the figure includes a semiconductor substrate 10, circuit elements 20 and 30 formed on the semiconductor substrate 10, and a multilayer wiring portion 55 formed on the semiconductor substrate 10 so as to cover the circuit elements 20 and 30. And.

The semiconductor substrate 10 may be a substrate made of an elemental semiconductor such as silicon, or may be a substrate made of a compound semiconductor such as gallium arsenide. Furthermore, an SOI (Silicon On Insulator) substrate may be used. A predetermined element region (well) corresponding to the type of circuit element to be formed on the semiconductor substrate 10 and an element isolation region having a predetermined shape are formed at predetermined positions of the semiconductor substrate 10. The illustrated semiconductor substrate 10 has an N-type well 3 and a P-type well 5 formed at predetermined locations on a P ⁻ -type silicon substrate 1, and further element isolation regions so as to partition the element regions 3 and 5 in plan view. 7 is formed.

  Which element is formed as the circuit element is appropriately selected according to the function required of the semiconductor device 60. The circuit elements 20 and 30 shown in FIG. 1 are both field effect transistors (hereinafter referred to as “field effect transistor 20” and “field effect transistor 30”). The field effect transistor 20 includes a source region 12 and a drain region 14 formed in the N-type well 3, a gate electrode 18 disposed on the semiconductor substrate 10 via a gate insulating film 16, and a line width direction in the gate electrode 18. Side wall spacers SW and SW arranged on both sides are provided. The field effect transistor 30 includes a source region 22 and a drain region 24 formed in the P-type well 5, a gate electrode 28 disposed on the semiconductor substrate 10 via a gate insulating film 26, and a line in the gate electrode 28. Side wall spacers SW and SW are arranged on both sides in the width direction.

  The entire multilayer wiring portion 55 is a multilayer copper wiring portion (hereinafter referred to as “multilayer copper wiring portion 55”). The multilayer copper wiring portion 55 includes a plurality of interlayer insulating films, a plurality of damascene copper wirings formed in each of the plurality of interlayer insulating films, and at least one damascene copper wiring. Contact plugs that connect damascene copper wiring to wirings or circuit elements below the interlayer insulating film in which the damascene copper wiring is formed, and one damascene copper wiring are arranged one by one, and the damascene copper wiring and And a barrier metal layer covering the side and bottom surfaces of each contact plug connected to the damascene copper wiring.

  Each interlayer insulating film constituting the multilayer wiring portion (multilayer copper wiring portion) 55 is made of a desired inorganic material or organic material, and the individual interlayer insulating films are except for the lowermost interlayer insulating film. A narrower first type damascene copper wiring and a wider second type damascene copper wiring are formed as compared with the lower-layer damascene copper wiring connected through the formed contact plug. The numbers of the first type damascene copper wiring and the second type damascene copper wiring are appropriately selected for each interlayer insulating film. These damascene copper wirings and contact plugs are connected under a predetermined pattern to form an integrated circuit together with each of the circuit elements (field effect transistor 20 and field effect transistor 30).

  In FIG. 1, among the damascene copper wirings and contact plugs formed in each interlayer insulating film, four first layer contact plugs 32a to 32d and four four are formed in the lowermost first interlayer insulating film 35. First layer damascene copper wirings 33a to 33d, one second layer contact plug 37a formed in the second interlayer insulating film 40 second from the bottom, and the second (n-1) interlayer insulating film 45 second from the top Are formed in one (n-1) layer contact plug 42a, three (n-1) layer damascene copper wirings 43a to 43c, and the uppermost nth interlayer insulating film 50. Three n-layer contact plugs 47a to 47c and three n-th layer damascene copper wirings 48a to 48c appear. The nth layer damascene copper wiring 48b is a first type damascene copper wiring, and the nth layer damascene copper wiring 48c is a second type damascene copper wiring. Note that the second layer damascene copper wiring formed in the second interlayer insulating film 40 second from the bottom does not appear in FIG. The above “n” represents an integer of 4 or more, but it is also possible to configure a multilayer copper wiring portion with “n” being 2 or 3.

  Each contact plug and damascene copper wiring has a dual damascene structure, and each damascene copper wiring and contact plug formed on the same interlayer insulating film and connected to each other is composed of one region of one copper layer. ing. In FIG. 1, for the sake of convenience, a boundary line is drawn between the damascene copper wiring having a dual damascene structure and the contact plug.

  Each barrier metal layer BM is formed of, for example, a metal such as tantalum (Ta), titanium (Ti), tungsten (W), ruthenium (Ru), a nitride or nitride nitride of these metals, or the above-mentioned And a layer made of the above-mentioned nitride or nitride nitride, and covers the side and bottom surfaces of the corresponding contact plug and damascene copper wiring. However, the barrier metal layer is not formed in the region located on the contact plug in the lower surface of the damascene copper wiring. Note that a liner film formed of, for example, silicon nitride or silicon carbonitride is provided on each interlayer insulating film, but the illustration thereof is omitted in FIG.

  The greatest feature of the semiconductor device 60 having such a structure is that the number of first-type damascene copper wirings is larger than the number of second-type damascene copper wirings in a damascene copper wiring, contact plug, A damascene copper wiring, a contact plug, and a barrier having a maximum hydrogen content in the barrier metal layer, wherein the number of first-type damascene copper wiring is less than the number of second-type damascene copper wiring This is because it is smaller than the maximum hydrogen content in the metal layer. Since the semiconductor device 60 has the above-described characteristics, it is a semiconductor device that can easily improve the SIV resistance of the entire device. Hereinafter, the reason will be described with reference to FIGS.

  The “hydrogen content” in the present invention means a hydrogen content measured by a nuclear reaction analysis method (NRA). “The maximum value of the hydrogen content in the damascene copper wiring, the contact plug, and the barrier metal layer formed in the interlayer insulating film” means that the NRA extends from the damascene copper wiring to the contact plug and the barrier metal layer immediately below. Means the maximum value when the hydrogen content is measured sequentially.

  FIG. 2 is a graph showing an analysis result of the hydrogen content in the sample when the hydrogen plasma treatment is performed on the sample simulating the multilayer copper wiring part. In the above sample, a stack of a tantalum nitride layer and a tantalum layer, a first copper layer, a tantalum layer, and a second copper layer are stacked in this order on a silicon wafer on which a thermal oxide film is formed. The hydrogen plasma treatment is performed to remove a natural oxide film (copper oxide film) generated on the first copper layer before the tantalum layer is laminated on the first copper layer. This figure shows the analysis results when the treatment time with hydrogen plasma is 0 seconds, 30 seconds, or 180 seconds.

  Based on this analysis, the inventors have found that the first copper layer subjected to the hydrogen plasma treatment, the tantalum layer and the tantalum nitride layer under the first copper layer, and the tantalum layer on the first copper layer. It has been clarified that hydrogen atoms are also taken in, and the content tends to increase as the treatment time with hydrogen plasma increases. Based on this analysis result, even in an actual semiconductor device, when the natural oxide film generated in the damascene copper wiring is removed by the hydrogen plasma treatment, the damascene copper wiring subjected to the hydrogen plasma treatment is of course included in the damascene copper wiring. It is considered that hydrogen atoms are also taken into the corresponding barrier metal layer and the barrier metal layer formed on the damascene copper wiring. Note that the uptake of hydrogen atoms in the tantalum layer (the tantalum layer on the first copper layer) shown in FIG. 2 is due to the diffusion of the hydrogen atoms taken up in the first copper layer. Seem. In addition, the presence of hydrogen atoms was also confirmed in the second copper layer. This is because the moisture in the atmosphere does not increase until the hydrogen content is measured by NRA after the second copper layer is formed. This is considered to be a result of absorption by the copper layer 2.

  Based on the above analysis results, the present inventors have developed a wiring pattern in which the upper damascene copper wiring connected by one contact plug is narrower than the lower damascene copper wiring (hereinafter, “ And a wiring pattern in which the upper damascene copper wiring connected by one contact plug is wider than the lower damascene copper wiring (hereinafter referred to as “second pattern”). ”) Was examined for the presence of a relationship between hydrogen plasma treatment and SIV resistance.

  FIG. 3 is a graph showing the relationship between the treatment time with hydrogen plasma in the first pattern and the cumulative failure rate after 3000 hours. The data shown in the figure shows that the upper damascene copper wiring (upper damascene copper wiring) having a line width of 0.42 μm and the lower damascene copper wiring (lower damascene copper wiring) having a line width of 10 μm are contact plugs having a diameter of 0.14 μm. When the first pattern is formed on the silicon wafer by connecting with the above, six samples are prepared by appropriately changing the processing time in the hydrogen plasma processing applied to the lower damascene copper wiring, and the via resistance is increased for each sample. Is the cumulative failure rate after 3000 hours under the temperature condition of 200 ° C. A first wiring pattern is formed on a scale of 10,000 pieces in one sample. A tantalum layer is used as the barrier metal layer corresponding to the upper layer damascene copper wiring, and a laminate in which the tantalum nitride layer and the tantalum layer are stacked in this order is used as the barrier metal layer corresponding to the lower layer damascene copper wiring. ing. The hydrogen plasma treatment was performed using 100% hydrogen gas.

  As apparent from FIG. 3, in the first pattern, the cumulative failure rate when hydrogen plasma treatment is not performed is the lowest, and the cumulative failure rate tends to increase as the treatment time with hydrogen plasma becomes longer. Since the cumulative failure rate when the treatment time by hydrogen plasma is 0 (zero) seconds is 0%, in the first pattern, the natural oxide film generated in the lower damascene copper wiring is formed on the barrier metal layer (tantalum). Is considered to have been reduced by the layer).

  FIG. 4 is a graph showing the relationship between the treatment time with hydrogen plasma in the second pattern and the cumulative failure rate after 3000 hours. The data shown in the figure is for forming a second pattern on a silicon wafer by connecting an upper damascene copper wiring having a line width of 10 μm and a lower damascene copper wiring having a line width of 0.42 μm with a contact plug having a diameter of 0.14 μm. At that time, six samples were prepared by appropriately changing the processing time in the hydrogen plasma processing applied to the lower damascene copper wiring, and the cumulative failure rate was obtained for each sample. This data is measured under the same conditions as those obtained for the data shown in FIG. 3 except for the line widths of the upper layer damascene copper wiring and the lower layer damascene copper wiring.

  As is clear from FIG. 4, in the second pattern, the cumulative failure rate when hydrogen plasma treatment is not performed is the highest, and the cumulative failure rate for each sample subjected to hydrogen plasma treatment for 15 seconds or more is any sample. It was also 0%. Therefore, although the second pattern is strongly influenced by the natural oxide film generated in the lower damascene copper wiring, it is presumed that there is almost no correlation between the increase in the hydrogen content and the SIV resistance.

  As described above, it has been clarified by the study by the present inventors that the influence of the hydrogen content on the SIV resistance is mutually contradictory between the first pattern and the second pattern. In order to form the first pattern excellent in SIV resistance, it is desired to shorten the treatment time by hydrogen plasma as much as possible, and it is possible to omit the hydrogen plasma treatment. On the other hand, in order to form the second pattern having excellent SIV resistance, it is substantially essential to perform a hydrogen plasma treatment.

  In an actual semiconductor device, usually, a damascene copper wiring corresponding to the upper layer damascene copper wiring in the first pattern (“first type damascene copper wiring” in the present invention) and an upper layer damascene copper wiring in the second pattern are used. Corresponding damascene copper wiring (“second type damascene copper wiring” in the present invention) is mixed in one interlayer insulating film, and the number ratio of these damascene copper wirings is different for each interlayer insulating film. For this reason, in order to improve the SIV resistance of the semiconductor device as a whole, hydrogen plasma is performed prior to forming the barrier metal layer BM in each interlayer insulating film constituting the multilayer wiring portion (multilayer copper wiring portion). Instead of making the processing time in the processing constant, the processing time by hydrogen plasma can be appropriately adjusted according to the number ratio of the first type damascene copper wiring and the second type damascene copper wiring in each interlayer insulating film. desired. For an interlayer insulating film having a high number ratio of the first type damascene copper wiring, it is desirable to shorten the processing time by hydrogen plasma compared to an interlayer insulating film having a low number ratio of the first type damascene copper wiring.

  When the processing time by hydrogen plasma is adjusted as described above, as in the semiconductor device 60 shown in FIG. 1, the number of first-type damascene copper wirings is larger than the number of second-type damascene copper wirings. The maximum value of the hydrogen content in the formed damascene copper wiring, contact plug, and barrier metal layer was formed in an interlayer insulating film in which the number of first-type damascene copper wiring was less than the number of second-type damascene copper wiring Less than the maximum hydrogen content in damascene copper interconnects, contact plugs, and barrier metal layers.

Therefore, the semiconductor device 60 is a semiconductor device that can easily improve the SIV resistance of the entire device. What is the maximum hydrogen content in the damascene copper wiring, contact plug, and barrier metal layer formed in each interlayer insulating film, in other words, for forming the barrier metal layer in the interlayer insulating film? The amount of time for the hydrogen plasma treatment to be performed in advance is appropriately selected according to the number ratio of the first type damascene copper wiring and the second type damascene copper wiring in the interlayer insulating film. Usually, the maximum value is in the range of 0.1 × 10 ^{21 to} 5.0 × 10 ²¹ atoms / cc (0.1 × 10 ^{21 to} 5.0 × 10 ²¹ atoms / cm ³ ).

Embodiment 2. FIG.
The semiconductor device 60 described above can be obtained, for example, by the method for manufacturing a semiconductor device of the present invention. The manufacturing method includes an interlayer insulating film stacking step and a natural oxide film removing step. After the natural oxide film removal step, a predetermined post-step is performed. Hereinafter, it explains in full detail for every process.

(Interlayer insulation film lamination process)
In the interlayer insulating film laminating step, an electrical insulating film is formed on a wired interlayer insulating film on which a plurality of barrier metal layers, contact plugs, and damascene copper wirings are respectively formed, and then the electrical insulating film is patterned to form a damascene copper wiring. A non-wiring interlayer insulating film having a plurality of trenches in which the contact plugs are formed and a plurality of via holes in which contact plugs are formed is obtained. The plurality of trenches formed in the non-wiring interlayer insulating film include a first type trench in which a first type damascene copper wiring narrower than a damascene copper wiring exposed at the bottom of the via hole is formed, and a wide trench A second type trench in which a second type damascene copper wiring is formed.

  The wired interlayer insulating film may be any interlayer insulating film (however, excluding the uppermost interlayer insulating film) constituting the multilayer copper wiring portion. A semiconductor substrate on which desired circuit elements are formed is located under the multilayer copper wiring portion. However, the method for forming these semiconductor substrates and circuit elements is not particularly limited, and a semiconductor device to be manufactured. The semiconductor device is manufactured by various methods depending on the application and the function or performance required for the semiconductor device. The formation of the wired interlayer insulating film and the formation of the barrier metal layer, contact plug, and damascene copper wiring in the wired interlayer insulating film are performed as follows. Since this is performed in the same manner as the formation of the barrier metal layer, contact plug, and damascene copper wiring in FIG.

  FIG. 5 is a cross-sectional view schematically showing an example of an unwired interlayer insulating film. The non-wiring interlayer insulating film 50 shown in the figure corresponds to the n-th interlayer insulating film 50 shown in FIG. 1, and the wired interlayer insulating film 45 serving as the base is the (n-th) interlayer insulating film 45 shown in FIG. -1) Since it corresponds to the interlayer insulating film 45, the constituent members shown in FIG. 5 are denoted by the same reference numerals as those used in FIG.

In obtaining the non-wiring interlayer insulating film 50 shown in the figure, for example, an electric insulating film is formed of a desired inorganic material or organic material, and an etching mask having a predetermined shape is provided on the electric insulating film, and the electric insulating film is formed. Are selectively etched to form a plurality of damascene copper wiring trenches, and then another etching mask is provided in place of the etching mask to selectively etch the electrical insulating film. A plurality of via holes for plug formation are formed. As a result, a non-wiring interlayer insulating film 50 laminated on the wired interlayer insulating film 45 is obtained. In FIG. 5, three trenches T _{1 to} T ₃ and three via holes V _{1 to} V ₃ among the plurality of trenches and the plurality of via holes formed in the unwired interlayer insulating film 50 appear. Of the three trenches T _{1 to} T ₃ , the trench T ₂ corresponds to the first type trench, and the trench T ₃ corresponds to the second type trench.

(Natural oxide film removal process)
When the above-mentioned non-wiring interlayer insulating film is laminated on the wired interlayer insulating film, a natural oxide film (copper oxide) is inevitably formed on the surface of the damascene copper wiring exposed from the bottom of the via hole formed in the non-wiring interlayer insulating film. Therefore, in the natural oxide film removing step, the natural oxide film is removed using hydrogen gas or a gas containing hydrogen atoms.

  Specifically, the natural oxide film is removed by hydrogen plasma treatment, hydrogen annealing treatment, or hydrogen radical treatment. Instead of the hydrogen gas used in these methods, a mixed gas of hydrogen gas and an inert gas (helium gas, neon gas, argon gas, etc.), or a reducing gas containing hydrogen atoms (ammonia gas, etc.) was used. The natural oxide film can also be removed by plasma treatment, annealing treatment, or radical treatment.

FIG. 6 is a schematic cross-sectional view of an example of the natural oxide film removing step. In the example shown in the drawing, a natural oxide film (copper oxide generated on the surface of the damascene copper wiring 43a~43c exposed three via holes V ₁ ~V ₃ of each bottom formed unwired interlayer insulating film 50 Film) CO is removed by irradiating the natural oxide film CO with hydrogen plasma HP.

The processing time at this time depends on the number ratio of the first type damascene copper wiring and the second type damascene copper wiring to be formed in the unwired interlayer insulating film 45 as already described in the first embodiment. Controlled. When the number ratio of the first type damascene copper wiring exceeds 1, it is preferable to shorten the processing time compared to when the number ratio of the first type damascene copper wiring is less than one. In the illustrated example, the damascene copper wiring formed in the trench T ₂ which is the first type trench corresponds to the first type damascene copper wiring, and the damascene copper wiring formed in the trench T ₃ which is the second type trench. Corresponds to type 2 damascene copper wiring.

(Post-process)
In the post-process, a barrier metal layer, a contact plug, and a damascene copper wiring are formed on the unwiring interlayer insulating film 50 after the natural oxide film is removed as described above. The formation of the barrier metal layer, the contact plug, and the damascene copper wiring is performed, for example, as follows.

  First, an inorganic film serving as a base of the barrier metal layer is formed by physical vapor deposition such as sputtering, and a thin copper layer or thin copper alloy layer is formed thereon by physical vapor deposition such as sputtering. Form a film. A thin copper layer or a thin copper alloy layer formed on the inorganic film functions as a seed for forming a contact plug and a damascene copper wiring by a damascene method.

  Next, electrolytic plating is performed using the above seed as an electrode, and each of the via hole and the trench is filled with a copper plating layer. Thereafter, the excess copper plating layer, that is, the copper plating layer deposited on the upper surface of the unwiring interlayer insulating film 50 or the copper plating layer deposited in each via hole and each trench overflows from the via hole or the trench. The region and the region located on the upper surface of the non-wiring interlayer insulating film 50 in the inorganic film are removed by chemical mechanical polishing (CMP).

FIG. 7 is a cross-sectional view schematically showing an example of each of an inorganic film serving as a base of a barrier metal layer and a seed for forming a damascene copper wiring. As shown in the figure, the inorganic film 70 which is the source of the barrier metal layer, the via holes V ₁ ~V ₃ walls, damascene copper wiring 43a~43c exposed from the bottom of the via hole V ₁ ~V ₃ The film is formed so as to cover the upper surface, the wall surfaces of the trenches T _{1 to} T ₃ , and the upper surface of the non-wiring interlayer insulating film 50. The seed 72 s is formed on the inorganic film 70 so as to cover the inorganic film 70.

FIG. 8 is a cross-sectional view schematically showing an example of a copper plating layer formed by electrolytic plating using the above-described seed as an electrode. Copper plating layer 72 shown in the figure, consists of a seed 72s (see FIG. 7) and the copper deposited on the seed 72s, with fills the via holes V ₁ ~V ₃ and each trench T ₁ through T ₃ The upper surface of the non-wiring interlayer insulating film 50 is covered.

  By performing the above-described CMP on each of the copper plating layer 72 and the inorganic film 70 shown in FIG. 8, a predetermined number of barrier metal layers, contact plugs, and damascene copper wirings are formed on the unwired interlayer insulating film 50, respectively. The In the illustrated example, the n-th layer contact plugs 47 a to 47 c and the n-th layer damascene copper wirings 48 a to 48 c shown in FIG. 1 are formed in the unwired interlayer insulating film 50.

  A semiconductor device 60 shown in FIG. 1 includes a semiconductor substrate 10, circuit elements (field effect transistors) 20 and 30, a first interlayer insulating film 35, first layer contact plugs 32 a to 32 d, a first layer damascene shown in FIG. After the copper wirings 33a to 33d and the barrier metal layer BM corresponding to each first layer contact plug and each first layer damascene copper wiring are formed by a desired method, the interlayer insulating film stacking step and the natural oxide film removing step described above are performed. And the subsequent process is repeated as many times as necessary to form the multilayer copper wiring portion (multilayer wiring portion) 55.

  The embodiments of the semiconductor device and the manufacturing method thereof have been described above. However, as described above, the present invention is not limited to the above-described embodiments. For example, in the multilayer wiring part constituting the semiconductor device, in addition to the multilayer copper wiring part as a whole, wiring (including damascene wiring) is formed of the multilayer copper wiring part and a conductive material (for example, aluminum) other than copper. It can also be formed in combination with an interlayer insulating film. The interlayer insulating film in which the aluminum wiring is formed is disposed, for example, on the multilayer copper wiring portion.

  In dual damascene wiring using aluminum, for example, an inorganic film as a base of a barrier metal layer is formed on the wall surface of a via hole, the wall surface of a trench, and the upper surface of a non-wiring interlayer insulating film, respectively, and a low temperature environment ( After forming a thin aluminum layer by sputtering, for example, at room temperature), after depositing aluminum on the thin aluminum layer by sputtering in a high temperature environment (a temperature environment in which aluminum reflows), surplus aluminum And it can be obtained by removing the region of the inorganic film located on the upper surface of the interlayer insulating film by CMP.

  In the embodiment described above, each damascene copper wiring is a dual damascene wiring, but may be a single damascene wiring. In addition, the semiconductor device and the manufacturing method thereof according to the present invention can be variously modified, modified, combined, and the like.

It is sectional drawing which shows roughly an example of the semiconductor device of this invention. It is a graph which shows the analysis result of the hydrogen content in the said sample when performing the hydrogen plasma process to the sample which simulated the multilayer copper wiring part. The processing time by hydrogen plasma and the cumulative failure rate after 3000 hours in a wiring pattern in which the line width of the upper damascene copper wiring connected by one contact plug is narrower than that of the lower damascene copper wiring It is a graph which shows the relationship. The processing time by hydrogen plasma and the cumulative failure rate after 3000 hours in a wiring pattern in which the line width of the upper damascene copper wiring connected by one contact plug is wider than that of the lower damascene copper wiring It is a graph which shows the relationship. It is sectional drawing which shows roughly an example of the unwiring interlayer insulation film formed at the interlayer insulation film lamination process in the manufacturing method of the semiconductor device of this invention. FIG. 5 is a schematic cross-sectional view of an example of a natural oxide film removing step in the method for manufacturing a semiconductor device of the present invention. Sectional drawing which shows roughly an example of each of the inorganic film | membrane used as the origin of the barrier metal layer formed in a non-wiring interlayer insulation film, and the seed for damascene copper wiring formation in obtaining a semiconductor device by the manufacturing method of the semiconductor device of this invention It is. It is sectional drawing which shows roughly an example of the copper plating layer formed by the electroplating which used the seed shown in FIG. 7 as an electrode.

Explanation of symbols

10 Semiconductor substrate 20, 30 Circuit element (field effect transistor)
32a to 32d, 37a, 42a, 47a to 47c Contact plugs 33a to 33d, 43a to 43c, 48a Damascene wiring 45 The (n-1) interlayer insulation film (interlayer insulation film with wiring)
48b Damascene wiring (Type 1 Damascene wiring)
48c Damascene copper wiring (Type 2 damascene wiring)
50 n-th interlayer insulating film (wiring interlayer insulating film)
55 Multilayer wiring part (Multilayer copper wiring part)
BM barrier metal layer V _{1 to} V ₃ via hole T ₁ trench T ₂ trench (first type trench)
T ₃ trench (type 2 trench)

Claims (5)

A semiconductor substrate, a circuit element formed on the semiconductor substrate, and a multilayer copper wiring portion formed on the semiconductor substrate so as to cover the circuit element, the multilayer copper wiring portion including a plurality of interlayer insulations A film, a plurality of damascene copper wirings formed on each of the plurality of interlayer insulating films, and at least one damascene copper wiring are disposed on the damascene copper wiring. Contact plugs connected to wirings or circuit elements below the interlayer insulating film, and one each of the contact plugs arranged in one damascene copper wiring and connected to the damascene copper wiring and the damascene copper wiring. A semiconductor device having a barrier metal layer covering side and bottom surfaces,
In each of the interlayer insulating films constituting the multilayer copper wiring portion, except for the lowermost interlayer insulating film in the multilayer copper wiring portion, a lower layer side connected via a contact plug formed in the interlayer insulating film The first type damascene copper wiring and the second type damascene copper wiring which are narrower than the damascene copper wiring are formed.
The maximum value of the hydrogen content in the damascene copper wiring, the contact plug, and the barrier metal layer formed in the interlayer insulating film in which the number of the first type damascene copper wiring is larger than the number of the second type damascene copper wiring is: More than the maximum value of the hydrogen content in the damascene copper wiring, the contact plug, and the barrier metal layer formed in the interlayer insulating film in which the number of the first type damascene copper wiring is smaller than the number of the second type damascene copper wiring. A semiconductor device characterized by being small.   2. The semiconductor device according to claim 1, wherein each of the barrier metal layers is a tantalum layer, or a laminate in which a tantalum nitride layer and a tantalum layer are laminated in this order. A semiconductor substrate, a circuit element formed on the semiconductor substrate, and a multilayer copper wiring portion formed on the semiconductor substrate so as to cover the circuit element, the multilayer copper wiring portion including a plurality of interlayer insulations A film, a plurality of damascene copper wirings formed on each of the plurality of interlayer insulating films, and at least one damascene copper wiring are disposed on the damascene copper wiring. Contact plugs connected to wirings or circuit elements below the interlayer insulating film, and one each of the contact plugs arranged in one damascene copper wiring and connected to the damascene copper wiring and the damascene copper wiring. A method of manufacturing a semiconductor device having a barrier metal layer covering side and bottom surfaces,
A plurality of trenches in which a damascene copper wiring is formed by forming an electrical insulating film on a wired interlayer insulating film in which a plurality of barrier metal layers, contact plugs, and damascene copper wirings are respectively formed, and then patterning the electrical insulating film And an interlayer insulating film laminating step for obtaining an unwired interlayer insulating film having a plurality of via holes in which contact plugs are formed,
A natural oxide film removing step of removing a natural oxide film formed on the surface of the damascene copper wiring exposed at the bottom of the via hole using a hydrogen gas or a gas containing hydrogen atoms;
Including
In the plurality of trenches formed in the non-wiring interlayer insulating film in the interlayer insulating film stacking step, the first type damascene copper wiring narrower than the damascene copper wiring exposed at the bottom of the via hole is formed. A second type trench in which a first type trench and a wide second type damascene copper wiring are formed,
The processing time for removing the natural oxide film in the natural oxide film removing step is the time between the first type damascene copper wiring and the second type damascene copper wiring to be formed in the unwired interlayer insulating film. A method of manufacturing a semiconductor device, wherein the method is controlled according to a number ratio.   The processing time is such that when the number of the first type damascene copper wiring is larger than the number of the second type damascene copper wiring, the number of the first type damascene copper wiring is larger than that of the second type damascene copper wiring. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the method is shorter than when the number is less than the number.   5. The semiconductor device according to claim 3, wherein a thallium layer is formed as the barrier metal layer, or a laminate in which a thallium nitride layer and a thallium layer are laminated in this order is formed. Method.

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