JP2007081195A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An electric field concentration at a junction between a contact plug and a capacitor lower electrode is suppressed. A difference in polishing rate between tungsten and an interlayer insulating film is large, and the polishing rate of the insulating film is c and the polishing rate of tungsten is increased. When chemical mechanical polishing is performed under the condition that the polishing rate ratio “c / d” is 3 or more when d, the insulating film 130 is retracted and the upper end portion of the contact plug is exposed above the insulating film 130. Furthermore, the shape of the upper end portion of the contact plug is processed into a hemispherical shape by advancing the insulating film chemical mechanical polishing. When a conductive film is formed on a hemispherical contact plug and a capacitor lower electrode is formed, the contact interface becomes hemispherical and there is no acute contact area, so electric field concentration during voltage application is suppressed. The
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a structure and manufacturing method of a stacked capacitor lower electrode and a contact plug in contact therewith.

  As semiconductor memory devices, especially DRAMs, become more highly integrated and have larger capacities, in order to ensure the capacitance of the capacitors, three-dimensional memory cells are being developed, and DRAMs using stacked capacitors have been developed. (For example, refer to Patent Document 1).

  Hereinafter, a structure of a conventional stacked capacitor and a method for forming the same will be described with reference to FIGS.

  FIG. 4 shows a cross-sectional view of a semiconductor memory device, particularly a DRAM. In FIG. 4, reference numeral 410 denotes a semiconductor or insulating substrate. Reference numeral 420 denotes a gate of a transistor constituting the memory cell. Reference numeral 430 denotes an interlayer insulating film. Reference numeral 460 indicates a contact plug for connecting the transistor and the stacked capacitor. Reference numeral 480 denotes a capacitor lower electrode of the stacked capacitor.

  In general, in a stacked capacitor, at the junction between the contact plug and the capacitor lower electrode that is in contact with it, the upper end of the contact plug protrudes from the interlayer insulating film due to the effect of overetching when the storage node (stacked capacitor) is formed. As a result, the upper end of the contact plug is present inside the capacitor lower electrode. At this time, the joint surface between the upper end portion of the contact plug and the capacitor lower electrode has an acute angle shape of 90 degrees or less. In FIG. 4, reference numeral 400 indicates an acute plug joint. In this case, performance degradation of the semiconductor device due to electric field concentration occurs at the contact point between the upper end portion of the contact plug and the capacitor lower electrode.

  Here, the reason why electric field concentration occurs at the upper end of the contact plug will be described. The electric field concentration occurs at the upper end portion of the contact, but also occurs at a different or the same type of conductor contact portion. When the tip of the contact plug has an acute angle shape, the contact area between the conductors becomes small at the tip of the contact portion, and it is considered that electric field concentration occurs due to the difference in area.

  A method of forming the lower first electrode of the capacitor will be described with reference to FIG.

  A transistor having a gate 420 is formed over a semiconductor or insulating substrate 410, and an HDP-NSG (High Density Plasma-Nondope Silicate Glass) film having a thickness of 700 nm, for example, is deposited as the insulating film 430 and subjected to heat treatment (FIG. 5 (a)).

  Next, chemical mechanical polishing flattening is performed on the insulating film 430 so that the film thickness becomes, for example, 400 nm (FIG. 5B).

  Next, a contact hole 440 for making contact with the gate 420 and the source / drain of the transistor constituting the memory cell is formed by lithography and dry etching (FIG. 5C). The diameter of the contact hole is, for example, 200 to 300 nm.

  Next, for example, tungsten 450 is deposited to a thickness of, for example, 300 nm as a conductive film on the surface of the insulating film 430 including the inside of the contact hole 440 (FIG. 5D).

  Next, tungsten chemical mechanical polishing in which the insulating film 430 acts as a stopper is performed to form a contact plug 460 made of tungsten (FIG. 5E). At this time, since the polishing of the insulating film 430 does not proceed, a plug recess 470 occurs. That is, the upper end of the contact plug 460 is recessed in a mortar shape, and the upper end of the contact plug 460 has an acute shape (FIG. 5F).

  Next, a storage node (stacked capacitor) is formed on the insulating film 430 on which the contact plug 460 is formed. The upper end portion of the contact plug 460 is formed from the surface of the insulating film 430 by overetching by dry etching at that time. It protrudes (FIG. 5 (g)).

  Further, a capacitor lower electrode 480 is formed thereon, and then a dielectric film 490 and a capacitor upper electrode 491 are formed.

  When capacitor lower electrode 480 is formed on contact plug 460, electric field concentration occurs at an acute contact interface between contact plug 460 and capacitor lower electrode 480 (FIG. 4). The occurrence of the plug recess 470 causes the upper end of the contact plug 460 to have a sharper shape, which causes a situation where electric field concentration is likely to occur. In order to prevent such problems, attempts have been made to suppress plug recesses by optimizing chemical mechanical polishing conditions.

  First, a method for suppressing plug recess by optimizing chemical mechanical polishing slurry will be described.

  Regarding the occurrence of the plug recess, the influence of the abrasive particles of the conductive film slurry, the additive, and the concentration thereof is the largest. Therefore, it is possible to suppress the occurrence of plug recesses by adjusting these compositions and bringing the selection ratio of the polishing rate with the insulating film (oxide film) 430 closer to 1.

  Next, plug plug suppression by improving chemical mechanical polishing conditions will be described.

Recent improvements in equipment performance have enabled chemical mechanical polishing at extremely low pressure (˜0.5 psi (= 3447.5 Pa)). By carrying out the conductive film chemical mechanical polishing under these conditions, chemical mechanical polishing that generates as little plug recess as possible is possible.
Japanese Patent Laid-Open No. 10-294441

  However, even if the plug recess is set to 0 nm, the angle of the upper end portion of the contact plug is limited to 90 degrees when completely flattened. Therefore, none of the above measures is perfect for suppressing electric field concentration.

  Further, as a countermeasure against the low selectivity chemical mechanical polishing slurry, it is possible to suppress the plug recess, but since there is no polishing stopper, there is a new concern that the variation in the plug height in the wafer surface will increase.

  As described above, the main cause of electric field concentration is the sharp upper end shape of the contact plug after chemical mechanical polishing of the conductive film, but the corner at the upper end of the plug is removed as a countermeasure by improving the polishing conditions of the chemical mechanical polishing of the conductive film. It is very difficult.

  As mentioned above, the method of preventing electric field concentration by conductive film chemical mechanical polishing is actually very difficult.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of suppressing electric field concentration at a junction between a contact plug and a capacitor lower electrode, and a manufacturing method thereof.

  In order to solve the above-mentioned problems, the present invention changes the way of viewing and assumes that the shape of the upper end of the contact plug becomes acute, and introduces a process for removing the acute angle portion of the upper end of the contact plug to introduce an upper end of the contact plug. Is formed into a convex curved surface to prevent sharp bonding at the contact interface between the contact plug and the capacitor lower electrode. As a result, electric field concentration at the junction between the contact plug and the capacitor lower electrode can be suppressed.

  As a method for processing the upper end portion of the contact plug, a method by chemical mechanical polishing, a method using oxide film wet etching and conductive film wet etching, or a method using oxide film wet etching and reverse sputtering is preferable.

  Specifically, the semiconductor device of the present invention includes a substrate, an interlayer insulating film provided on the substrate, a contact plug formed on the interlayer insulating film, and a capacitor lower electrode formed on the interlayer insulating film. And. The upper end of the contact plug protrudes from the surface of the interlayer insulating film, the upper end shape of the contact plug is a convex curved surface, and the upper end of the convex curved surface of the contact plug is located inside the capacitor lower electrode in contact with the contact plug. .

  The method for manufacturing a semiconductor device of the present invention includes the following steps (a) to (d). In the step (a), a conductive film is formed on an interlayer insulating film provided on the substrate and having contact holes. In step (b) after step (a), the conductive film is subjected to chemical mechanical polishing to form a contact plug. In the step (c) after the step (b), a part of the interlayer insulating film is removed to protrude the contact plug upward from the surface of the interlayer insulating film, and a part of the protruding contact plug is removed. The upper end is processed into a convex curved surface. In the step (d) after the step (c), a capacitor lower electrode is formed on the interlayer insulating film in which the contact plug is formed. Here, the convex curved upper end of the contact plug is located inside the capacitor lower electrode in contact with the contact plug.

  In the method of manufacturing a semiconductor device according to the present invention, the step (c) is preferably performed under the condition that the ratio “a / b” of the conductive film polishing rate b to the interlayer insulating film polishing rate a is 3 or more. .

  In the method for manufacturing a semiconductor device of the present invention, step (c) may include step (e) and step (f). In the step (e), a part of the interlayer insulating film is removed by wet etching under the condition that the ratio “c / d” of the wet etching rate d of the conductive film to the wet etching rate c of the interlayer insulating film is 3 or more. In the step (f) after the step (e), the protruding contact plug is formed under the condition that the ratio “e / f” of the wet etching rate f of the conductive film to the wet etching rate e of the interlayer insulating film is 0.9 or less. Remove some of the.

  In the method for manufacturing a semiconductor device of the present invention, the step (c) may include a step (e) and a step (g). In the step (e), a part of the interlayer insulating film is removed by wet etching under the condition that the ratio “c / d” of the conductive film removal rate d to the interlayer insulating film removal rate c is 3 or more. In the step (g) after the step (e), reverse sputtering is performed on the surface of the interlayer insulating film, and a part of the protruding contact plug is removed.

  In the method for manufacturing a semiconductor device of the present invention, the conductive film is made of, for example, tungsten, titanium nitride, titanium, polysilicon, or amorphous silicon.

  According to the present invention, the conductive film deposited on the surface of the insulating film having a trench or contact hole is subjected to conductive film chemical mechanical polishing using the insulating film as a polishing stopper, and the contact plug upper end is formed into a convex curved surface. By processing into, the electric field concentration at the contact interface between the contact plug and the conductive film in contact with the contact plug can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

  A transistor having a gate 120 is formed over a semiconductor or insulating substrate 110, an HDP-NSG film having a thickness of, for example, 700 nm is deposited as the insulating film 130, and heat treatment is performed (FIG. 1A).

  Next, chemical mechanical polishing flattening is performed on the insulating film 130 to make the film thickness 500 nm, for example (FIG. 1B).

  Next, a contact hole 140 for making contact with the gate 120 and the source / drain of the transistor is formed by lithography and dry etching (FIG. 1C). The diameter of the contact hole is, for example, 200 to 300 nm. Further, it is preferable to add a removal amount of about 100 to 300 nm to the design value so that the depth of the contact hole may be removed in a later step.

  Next, as a conductive film, for example, tungsten 150 is deposited to a thickness of, for example, 250 nm on the surface of the insulating film 130 including the inside of the contact hole 140 (FIG. 1D).

  Next, tungsten chemical mechanical polishing in which the insulating film 130 acts as a stopper is performed to form a contact plug 160 made of tungsten (FIG. 1E). Since the polishing of the insulating film 130 does not proceed, a plug recess 170 is generated, the upper end of the contact plug 160 is recessed in a mortar shape, and the upper end of the contact plug 160 has an acute shape (FIG. 1 (f)). At this time, the ratio “b / a” of the polishing rate a of the insulating film 130 to the polishing rate b of tungsten is set to 1 or more.

  Next, the polishing rate ratio “c / d” is 3 or more when the polishing rate difference between tungsten and the insulating film 130 is large, the polishing rate of the insulating film 130 is c, and the polishing rate of tungsten is d. When chemical mechanical polishing is performed, the insulating film 130 is retracted, and the upper end portion of the contact plug 160 is exposed above the insulating film 130 (FIG. 1G).

  Further, the insulating film chemical mechanical polishing is advanced to change the insulating film 130 from a broken line state to a solid line state, and the shape of the upper end portion of the contact plug 160 is processed into a convex curved surface shape, for example, a hemispherical shape (see FIG. 1 (h)). Reference numeral 180 denotes a contact plug whose tip is spheroidized. This chemical mechanical polishing is referred to as buff chemical mechanical polishing for convenience.

  A conductive film is formed on the hemispherical contact plug 180 to form a capacitor lower electrode 190. Thereafter, a dielectric film 191 and a capacitor upper electrode 192 are formed (FIG. 1 (i)).

  In FIG. 6, reference numeral 100 denotes a plug joint. From FIG. 6, it can be seen that the plug joint portion 100 does not have an acute angle portion as in the conventional example.

  The contact interface between the contact plug 180 and the capacitor lower electrode 190 is hemispherical, and there is no acute contact area. Therefore, it is considered that electric field concentration during voltage application is suppressed.

  Examples of the slurry used in chemical mechanical polishing of an oxide film such as HDP-NSG include the following slurries. This slurry contains, for example, fumed silica as particles and ammonium hydroxide or potassium hydroxide as a pH adjuster.

  Examples of the slurry used in chemical mechanical polishing of tungsten include the following slurries. This slurry contains, for example, silica as an abrasive particle, an additive for adjusting the polishing rate selection ratio with the underlying oxide film, and the like. As the slurry used in the buff chemical mechanical polishing, the oxide film chemical mechanical polishing slurry is used. When the polishing rate of the oxide film is i and the polishing rate of tungsten is j, the polishing rate ratio “i / j” is approximately 3 or more.

  The polishing amount of the buff chemical mechanical polishing is preferably about 100 to 150 nm, which is half the contact plug diameter. The larger the buff chemical mechanical polishing amount, the larger the plug protrusion and the contact area with the conductive film. However, when the capacitor lower electrode is embedded, the protrusion shape hinders the embedding of the electrode material. The upper limit of the polishing amount for buff chemical mechanical polishing is preferably about 150 nm from the viewpoint of increasing the amount of polishing in buff chemical mechanical polishing.

  The advantage of using this method is that it can be completed in a single step from plug protrusion to upper end hemispherical processing. For this reason, the process can be shortened.

  However, the use of chemical mechanical polishing may cause new surface defects such as micro scratches depending on the consumable member and polishing conditions.

  Although tungsten is used as the conductive film, titanium nitride, titanium, polysilicon, or amorphous silicon may be used.

(Embodiment 2)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG.

  A transistor having a gate 220 is formed on a semiconductor or insulating substrate 210, and an HDP-NSG film having a thickness of 700 nm, for example, is deposited as the insulating film 230 and heat treatment is performed (FIG. 2A).

  Next, chemical mechanical polishing flattening is performed on the insulating film 230 so that the film thickness becomes 400 nm, for example (FIG. 2B).

  Next, a contact hole 240 for making contact with the gate 220 and the source / drain of the transistor is formed by lithography and dry etching (FIG. 2C). The diameter of the contact hole is, for example, 200 to 300 nm.

  Next, as a conductive film, for example, tungsten 250 is deposited to a thickness of, for example, 300 nm on the surface of the insulating film 230 including the inside of the contact hole 240 (FIG. 2D).

  Next, tungsten chemical mechanical polishing in which the insulating film 230 acts as a stopper is performed to form a contact plug 260 made of tungsten (FIG. 2E). Since the polishing of the insulating film 230 does not proceed, a plug recess 270 is generated, the upper end of the contact plug 260 is recessed in a mortar shape, and the upper end of the contact plug 260 has an acute shape (FIG. 2F). At this time, the ratio “b / a” of the polishing rate a of the insulating film 230 to the polishing rate b of tungsten is set to 1 or more.

  Next, when the first wet etching is performed under a condition where the wet etching rate difference between the tungsten and the insulating film 230 is large and tungsten is difficult to be etched, the insulating film 230 is retracted, and the upper end portion of the contact plug 260 is the insulating film. It is exposed above 230 (FIG. 2G). A typical chemical solution used for the first wet etching includes dilute hydrofluoric acid, and the concentration is preferably 1 to 5%. At this time, the ratio “c / d” of the wet etching rate d of tungsten to the wet etching rate c of the insulating film 230 is preferably 3 or more. Furthermore, when the second wet etching is performed under the condition that the etching rate difference between tungsten and the insulating film 230 is large and the insulating film 230 is difficult to be etched, the shape of the upper end portion of the contact plug 260 becomes a convex curved surface, for example, a hemispherical shape. It is processed (FIG. 2 (h)). In FIG. 2H, reference numeral 280 denotes a contact plug whose tip is spheroidized.

  As a typical chemical solution used for the second wet etching, hydrogen peroxide water can be cited, and its concentration is preferably 2 to 3%. At this time, the ratio “e / f” of the wet etching rate f of tungsten to the wet etching rate e of the insulating film 230 is preferably 0.9 or less.

  A conductive film is formed on the contact plug 280 processed into a hemispherical shape in the same manner as in the first embodiment to form a capacitor lower electrode 290. Thereafter, a dielectric film 291 and a capacitor upper electrode 292 are formed (FIG. 2 (i)).

  Since there is no acute contact area at the contact interface between the contact plug 280 and the capacitor lower electrode 290, it is considered that electric field concentration during voltage application is suppressed.

  The first wet etching may be dry etching in which the ratio “c / d” of the tungsten removal rate d to the removal rate c of the insulating film 230 is 3 or more. In addition, the chemical used for the second wet etching is another chemical if the ratio “e / f” of the tungsten wet etching rate f to the removal rate e of the insulating film 230 is 0.9 or less. It does not matter.

As an advantage of using this method, it is easy to adjust the wet etching amount and there is little damage to the wafer surface. However, since it is necessary to carry out the processing in two steps, the number of steps is more difficult than in the case of the first embodiment.
(Embodiment 3)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below with reference to FIG.

  A transistor having a gate 320 is formed over a semiconductor or insulating substrate 310, and an HDP-NSG film having a thickness of, for example, 700 nm is deposited as the insulating film 330 and heat treatment is performed (FIG. 3A).

  Next, chemical mechanical polishing flattening is performed on the insulating film 330 so that the film thickness becomes, for example, 400 nm (FIG. 3B).

  Next, a contact hole 340 for making contact with the gate 320 and the source / drain of the transistor is formed by lithography and dry etching (FIG. 3C). The diameter of the contact hole is, for example, 200 to 300 nm.

  Next, on the surface of the insulating film 330 including the inside of the contact hole 340, for example, tungsten 350 is deposited as a conductive film to a film thickness of 300 nm, for example (FIG. 3D).

  Next, tungsten chemical mechanical polishing in which the insulating film 330 acts as a stopper is performed to form a contact plug 360 made of tungsten (FIG. 3E). Since the polishing of the insulating film 330 does not proceed, a plug recess 370 is generated, the upper end of the contact plug 360 is recessed in a mortar shape, and the upper end of the contact plug 360 has an acute shape (FIG. 3F). At this time, the ratio “b / a” of the polishing rate a of the insulating film 330 to the polishing rate b of tungsten is set to 1 or more.

  Next, when wet etching is performed under the condition that the removal rate difference between the tungsten and the insulating film 330 is large and tungsten is difficult to be removed, the insulating film 330 is retracted, and the upper end portion of the contact plug 360 is located above the insulating film 330. Exposed (FIG. 3 (g)). A typical chemical used for the wet etching includes dilute hydrofluoric acid, and the concentration is preferably 1 to 5%.

  Furthermore, when the contact plug 360 is formed and the reverse sputtering process is performed on the surface of the insulating film 330 from which the contact plug 360 protrudes, the upper end portion of the contact plug 360 and a part of the surface of the insulating film 330 are physically separated. In particular, the upper end of the contact plug 360 protruding on the insulating film 330 is processed into a tapered shape, so that the shape of the upper end of the plug becomes a convex curved surface, for example, a hemispherical shape (FIG. 3H). In FIG. 3 (h), reference numeral 380 indicates a contact plug whose tip is spheroidized.

  Note that in the sputtering process, a metal or silicide target is placed against the wafer in a chamber under high vacuum, and argon gas is introduced. Argon is ionized using glow discharge due to a high electric field applied between the wafer and the target, the target is hit with high-energy argon ions accelerated by the electric field, and target material atoms that jump out of the recoil are attached to the wafer. It is processing. The reverse sputtering process is a process of directly removing atoms on the wafer surface by hitting ionized argon ions against the workpiece by the above method.

  As a method of adjusting the taper angle of the upper end of the contact plug 380, adjusting the directivity of Ar gas particles used during reverse sputtering can be mentioned. Generally, when the DC bias voltage applied to the substrate side during the reverse sputtering process is increased, the force with which Ar particles are attracted to the substrate increases, and the directivity increases. When the directivity increases, removal processing in the vertical direction is promoted with respect to the substrate, and the taper angle of the upper end of the contact plug 380 is reduced. When the directivity is lowered, the removal process in the vertical direction is weakened, and the taper angle of the upper end of the contact plug 380 is increased. Further, the DC voltage applied to the substrate is desirably 100 to 200 V, and it is possible to form a contact plug upper end shape that is closer to a hemispherical shape by increasing or decreasing the DC voltage stepwise.

  A conductive film is formed on the contact plug 380 processed into a hemispherical shape to form a capacitor lower electrode 390. Thereafter, a dielectric film 391 and a capacitor upper electrode 392 are formed (FIG. 3I).

  Since there is no acute contact area at the contact interface between the contact plug 380 and the capacitor lower electrode 390, it is considered that electric field concentration during voltage application is suppressed (FIG. 3 (i)).

  An advantage of using this method is that it can be processed without causing physical damage such as scratches. However, since the processing is performed in a reduced pressure atmosphere, the productivity is lower than in the first and second embodiments.

  In each of the above embodiments, the upper end of the contact plug has been described as being hemispherical. However, the shape of the upper end of the contact plug is not limited to a hemispherical shape. May be a convex curved surface that is flat and has a periphery that smoothly continues with respect to the peripheral surface of the contact plug.

  Further, the present invention is not limited to a columnar or prismatic contact plug, but can also be applied to a contact plug having a trench structure.

  As described above, the present invention is useful for a semiconductor device having a stacked capacitor.

It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 3 of this invention. It is a schematic sectional drawing of the prior art of a semiconductor device. It is a schematic sectional drawing which shows the manufacturing process of the prior art of a semiconductor device. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Plug junction part 110 Substrate 120 Gate 130 Insulating film 140 Contact hole 150 Tungsten 160 Contact plug 170 Plug recess 180 Contact plug whose upper end is hemispherical processing 210 Substrate 220 Gate 230 Insulating film 240 Contact hole 250 Tungsten 260 Contact plug 270 Plug recess 280 Contact plug 310 whose upper end is hemispherically processed 310 Substrate 320 Gate 330 Insulating film 340 Contact hole 350 Tungsten 360 Contact plug 370 Plug recess 380 Insulating film 390 in which the contact plug protrudes 390 Contact plug 400 whose upper end is hemispherically processed 400 Acute Plug joint 410 Substrate 420 Gate 430 Insulating film 440 Contact hole 450 Tungsten 460 contact plug 470 plug recess 480 capacitor lower electrode

Claims (6)

A substrate, an interlayer insulating film provided on the substrate, a contact plug formed on the interlayer insulating film, and a capacitor lower electrode formed on the interlayer insulating film,
The upper end of the contact plug protrudes from the surface of the interlayer insulating film, the upper end shape of the contact plug is a convex curved surface, and the upper end of the convex curved surface of the contact plug is in contact with the contact plug. A semiconductor device located inside. A step (a) of forming a conductive film on an interlayer insulating film provided on a substrate and having contact holes formed thereon;
(B) after the step (a), chemical mechanical polishing the conductive film to form a contact plug;
After the step (b), a part of the interlayer insulating film is removed to protrude a contact plug upward from the surface of the interlayer insulating film, and a part of the protruding contact plug is removed to remove the upper end. A step (c) of processing into a convex curved surface;
Forming a capacitor lower electrode on the interlayer insulating film in which the contact plug is formed, and (d),
A method for manufacturing a semiconductor device, wherein an upper end of a convex curved surface of the contact plug is located inside a capacitor lower electrode in contact with the contact plug.   3. The semiconductor device according to claim 2, wherein the step (c) is performed under a condition that a ratio “a / b” of the polishing rate b of the conductive film to the polishing rate a of the interlayer insulating film is 3 or more. Manufacturing method. The step (c)
A step (e) of removing part of the interlayer insulating film by wet etching under a condition that a ratio “c / d” of the wet etching rate d of the conductive film to the wet etching rate c of the interlayer insulating film is 3 or more; ,
After the step (e), one of the protruding contact plugs is formed under a condition that a ratio “e / f” of the wet etching rate f of the conductive film to the wet etching rate e of the interlayer insulating film is 0.9 or less. The method for manufacturing a semiconductor device according to claim 2, further comprising a step (f) of removing the portion. The step (c)
A step (e) of removing part of the interlayer insulating film by wet etching under a condition that a ratio “c / d” of the conductive film removal rate d to the interlayer insulating film removal rate c is 3 or more;
3. The method according to claim 2, further comprising: after the step (e), performing a reverse sputtering process on the surface of the interlayer insulating film to remove a part of the protruding contact plug. A method for manufacturing a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 2, wherein the conductive film is made of tungsten, titanium nitride, titanium, polysilicon, or amorphous silicon.

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