JP2006196560A - Semiconductor device - Google Patents

Abstract

To cope with an increase in the number of pins, a part of an electrode pad on a main surface of a semiconductor chip is pulled out to the back surface side.
A circuit element (not shown) and a plurality of electrode pads (2a, 2b) are provided on the main surface of a semiconductor chip (1), and a part of the electrode pads (2a) is led out to the back side of the semiconductor chip (1) through a through wiring portion (3). Then, the electrode pads 2 b that are connected to the back surface connection wiring pattern 5 of the interposer substrate 4 and remain on the main surface are connected to the surface connection wiring pattern 6 by wire bonding 7. By connecting the electrode pads 2a and 2b of the semiconductor chip 1 separately on the main surface side and the back surface side, the wiring portion on the interposer substrate 4 can be effectively used, and the downsizing of the device can be promoted.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having an efficient mounting structure of a semiconductor package or module for connecting a semiconductor chip to a wiring board.

  2. Description of the Related Art Conventionally, a semiconductor chip has a plurality of electrode pads for connecting a wiring board, and the semiconductor chip is mounted on an interposer substrate that is a wiring board of a package. Are normally connected by a wire bonding method using Au wire having a diameter of 0.02 to 0.03 mm. After the electrical connection, the semiconductor chip and the Au wire are sealed with an epoxy resin for protecting the semiconductor chip and the Au wire by a transfer molding method to form a semiconductor package.

  The wiring portion of the interposer substrate is connected to a package electrode having a wide connection interval of 0.5 to 1.0 mm in order to connect to a motherboard having a lower wiring density. The package electrode provided with solder balls having a diameter of 0.3 to 0.6 mm is called FBGA (Fine Pith Ball Grid Array).

  Therefore, the electrode pads of the semiconductor chip, which are usually provided at intervals of 0.06 to 0.1 mm, are expanded to intervals of 0.5 to 1.0 mm when connecting to the motherboard via the interposer substrate. ing.

  Alternatively, after the bumps made of Ni or Au are plated on the electrode pads of the semiconductor chip or formed by a ball bonder, the bumps are aligned with the electrodes of the interposer substrate pre-coated with Sn-Ag solder. In some cases, the connection is made by a flip chip method in which an alloy is connected by heating and pressing at 150 to 250 ° C.

  In addition, by rearranging the electrode pads in a matrix using a redistribution technique on the semiconductor chip, after widening the pad spacing, after a certain amount of solder is disposed on the electrode pads by vapor deposition or printing, The solder is melted by heating to 200 to 300 ° C. to form a solder ball, and the semiconductor chip having the solder ball is aligned so that the electrode on the wiring substrate and the solder ball face each other, and then mounted on the wiring substrate. In some cases, so-called C4 connection is used in which the solder balls are melted by heating at 200 to 300 ° C. in a reflow furnace and joined to the electrodes of the wiring board. Normally, the pad pitch used for this C4 connection is as wide as 0.15 to 0.30 mm, and if it is an 8 mm square chip, 600 to 2800 electrode pads can be provided by forming a full grid. is there.

  In the case of the flip chip connection and the C4 connection described above, in order to prevent the connection portion from being broken due to thermal stress due to the thermal expansion difference between Si of the semiconductor chip and the glass epoxy resin of the wiring substrate, An underfill material in which silica particles are mixed in an epoxy resin is injected into a slight gap of 0.03 to 0.1 mm, and is cured and reinforced.

Furthermore, as disclosed in Patent Document 1, flip chip connection is used for high-frequency signal line connection, and wire bonding is performed on the back surface as a ground electrode of a GaAs substrate, thereby reducing and stabilizing the wiring impedance. A method for securing a ground potential of a semi-insulating substrate peculiar to a GaAs substrate is known. Further, as disclosed in Patent Document 2 and Patent Document 3, through holes are formed in a Si substrate that is a semiconductor chip, insulation is performed, a conductor is provided, and an electrode portion is provided on the back surface or side surface of the semiconductor chip. A method of forming and stacking has also been proposed.
JP-A-6-120302 JP-A-8-306724 JP 2002-198463 A

  However, there are various technical problems in the above prior art. First, it has become impossible to make a high-density connection corresponding to the increase in the number of pads of a semiconductor chip. Currently, the pitch of electrode pads for wire bonding of a semiconductor chip is about 0.08 to 0.05 mm, and if the chip size is 8 mm, 100 to 160 electrode pads are provided per side. The number is 400 to 640. However, shrinkage (size reduction) of 0.7 times the chip due to the progress of the semiconductor process rule by one generation leads to a side of 5.6 mm even on the same chip. To obtain the same number of pads, a pad pitch of 0.035-0. 056 mm must be realized.

  On the other hand, the wiring pitch on the side of the wiring board connected to the electrode pads of the semiconductor chip by wire bonding is 0.08 to 0.1 mm, and cannot catch up with the shrinkage of the pad pitch of the semiconductor chip. Therefore, the length per side of the electrode part on the wiring board side is required to be 8.0 to 16.0 mm, and not only the package size cannot be reduced, but also the electrode of the wiring board from the electrode pad of the semiconductor chip. Since the length to the part far exceeds several millimeters which is the limit of wire bonding, a wire droop or a wire short occurs.

  Further, in the case of flip chip connection, the pad pitch is shortened, so that the wiring rule of the wiring board must be matched with the pad pitch of the semiconductor chip to form a wiring with a very narrow pitch with a wiring width of 15 to 25 μm. Incurs a significant increase in cost. Furthermore, it is necessary to pre-coat solder for bonding on the thin wiring, but it is difficult to pre-coat to this wiring width, and even if it can be pre-coated, the cross-sectional shape becomes semicircular Therefore, the bumps slide off from the electrodes due to the load applied during bonding, and it is difficult to obtain stable bonding.

  In addition, as the pitch becomes narrower, the bump height has to be lowered, so that the gap between the semiconductor chip and the wiring board is 20 to 40 μm, and the filler particle size of the reinforcing underfill resin must be several μm or less. In this case, stable injection cannot be performed, but at this particle size, aggregation of particles occurs and it is difficult to perform stable injection.

  Furthermore, in C4 connection, it is possible to provide 18 × 18 = 324 to 37 × 37 = 1369 electrode pads on the surface of a 5.6 mm square semiconductor chip, and the pad pitch is also compared with wire bonding or flip chip. It seems that there is no problem because it is loose, but the pad arrangement becomes a multi-row matrix structure, and if you try to pull out the wiring from the electrode terminal on the inner periphery, a multilayer board is required, which eventually increases the board cost significantly .

  Further, in the case of C4 connection, since solder is used as a bonding material, a flux containing an acid that removes an oxide film on the solder surface is used. Therefore, the surface of the semiconductor chip is contaminated with gas generated from the flux during bonding. In order to prevent corrosion due to acid contained in the flux residue remaining after the joining, a flux cleaning step is essential.

  Furthermore, since the reinforcing underfill material is injected in a liquid state, it protrudes by about 1 to 2 mm around the semiconductor chip. If the gap between the semiconductor chip and the wiring board is not filled with an underfill material without a gap, a problem in reliability will occur, and a certain amount must flow out of the semiconductor chip in order to be sufficiently filled. Is difficult to reduce. For this reason, the underfill region should be taken into account as the semiconductor chip mounting region. In the case of flip chip or C4 connection, the actual mounting area required for the flip chip or C4 connection is the semiconductor chip area. A larger area is required.

  In addition, if wire bonding is performed from the flip-chip connected back surface, a bonding pad that is an electrode on the wiring board side must be provided in a region beyond the underfill protruding region (1-2 mm from the chip end). The total length of the Au wire must be long. Furthermore, the height of the bump or solder ball for flip chip connection must be higher than that of a normal semiconductor chip. When combined with the increase in the total length of the wire, the wire length is 2 to 4 mm. Causes a wire short or a short due to a chip touch.

In the method of providing electrodes on the back surface or side surface of the semiconductor chip, a hole penetrating the semiconductor chip is provided for each electrode by etching or laser, and the exposed side surface and back surface are formed of an inorganic material such as SiO ₂ or SiN by the CVD method. Or an insulating film made of an organic material such as polyimide resin or epoxy resin, and then provided with Cr, Ti, Pd, etc., with the wiring from the electrode pad as an adhesion layer, Ni, Cu, Au The process of forming by patterning after providing conductor layers, such as, is needed. In addition, if all the electrodes are drawn out and connected to the substrate on the back surface of the semiconductor chip, the number of connection points is not basically reduced, and the same as described above for a multi-pin semiconductor chip. It will cause problems.

  The present invention has been made in view of the above-mentioned unsolved problems of the prior art, and efficiently utilizes the wiring portion of the wiring board in response to the increase in the number of pins of the semiconductor chip, thereby reducing the size of the package. An object of the present invention is to provide a semiconductor device capable of promoting the above.

  In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor chip having a circuit element and a plurality of terminal electrodes on a main surface, and a wiring portion connected to the plurality of terminal electrodes of the semiconductor chip. A wiring board, and the semiconductor chip is mounted on the wiring board with the main surface as an upper surface, and a part of the plurality of terminal electrodes is connected to a wiring portion of the wiring board by wire bonding, The remaining terminal electrodes are drawn to the surface opposite to the main surface by a through wiring portion that penetrates the semiconductor chip, and then connected to the wiring portion of the wiring board.

  With regard to the connection method between the multi-pin semiconductor chip and the wiring board, the connection portions are dispersed on the two surfaces of the semiconductor chip, thereby reducing the number of connection portions on a single surface, for example, by wire bonding. As a result, by expanding the pitch of the connecting portion, the restriction corresponding to the wiring pitch on the wiring board is relaxed. As a result, the difference between the pitch of the terminal electrodes connected on the main surface of the semiconductor chip and the pitch of the wiring portion of the wiring board can be reduced, and the spread of the connecting portion due to wire bonding can be suppressed.

  Similarly, in the flip-chip connection, the pitch of the wiring portions connected on the back surface side of the semiconductor chip is widened so that the wiring pitch can be manufactured. In the case of C4 connection, it is possible to draw out wiring from between the electrodes by reducing the number of columns of connection portions in a matrix arrangement or increasing the interval.

  As shown in FIG. 1, the semiconductor chip 1 has electrode pads 2a and 2b as a plurality of terminal electrodes on the first surface, which is the main surface on which the circuit elements are formed, and approximately half of the electrode pads 2a pass therethrough. It is drawn out to the second surface opposite to the main surface of the semiconductor chip 1 (back surface) via the wiring portion 3 and connected to the back surface connection wiring pattern 5 of the interposer substrate 4 that is a wiring substrate for the package by pressure contact. The electrode pads 2 b remaining on the surface and the surface connection wiring pattern 6 of the interposer substrate 4 are connected by wire bonding 7. After all the electrode pads 2a and 2b of the semiconductor chip 1 and the connection wiring patterns 5 and 6 which are wiring portions of the interposer substrate 4 are electrically connected, the semiconductor chip 1 is sealed with an epoxy resin, for example, Then, a solder ball is joined to an electrode for connection with a mother board provided on the back surface of the interposer substrate 4 to obtain a semiconductor package.

  As shown in FIG. 2A, on the back side of the semiconductor chip 1, the adhesive 8 disposed between the interposer substrate 4 is pressurized and cured, and the compressive stress of the adhesive 8 is used. The electrode pad 2 a drawn out to the back surface of the semiconductor chip 1 is connected to the back surface side connection wiring pattern 5. Since the underfill material is not injected after the connection as in the flip chip connection or the C4 connection, it is not necessary to provide a wide injection region or a region for underfill flowing out around the semiconductor chip 1.

  Since the outflow amount of the adhesive 8 to the outside of the semiconductor chip 1 is (semiconductor chip area × push-in amount), it is extremely small, and the amount of the adhesive 8 supplied in advance can be controlled. Therefore, the outflow amount can be controlled stably. In the case where the adhesive 8 is an anisotropic conductive film or NCP (Non Conductive Past), the curing reaction starts simultaneously with the discharge due to the softening of the resin at the time of bonding, so that the injection property is improved like an underfill. Therefore, since the flow does not continue due to the reduced viscosity, the outflow amount to the outside of the semiconductor chip 1 is extremely small.

  Therefore, as shown in FIG. 2B, the surface connection wiring pattern 6 of the interposer substrate 4 connected to the electrode 2b remaining on the main surface of the semiconductor chip 1 can be provided in the vicinity of the semiconductor chip 1. By shortening the wire length of the wire bonding 7, it is possible to prevent drooling or wire shorting.

  In this way, by distributing the connection parts between the front and back surfaces of the semiconductor chip, the number of connection points on one surface is reduced, and the difference in connection pitch with the wiring board is reduced, so that the size is small, the performance is stable, and the cost is low. A simple semiconductor package can be realized. Furthermore, the semiconductor chip can be stably fixed to the wiring substrate by using an anisotropic conductive film, NCF, or the like that uses the compressive stress of the resin at the connection portion below the semiconductor chip size.

  As a result, the number of electrode pads of the semiconductor chip can be increased to provide a multi-pin semiconductor package or module at low cost.

  1 to 4 show a first embodiment. The semiconductor chip 1 has a chip size S shown in FIG. 3 of 6 mm, and the number of electrodes on the main surface, that is, the total number of the two sets of electrode pads 2a and 2b is 600. Therefore, the number of pads per side of the semiconductor chip 1 is 150 (= 600/4), and the pad pitch is 0.040 mm (= 6/150). Therefore, the pad pitch per row is set to 0.08 mm by forming the electrode pads 2a and 2b in a two-row configuration in a staggered arrangement. The semiconductor package of this embodiment is manufactured by the following process.

First, after the semiconductor chip 1 is in a wafer state, the wafer thickness is reduced to about 0.05 to 0.25 mm by back surface grinding, and then SiO ₂ or SiN is deposited on the ground back surface using CVD to obtain a thickness of 0. An insulating film 9 of 5 to 2 μm is provided on the entire back surface. Next, using an excimer laser, holes corresponding to the through-wiring portions 3 penetrating the wafer are opened by the number of electrode pads 2a with a diameter of 0.03 to 0.1 mm to the back side. The diameter of the hole to be opened is determined based on two pitches based on the wafer thickness and the number of electrode pads. The aspect ratio (wafer thickness / hole diameter) is 5 or less with respect to the wafer thickness and less than the pitch with respect to the pitch. Any hole diameter may be selected.

  In this embodiment, since half of the electrode pads 2a are drawn out to the back surface, 300 pieces (= 600/2) per chip are opened with a hole diameter of 0.05 mm and a wafer thickness of 0.15 mm.

Thereafter, SiO ₂ or SiN is again deposited by 0.5 to 1.0 μm on the side wall of the hole by CVD to form an insulating film 9 on the side wall of the hole. Next, the entire surface of the wafer including the electrode pads 2a and 2b including the Al electrode is coated with Ni by several μm electroless plating using Pd as an undercoat layer, and then the front and back surfaces of the wafer with resist so that the portions used as wiring are exposed. After patterning, Au is deposited to about 0.5 to 2 μm by electrolytic plating using the Ni layer as a common electrode.

  Wiring from the electrode pad 2a on the front surface of the wafer to the back surface through the through wiring portion 3 by removing the exposed Ni and the Pd therebelow by using Au formed by electrolytic plating as an etching resist after peeling off the resist Wiring 10b (see FIGS. 2 and 4) on 10a and electrode pad 2b is formed.

  Thereafter, the wafer is divided into semiconductor chips 1 by a dicing saw to form the semiconductor chip 1 shown in FIG.

  Bumps (protrusions) 11 are formed by ball bonding as shown in FIG. 4B on the portion of the back surface connection wiring pattern 5 formed on the surface of the interposer substrate 4 to be connected to the electrode pads 2a of the semiconductor chip 1. The surface is flattened by stamping. Since the back surface connection wiring pattern 5 only needs to connect half of the electrode pads 2a per side as described above, the pitch is 0.08 mm, the wiring width is about 0.04 mm, and the flatness of the wiring can be sufficiently secured. Therefore, the bump height varies and no bonding failure occurs at the time of bonding. The bump height is in the range of 10 to 40 μm.

  An adhesive 8 made of an anisotropic conductive film is disposed in the region of the interposer substrate 4 on which the semiconductor chip 1 is mounted, the semiconductor chip 1 and the interposer substrate 4 are aligned, and then the semiconductor By heating and pressurizing the chip 1 to 150 ° C. to 200 ° C., the resin of the anisotropic conductive film is softened, and the conductive particles contained in the anisotropic conductive film are discharged except for the joints, and the heat of the resin Curing begins. Thus, the semiconductor chip 1 and the interposer substrate 4 are fixed, and the wiring 10a and the bump 11 of the electrode pad 2a on the back surface side are connected by pressure contact using the compressive stress at that time.

  The thickness of the anisotropic conductive film disposed as the adhesive 8 is a gap of 10 to 20 μm formed between the interposer substrate 4 and the semiconductor chip 1 via the bumps 11 after bonding. The reason for making it slightly thicker is to generate pressure for pushing conductive particles of several μm contained in the anisotropic conductive film by the flow of the resin and to secure a resin amount for embedding the uneven portion without gaps. is there. In this embodiment, the thickness of the anisotropic conductive film is 40 μm because the bump height is 30 μm and the gap is 25 μm.

Therefore, the amount of the anisotropic conductive film to be discharged is very small as 5.0 mm × 5.0 mm × (0.04 mm−0.025 mm) = 0.375 mm ³ , and discharge and curing are performed at the time of bonding. Since it is started at the same time, the outflow amount falls within 0.1 to 0.2 mm around the semiconductor chip 1.

  In this embodiment, since the wirings 10a and 10b are provided on both surfaces of the semiconductor chip 1, not only can both surfaces of the semiconductor chip 1 be adopted during alignment, but also the surface of the semiconductor chip 1 after bonding. By confirming the pattern, the positional accuracy can be confirmed, so that inspection at the time of manufacture can be easily performed.

  Next, half of the electrode pads 2b remaining on the surface of the semiconductor chip 1 mounted on the interposer substrate 4 and the surface connection wiring pattern 6 provided on the interposer substrate 4 are connected by wire bonding 7 using Au wire.

  If the pitch of the wiring pattern of the interposer substrate is the same with respect to the pad pitch of 0.08 mm on the chip surface, the area for connection is the same as one side of the semiconductor chip, but if the pitch of the wiring pattern is large, It spreads with the ratio of pad pitch and wiring pitch. Furthermore, this spread becomes larger with the number of connected pads. In general, since the Au wire diameter used for wire bonding is usually 20 to 25 μm, the connection wiring width is about 50 μm in consideration of positional deviation. Therefore, although the wiring pitch is 0.08 to 0.10, which is slightly larger than the pad pitch, in this embodiment, by reducing the number of connected pads by half, the spread is reduced and the length of the Au wire is reduced. Can be kept within the allowable range of 2 to 4 mm.

  Then, the semiconductor package which is a semiconductor device is obtained by sealing a semiconductor chip by transfer molding using sealing resin in which silica particles are contained in epoxy resin.

  In this example, electrode pad connection portions are distributed on both sides of the semiconductor chip, and the connection with the wiring substrate is performed from each side, thereby solving the problem in connection from the conventional electrode pad concentrated on one side, By reducing the burden on the wiring of the wiring board, a small semiconductor package can be realized at low cost.

  In this embodiment, bumps used for connection between the electrode connecting portion on the back side of the semiconductor chip and the interposer substrate are provided on the interposer substrate side. However, this may be provided on the semiconductor chip side.

  FIGS. 5 and 6 show the second embodiment. In this embodiment, in order to cope with the increase in the signal speed of the semiconductor chip 1, the purpose of shortening the connection of the signal lines is shown in FIG. As shown in (a), the electrode pads 2b in the active region of the semiconductor chip 1 are connected face down, while as shown in (b) of FIG. The electrode pads 2a of the power supply / GND line that continues to be turned are turned to the back side of the semiconductor chip 1, whereby the electrode pads 2a, 2b of the semiconductor chip 1 are dispersed and connected to the interposer substrate 4.

  FIG. 6 shows a process of mounting the semiconductor chip 1 on the interposer substrate 4. As shown in FIG. 6A, the semiconductor chip 1 manufactured in the same manner as in the first embodiment is turned upside down, as shown in FIG. Then, it is fixed to the interposer substrate 4 through the adhesive 8 and then connected by wire bonding 7.

  When the adhesive 8 is an NCP that does not contain an anisotropic conductive film or conductive particles, the connection resistance value is a pressure contact, so that it is high compared to an alloyed joint such as solder or wire bonding. The resistance value is not a problem as the impedance in the digital signal, and the L component can be reduced by shortening the wiring length. It is also possible to turn a signal from an analog circuit unit whose resistance component is a problem as a signal to be turned to the back surface. The other points are the same as those of the first embodiment, and a semiconductor package corresponding to a semiconductor chip of a multi-pin and high-speed signal can be provided at low cost.

  7 and 8 show a third embodiment. In this embodiment, as shown in FIGS. 7A and 7B, an NCF (Non Conductive Film) 12 is used in place of the adhesive 8 of Embodiment 1, and FIG. As shown in FIG. 4, after the semiconductor chip 1 is in a wafer state and the electrode pad 2a is drawn out through the through wiring portion 3 on the back surface of the wafer, the NCF 12 is bonded to the entire back surface of the wafer. Thereafter, the wafer is attached to a dicing tape, and the wafer and NCF 12 are simultaneously cut with a dicing saw. By cutting in this way, the semiconductor chip 1 having the NCF 12 having the same size as the chip size of the semiconductor chip 1 can be manufactured.

  Further, in the normal face-down connection, since the surfaces to be joined are covered with NCF, the target for positioning the surfaces to be joined cannot be recognized and cannot be joined. In addition, since the electrode pad exists, the back surface of the semiconductor chip can be joined with high accuracy by recognizing the pattern and the electrode pad on the surface of the semiconductor chip.

  This embodiment has an advantage that the NCF as a bonding material can be stably supplied to the semiconductor chip in advance, and the NCF bonding accuracy in the bonding process is not necessary. As a result, the amount of protrusion can be further reduced, and the connection part on the semiconductor chip surface side can be arranged close to the semiconductor chip, so that the semiconductor package can be further miniaturized.

1 is a schematic plan view showing Example 1. FIG. FIG. 2 is a cross-sectional view of the apparatus of FIG. 1, where (a) is a cross-sectional view taken along the back-side connection portion, and (b) is a cross-sectional view taken along the front-side connection portion. It is a top view which shows only the semiconductor chip of FIG. FIG. 5 is a process diagram illustrating an assembly process of Example 1. FIG. 2 shows a second embodiment, where (a) is a cross-sectional view taken along the back surface side connection portion, and (b) is a cross sectional view taken along the front surface side connection portion. FIG. 6 is a process diagram illustrating an assembly process of Example 2. FIGS. 3A and 3B show Example 3, in which FIG. 5A is a cross-sectional view taken along the back-side connection portion, and FIG. 5B is a cross-sectional view taken along the front-side connection portion. FIG. 10 is a process diagram illustrating an assembly process of Example 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2a, 2b Electrode pad 3 Through wiring part 4 Interposer board 5 Back surface connection wiring pattern 6 Surface connection wiring pattern 7 Wire bonding 8 Adhesive 9 Insulating film 11 Bump 12 NCF

Claims (3)

  A semiconductor chip having a circuit element and a plurality of terminal electrodes on a main surface; and a wiring board having a wiring portion connected to the plurality of terminal electrodes of the semiconductor chip, wherein the semiconductor chip has the main chip Mounted on the wiring board with the surface as an upper surface, a part of the plurality of terminal electrodes is connected to a wiring part of the wiring board by wire bonding, and the remaining terminal electrodes pass through the semiconductor chip. The semiconductor device is pulled out to a surface opposite to the main surface by and is connected to a wiring portion of the wiring board.   The semiconductor device according to claim 1, wherein the remaining terminal electrodes are pressed and connected to a wiring portion of the wiring board.   A semiconductor chip having a circuit element and a plurality of terminal electrodes on a main surface; and a wiring board having a wiring portion connected to the plurality of terminal electrodes of the semiconductor chip, wherein the semiconductor chip has the main chip Mounted on the wiring board with the surface as the bottom surface, and a part of the plurality of terminal electrodes is drawn out to the surface opposite to the main surface by a through wiring portion that penetrates the semiconductor chip, and then by wire bonding A semiconductor device, wherein the semiconductor device is connected to a wiring portion of the wiring substrate, and the remaining terminal electrodes are pressed and connected to the wiring portion of the wiring substrate.

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